* [PATCH AUTOSEL 5.5 008/542] pinctrl: baytrail: Allocate IRQ chip dynamic [not found] <20200214154854.6746-1-sashal@kernel.org> @ 2020-02-14 15:40 ` Sasha Levin 2020-02-14 15:40 ` [PATCH AUTOSEL 5.5 030/542] pinctrl: sh-pfc: r8a77965: Fix DU_DOTCLKIN3 drive/bias control Sasha Levin ` (9 subsequent siblings) 10 siblings, 0 replies; 13+ messages in thread From: Sasha Levin @ 2020-02-14 15:40 UTC (permalink / raw) To: linux-kernel, stable Cc: Andy Shevchenko, Mika Westerberg, Sasha Levin, linux-gpio From: Andy Shevchenko <andriy.shevchenko@linux.intel.com> [ Upstream commit 539d8bde72c22d760013bf81436d6bb94eb67aed ] Keeping the IRQ chip definition static shares it with multiple instances of the GPIO chip in the system. This is bad and now we get this warning from GPIO library: "detected irqchip that is shared with multiple gpiochips: please fix the driver." Hence, move the IRQ chip definition from being driver static into the struct intel_pinctrl. So a unique IRQ chip is used for each GPIO chip instance. Fixes: 9f573b98ca50 ("pinctrl: baytrail: Update irq chip operations") Depends-on: ca8a958e2acb ("pinctrl: baytrail: Pass irqchip when adding gpiochip") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Sasha Levin <sashal@kernel.org> --- drivers/pinctrl/intel/pinctrl-baytrail.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 55141d5de29e6..72ffd19448e50 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -107,6 +107,7 @@ struct byt_gpio_pin_context { struct byt_gpio { struct gpio_chip chip; + struct irq_chip irqchip; struct platform_device *pdev; struct pinctrl_dev *pctl_dev; struct pinctrl_desc pctl_desc; @@ -1395,15 +1396,6 @@ static int byt_irq_type(struct irq_data *d, unsigned int type) return 0; } -static struct irq_chip byt_irqchip = { - .name = "BYT-GPIO", - .irq_ack = byt_irq_ack, - .irq_mask = byt_irq_mask, - .irq_unmask = byt_irq_unmask, - .irq_set_type = byt_irq_type, - .flags = IRQCHIP_SKIP_SET_WAKE, -}; - static void byt_gpio_irq_handler(struct irq_desc *desc) { struct irq_data *data = irq_desc_get_irq_data(desc); @@ -1551,8 +1543,15 @@ static int byt_gpio_probe(struct byt_gpio *vg) if (irq_rc && irq_rc->start) { struct gpio_irq_chip *girq; + vg->irqchip.name = "BYT-GPIO", + vg->irqchip.irq_ack = byt_irq_ack, + vg->irqchip.irq_mask = byt_irq_mask, + vg->irqchip.irq_unmask = byt_irq_unmask, + vg->irqchip.irq_set_type = byt_irq_type, + vg->irqchip.flags = IRQCHIP_SKIP_SET_WAKE, + girq = &gc->irq; - girq->chip = &byt_irqchip; + girq->chip = &vg->irqchip; girq->init_hw = byt_gpio_irq_init_hw; girq->parent_handler = byt_gpio_irq_handler; girq->num_parents = 1; -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH AUTOSEL 5.5 030/542] pinctrl: sh-pfc: r8a77965: Fix DU_DOTCLKIN3 drive/bias control [not found] <20200214154854.6746-1-sashal@kernel.org> 2020-02-14 15:40 ` [PATCH AUTOSEL 5.5 008/542] pinctrl: baytrail: Allocate IRQ chip dynamic Sasha Levin @ 2020-02-14 15:40 ` Sasha Levin 2020-02-14 15:40 ` [PATCH AUTOSEL 5.5 035/542] pinctrl: sh-pfc: sh7264: Fix CAN function GPIOs Sasha Levin ` (8 subsequent siblings) 10 siblings, 0 replies; 13+ messages in thread From: Sasha Levin @ 2020-02-14 15:40 UTC (permalink / raw) To: linux-kernel, stable Cc: Geert Uytterhoeven, Sasha Levin, linux-renesas-soc, linux-gpio From: Geert Uytterhoeven <geert+renesas@glider.be> [ Upstream commit a34cd9dfd03fa9ec380405969f1d638bc63b8d63 ] R-Car Gen3 Hardware Manual Errata for Rev. 2.00 of October 24, 2019 changed the configuration bits for drive and bias control for the DU_DOTCLKIN3 pin on R-Car M3-N, to match the same pin on R-Car H3. Update the driver to reflect this. After this, the handling of drive and bias control for the various DU_DOTCLKINx pins is consistent across all of the R-Car H3, M3-W, M3-W+, and M3-N SoCs. Fixes: 86c045c2e4201e94 ("pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20191113101653.28428-1-geert+renesas@glider.be Signed-off-by: Sasha Levin <sashal@kernel.org> --- drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c index 8bdf33c807f6c..6616f5210b9d9 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c @@ -5998,7 +5998,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ } }, { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { - { PIN_DU_DOTCLKIN3, 28, 2 }, /* DU_DOTCLKIN3 */ + { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */ { PIN_FSCLKST, 20, 2 }, /* FSCLKST */ { PIN_TMS, 4, 2 }, /* TMS */ } }, @@ -6254,8 +6254,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ } }, { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { - [ 0] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */ - [ 1] = SH_PFC_PIN_NONE, + [ 0] = SH_PFC_PIN_NONE, + [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */ [ 2] = PIN_FSCLKST, /* FSCLKST */ [ 3] = PIN_EXTALR, /* EXTALR*/ [ 4] = PIN_TRST_N, /* TRST# */ -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH AUTOSEL 5.5 035/542] pinctrl: sh-pfc: sh7264: Fix CAN function GPIOs [not found] <20200214154854.6746-1-sashal@kernel.org> 2020-02-14 15:40 ` [PATCH AUTOSEL 5.5 008/542] pinctrl: baytrail: Allocate IRQ chip dynamic Sasha Levin 2020-02-14 15:40 ` [PATCH AUTOSEL 5.5 030/542] pinctrl: sh-pfc: r8a77965: Fix DU_DOTCLKIN3 drive/bias control Sasha Levin @ 2020-02-14 15:40 ` Sasha Levin 2020-02-14 15:40 ` [PATCH AUTOSEL 5.5 050/542] gpio: gpio-grgpio: fix possible sleep-in-atomic-context bugs in grgpio_irq_map/unmap() Sasha Levin ` (7 subsequent siblings) 10 siblings, 0 replies; 13+ messages in thread From: Sasha Levin @ 2020-02-14 15:40 UTC (permalink / raw) To: linux-kernel, stable Cc: Geert Uytterhoeven, Sasha Levin, linux-renesas-soc, linux-gpio From: Geert Uytterhoeven <geert+renesas@glider.be> [ Upstream commit 55b1cb1f03ad5eea39897d0c74035e02deddcff2 ] pinmux_func_gpios[] contains a hole due to the missing function GPIO definition for the "CTX0&CTX1" signal, which is the logical "AND" of the two CAN outputs. Fix this by: - Renaming CRX0_CRX1_MARK to CTX0_CTX1_MARK, as PJ2MD[2:0]=010 configures the combined "CTX0&CTX1" output signal, - Renaming CRX0X1_MARK to CRX0_CRX1_MARK, as PJ3MD[1:0]=10 configures the shared "CRX0/CRX1" input signal, which is fed to both CAN inputs, - Adding the missing function GPIO definition for "CTX0&CTX1" to pinmux_func_gpios[], - Moving all CAN enums next to each other. See SH7262 Group, SH7264 Group User's Manual: Hardware, Rev. 4.00: [1] Figure 1.2 (3) (Pin Assignment for the SH7264 Group (1-Mbyte Version), [2] Figure 1.2 (4) Pin Assignment for the SH7264 Group (640-Kbyte Version, [3] Table 1.4 List of Pins, [4] Figure 20.29 Connection Example when Using This Module as 1-Channel Module (64 Mailboxes x 1 Channel), [5] Table 32.10 Multiplexed Pins (Port J), [6] Section 32.2.30 (3) Port J Control Register 0 (PJCR0). Note that the last 2 disagree about PJ2MD[2:0], which is probably the root cause of this bug. But considering [4], "CTx0&CTx1" in [5] must be correct, and "CRx0&CRx1" in [6] must be wrong. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20191218194812.12741-4-geert+renesas@glider.be Signed-off-by: Sasha Levin <sashal@kernel.org> --- drivers/pinctrl/sh-pfc/pfc-sh7264.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c index 4a95867deb8af..5a026601d4f9a 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c @@ -497,17 +497,15 @@ enum { SD_WP_MARK, SD_CLK_MARK, SD_CMD_MARK, CRX0_MARK, CRX1_MARK, CTX0_MARK, CTX1_MARK, + CRX0_CRX1_MARK, CTX0_CTX1_MARK, PWM1A_MARK, PWM1B_MARK, PWM1C_MARK, PWM1D_MARK, PWM1E_MARK, PWM1F_MARK, PWM1G_MARK, PWM1H_MARK, PWM2A_MARK, PWM2B_MARK, PWM2C_MARK, PWM2D_MARK, PWM2E_MARK, PWM2F_MARK, PWM2G_MARK, PWM2H_MARK, IERXD_MARK, IETXD_MARK, - CRX0_CRX1_MARK, WDTOVF_MARK, - CRX0X1_MARK, - /* DMAC */ TEND0_MARK, DACK0_MARK, DREQ0_MARK, TEND1_MARK, DACK1_MARK, DREQ1_MARK, @@ -995,12 +993,12 @@ static const u16 pinmux_data[] = { PINMUX_DATA(PJ3_DATA, PJ3MD_00), PINMUX_DATA(CRX1_MARK, PJ3MD_01), - PINMUX_DATA(CRX0X1_MARK, PJ3MD_10), + PINMUX_DATA(CRX0_CRX1_MARK, PJ3MD_10), PINMUX_DATA(IRQ1_PJ_MARK, PJ3MD_11), PINMUX_DATA(PJ2_DATA, PJ2MD_000), PINMUX_DATA(CTX1_MARK, PJ2MD_001), - PINMUX_DATA(CRX0_CRX1_MARK, PJ2MD_010), + PINMUX_DATA(CTX0_CTX1_MARK, PJ2MD_010), PINMUX_DATA(CS2_MARK, PJ2MD_011), PINMUX_DATA(SCK0_MARK, PJ2MD_100), PINMUX_DATA(LCD_M_DISP_MARK, PJ2MD_101), @@ -1245,6 +1243,7 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(CTX1), GPIO_FN(CRX1), GPIO_FN(CTX0), + GPIO_FN(CTX0_CTX1), GPIO_FN(CRX0), GPIO_FN(CRX0_CRX1), -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH AUTOSEL 5.5 050/542] gpio: gpio-grgpio: fix possible sleep-in-atomic-context bugs in grgpio_irq_map/unmap() [not found] <20200214154854.6746-1-sashal@kernel.org> ` (2 preceding siblings ...) 2020-02-14 15:40 ` [PATCH AUTOSEL 5.5 035/542] pinctrl: sh-pfc: sh7264: Fix CAN function GPIOs Sasha Levin @ 2020-02-14 15:40 ` Sasha Levin 2020-02-14 15:40 ` [PATCH AUTOSEL 5.5 060/542] pinctrl: baytrail: Do not clear IRQ flags on direct-irq enabled pins Sasha Levin ` (6 subsequent siblings) 10 siblings, 0 replies; 13+ messages in thread From: Sasha Levin @ 2020-02-14 15:40 UTC (permalink / raw) To: linux-kernel, stable; +Cc: Jia-Ju Bai, Linus Walleij, Sasha Levin, linux-gpio From: Jia-Ju Bai <baijiaju1990@gmail.com> [ Upstream commit e36eaf94be8f7bc4e686246eed3cf92d845e2ef8 ] The driver may sleep while holding a spinlock. The function call path (from bottom to top) in Linux 4.19 is: drivers/gpio/gpio-grgpio.c, 261: request_irq in grgpio_irq_map drivers/gpio/gpio-grgpio.c, 255: _raw_spin_lock_irqsave in grgpio_irq_map drivers/gpio/gpio-grgpio.c, 318: free_irq in grgpio_irq_unmap drivers/gpio/gpio-grgpio.c, 299: _raw_spin_lock_irqsave in grgpio_irq_unmap request_irq() and free_irq() can sleep at runtime. To fix these bugs, request_irq() and free_irq() are called without holding the spinlock. These bugs are found by a static analysis tool STCheck written by myself. Signed-off-by: Jia-Ju Bai <baijiaju1990@gmail.com> Link: https://lore.kernel.org/r/20191218132605.10594-1-baijiaju1990@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org> --- drivers/gpio/gpio-grgpio.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/gpio-grgpio.c b/drivers/gpio/gpio-grgpio.c index 08234e64993a9..3224933f4c8f4 100644 --- a/drivers/gpio/gpio-grgpio.c +++ b/drivers/gpio/gpio-grgpio.c @@ -253,17 +253,16 @@ static int grgpio_irq_map(struct irq_domain *d, unsigned int irq, lirq->irq = irq; uirq = &priv->uirqs[lirq->index]; if (uirq->refcnt == 0) { + spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); ret = request_irq(uirq->uirq, grgpio_irq_handler, 0, dev_name(priv->dev), priv); if (ret) { dev_err(priv->dev, "Could not request underlying irq %d\n", uirq->uirq); - - spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); - return ret; } + spin_lock_irqsave(&priv->gc.bgpio_lock, flags); } uirq->refcnt++; @@ -309,8 +308,11 @@ static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq) if (index >= 0) { uirq = &priv->uirqs[lirq->index]; uirq->refcnt--; - if (uirq->refcnt == 0) + if (uirq->refcnt == 0) { + spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); free_irq(uirq->uirq, priv); + return; + } } spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH AUTOSEL 5.5 060/542] pinctrl: baytrail: Do not clear IRQ flags on direct-irq enabled pins [not found] <20200214154854.6746-1-sashal@kernel.org> ` (3 preceding siblings ...) 2020-02-14 15:40 ` [PATCH AUTOSEL 5.5 050/542] gpio: gpio-grgpio: fix possible sleep-in-atomic-context bugs in grgpio_irq_map/unmap() Sasha Levin @ 2020-02-14 15:40 ` Sasha Levin 2020-02-14 15:41 ` [PATCH AUTOSEL 5.5 100/542] pinctrl: qcom: Don't lock around irq_set_irq_wake() Sasha Levin ` (5 subsequent siblings) 10 siblings, 0 replies; 13+ messages in thread From: Sasha Levin @ 2020-02-14 15:40 UTC (permalink / raw) To: linux-kernel, stable Cc: Hans de Goede, Mika Westerberg, Linus Walleij, Andy Shevchenko, Sasha Levin, linux-gpio From: Hans de Goede <hdegoede@redhat.com> [ Upstream commit a23680594da7a9e2696dbcf4f023e9273e2fa40b ] Suspending Goodix touchscreens requires changing the interrupt pin to output before sending them a power-down command. Followed by wiggling the interrupt pin to wake the device up, after which it is put back in input mode. On Bay Trail devices with a Goodix touchscreen direct-irq mode is used in combination with listing the pin as a normal GpioIo resource. This works fine, until the goodix driver gets rmmod-ed and then insmod-ed again. In this case byt_gpio_disable_free() calls byt_gpio_clear_triggering() which clears the IRQ flags and after that the (direct) IRQ no longer triggers. This commit fixes this by adding a check for the BYT_DIRECT_IRQ_EN flag to byt_gpio_clear_triggering(). Note that byt_gpio_clear_triggering() only gets called from byt_gpio_disable_free() for direct-irq enabled pins, as these are excluded from the irq_valid mask by byt_init_irq_valid_mask(). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Sasha Levin <sashal@kernel.org> --- drivers/pinctrl/intel/pinctrl-baytrail.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 72ffd19448e50..ce9cf50121bd5 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -753,7 +753,13 @@ static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset) raw_spin_lock_irqsave(&byt_lock, flags); value = readl(reg); - value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); + + /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */ + if (value & BYT_DIRECT_IRQ_EN) + /* nothing to do */ ; + else + value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); + writel(value, reg); raw_spin_unlock_irqrestore(&byt_lock, flags); } -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH AUTOSEL 5.5 100/542] pinctrl: qcom: Don't lock around irq_set_irq_wake() [not found] <20200214154854.6746-1-sashal@kernel.org> ` (4 preceding siblings ...) 2020-02-14 15:40 ` [PATCH AUTOSEL 5.5 060/542] pinctrl: baytrail: Do not clear IRQ flags on direct-irq enabled pins Sasha Levin @ 2020-02-14 15:41 ` Sasha Levin 2020-02-14 15:44 ` [PATCH AUTOSEL 5.5 272/542] pinctrl: sh-pfc: r8a7778: Fix duplicate SDSELF_B and SD1_CLK_B Sasha Levin ` (4 subsequent siblings) 10 siblings, 0 replies; 13+ messages in thread From: Sasha Levin @ 2020-02-14 15:41 UTC (permalink / raw) To: linux-kernel, stable Cc: Stephen Boyd, Douglas Anderson, Brian Masney, Lina Iyer, Maulik Shah, Bjorn Andersson, Linus Walleij, Sasha Levin, linux-arm-msm, linux-gpio From: Stephen Boyd <swboyd@chromium.org> [ Upstream commit 1d44616e7549d0154c1224a3eee3c407029294dc ] We don't need to hold the local pinctrl lock here to set irq wake on the summary irq line. Doing so only leads to lockdep warnings instead of protecting us from anything. Remove the locking. WARNING: possible circular locking dependency detected 5.4.11 #2 Tainted: G W ------------------------------------------------------ cat/3083 is trying to acquire lock: ffffff81f4fa58c0 (&irq_desc_lock_class){-.-.}, at: __irq_get_desc_lock+0x64/0x94 but task is already holding lock: ffffff81f4880c18 (&pctrl->lock){-.-.}, at: msm_gpio_irq_set_wake+0x48/0x7c which lock already depends on the new lock. the existing dependency chain (in reverse order) is: -> #1 (&pctrl->lock){-.-.}: _raw_spin_lock_irqsave+0x64/0x80 msm_gpio_irq_ack+0x68/0xf4 __irq_do_set_handler+0xe0/0x180 __irq_set_handler+0x60/0x9c irq_domain_set_info+0x90/0xb4 gpiochip_hierarchy_irq_domain_alloc+0x110/0x200 __irq_domain_alloc_irqs+0x130/0x29c irq_create_fwspec_mapping+0x1f0/0x300 irq_create_of_mapping+0x70/0x98 of_irq_get+0xa4/0xd4 spi_drv_probe+0x4c/0xb0 really_probe+0x138/0x3f0 driver_probe_device+0x70/0x140 __device_attach_driver+0x9c/0x110 bus_for_each_drv+0x88/0xd0 __device_attach+0xb0/0x160 device_initial_probe+0x20/0x2c bus_probe_device+0x34/0x94 device_add+0x35c/0x3f0 spi_add_device+0xbc/0x194 of_register_spi_devices+0x2c8/0x408 spi_register_controller+0x57c/0x6fc spi_geni_probe+0x260/0x328 platform_drv_probe+0x90/0xb0 really_probe+0x138/0x3f0 driver_probe_device+0x70/0x140 device_driver_attach+0x4c/0x6c __driver_attach+0xcc/0x154 bus_for_each_dev+0x84/0xcc driver_attach+0x2c/0x38 bus_add_driver+0x108/0x1fc driver_register+0x64/0xf8 __platform_driver_register+0x4c/0x58 spi_geni_driver_init+0x1c/0x24 do_one_initcall+0x1a4/0x3e8 do_initcall_level+0xb4/0xcc do_basic_setup+0x30/0x48 kernel_init_freeable+0x124/0x1a8 kernel_init+0x14/0x100 ret_from_fork+0x10/0x18 -> #0 (&irq_desc_lock_class){-.-.}: __lock_acquire+0xeb4/0x2388 lock_acquire+0x1cc/0x210 _raw_spin_lock_irqsave+0x64/0x80 __irq_get_desc_lock+0x64/0x94 irq_set_irq_wake+0x40/0x144 msm_gpio_irq_set_wake+0x5c/0x7c set_irq_wake_real+0x40/0x5c irq_set_irq_wake+0x70/0x144 cros_ec_rtc_suspend+0x38/0x4c platform_pm_suspend+0x34/0x60 dpm_run_callback+0x64/0xcc __device_suspend+0x310/0x41c dpm_suspend+0xf8/0x298 dpm_suspend_start+0x84/0xb4 suspend_devices_and_enter+0xbc/0x620 pm_suspend+0x210/0x348 state_store+0xb0/0x108 kobj_attr_store+0x14/0x24 sysfs_kf_write+0x4c/0x64 kernfs_fop_write+0x15c/0x1fc __vfs_write+0x54/0x18c vfs_write+0xe4/0x1a4 ksys_write+0x7c/0xe4 __arm64_sys_write+0x20/0x2c el0_svc_common+0xa8/0x160 el0_svc_handler+0x7c/0x98 el0_svc+0x8/0xc other info that might help us debug this: Possible unsafe locking scenario: CPU0 CPU1 ---- ---- lock(&pctrl->lock); lock(&irq_desc_lock_class); lock(&pctrl->lock); lock(&irq_desc_lock_class); *** DEADLOCK *** 7 locks held by cat/3083: #0: ffffff81f06d1420 (sb_writers#7){.+.+}, at: vfs_write+0xd0/0x1a4 #1: ffffff81c8935680 (&of->mutex){+.+.}, at: kernfs_fop_write+0x12c/0x1fc #2: ffffff81f4c322f0 (kn->count#337){.+.+}, at: kernfs_fop_write+0x134/0x1fc #3: ffffffe89a641d60 (system_transition_mutex){+.+.}, at: pm_suspend+0x108/0x348 #4: ffffff81f190e970 (&dev->mutex){....}, at: __device_suspend+0x168/0x41c #5: ffffff81f183d8c0 (lock_class){-.-.}, at: __irq_get_desc_lock+0x64/0x94 #6: ffffff81f4880c18 (&pctrl->lock){-.-.}, at: msm_gpio_irq_set_wake+0x48/0x7c stack backtrace: CPU: 4 PID: 3083 Comm: cat Tainted: G W 5.4.11 #2 Hardware name: Google Cheza (rev3+) (DT) Call trace: dump_backtrace+0x0/0x174 show_stack+0x20/0x2c dump_stack+0xc8/0x124 print_circular_bug+0x2ac/0x2c4 check_noncircular+0x1a0/0x1a8 __lock_acquire+0xeb4/0x2388 lock_acquire+0x1cc/0x210 _raw_spin_lock_irqsave+0x64/0x80 __irq_get_desc_lock+0x64/0x94 irq_set_irq_wake+0x40/0x144 msm_gpio_irq_set_wake+0x5c/0x7c set_irq_wake_real+0x40/0x5c irq_set_irq_wake+0x70/0x144 cros_ec_rtc_suspend+0x38/0x4c platform_pm_suspend+0x34/0x60 dpm_run_callback+0x64/0xcc __device_suspend+0x310/0x41c dpm_suspend+0xf8/0x298 dpm_suspend_start+0x84/0xb4 suspend_devices_and_enter+0xbc/0x620 pm_suspend+0x210/0x348 state_store+0xb0/0x108 kobj_attr_store+0x14/0x24 sysfs_kf_write+0x4c/0x64 kernfs_fop_write+0x15c/0x1fc __vfs_write+0x54/0x18c vfs_write+0xe4/0x1a4 ksys_write+0x7c/0xe4 __arm64_sys_write+0x20/0x2c el0_svc_common+0xa8/0x160 el0_svc_handler+0x7c/0x98 el0_svc+0x8/0xc Fixes: 6aced33f4974 ("pinctrl: msm: drop wake_irqs bitmap") Cc: Douglas Anderson <dianders@chromium.org> Cc: Brian Masney <masneyb@onstation.org> Cc: Lina Iyer <ilina@codeaurora.org> Cc: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20200121180950.36959-1-swboyd@chromium.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org> --- drivers/pinctrl/qcom/pinctrl-msm.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 5d6f9f61ce02c..9a8daa256a321 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -960,7 +960,6 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct msm_pinctrl *pctrl = gpiochip_get_data(gc); - unsigned long flags; /* * While they may not wake up when the TLMM is powered off, @@ -971,12 +970,8 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) if (d->parent_data) irq_chip_set_wake_parent(d, on); - raw_spin_lock_irqsave(&pctrl->lock, flags); - irq_set_irq_wake(pctrl->irq, on); - raw_spin_unlock_irqrestore(&pctrl->lock, flags); - return 0; } -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH AUTOSEL 5.5 272/542] pinctrl: sh-pfc: r8a7778: Fix duplicate SDSELF_B and SD1_CLK_B [not found] <20200214154854.6746-1-sashal@kernel.org> ` (5 preceding siblings ...) 2020-02-14 15:41 ` [PATCH AUTOSEL 5.5 100/542] pinctrl: qcom: Don't lock around irq_set_irq_wake() Sasha Levin @ 2020-02-14 15:44 ` Sasha Levin 2020-02-14 15:44 ` [PATCH AUTOSEL 5.5 273/542] pinctrl: sh-pfc: sh7269: Fix CAN function GPIOs Sasha Levin ` (3 subsequent siblings) 10 siblings, 0 replies; 13+ messages in thread From: Sasha Levin @ 2020-02-14 15:44 UTC (permalink / raw) To: linux-kernel, stable Cc: Geert Uytterhoeven, Sasha Levin, linux-renesas-soc, linux-gpio From: Geert Uytterhoeven <geert+renesas@glider.be> [ Upstream commit 805f635703b2562b5ddd822c62fc9124087e5dd5 ] The FN_SDSELF_B and FN_SD1_CLK_B enum IDs are used twice, which means one set of users must be wrong. Replace them by the correct enum IDs. Fixes: 87f8c988636db0d4 ("sh-pfc: Add r8a7778 pinmux support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20191218194812.12741-2-geert+renesas@glider.be Signed-off-by: Sasha Levin <sashal@kernel.org> --- drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c index 24866a5958aee..a9875038ed9b6 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c @@ -2305,7 +2305,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_ATAG0_A, 0, FN_REMOCON_B, 0, /* IP0_11_8 [4] */ FN_SD1_DAT2_A, FN_MMC_D2, 0, FN_BS, - FN_ATADIR0_A, 0, FN_SDSELF_B, 0, + FN_ATADIR0_A, 0, FN_SDSELF_A, 0, FN_PWM4_B, 0, 0, 0, 0, 0, 0, 0, /* IP0_7_5 [3] */ @@ -2349,7 +2349,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_TS_SDAT0_A, 0, 0, 0, 0, 0, 0, 0, /* IP1_10_8 [3] */ - FN_SD1_CLK_B, FN_MMC_D6, 0, FN_A24, + FN_SD1_CD_A, FN_MMC_D6, 0, FN_A24, FN_DREQ1_A, 0, FN_HRX0_B, FN_TS_SPSYNC0_A, /* IP1_7_5 [3] */ FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A, -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH AUTOSEL 5.5 273/542] pinctrl: sh-pfc: sh7269: Fix CAN function GPIOs [not found] <20200214154854.6746-1-sashal@kernel.org> ` (6 preceding siblings ...) 2020-02-14 15:44 ` [PATCH AUTOSEL 5.5 272/542] pinctrl: sh-pfc: r8a7778: Fix duplicate SDSELF_B and SD1_CLK_B Sasha Levin @ 2020-02-14 15:44 ` Sasha Levin 2020-02-14 15:45 ` [PATCH AUTOSEL 5.5 361/542] gpiolib: Set lockdep class for hierarchical irq domains Sasha Levin ` (2 subsequent siblings) 10 siblings, 0 replies; 13+ messages in thread From: Sasha Levin @ 2020-02-14 15:44 UTC (permalink / raw) To: linux-kernel, stable Cc: Geert Uytterhoeven, Sasha Levin, linux-sh, linux-renesas-soc, linux-gpio From: Geert Uytterhoeven <geert+renesas@glider.be> [ Upstream commit 02aeb2f21530c98fc3ca51028eda742a3fafbd9f ] pinmux_func_gpios[] contains a hole due to the missing function GPIO definition for the "CTX0&CTX1" signal, which is the logical "AND" of the first two CAN outputs. A closer look reveals other issues: - Some functionality is available on alternative pins, but the PINMUX_DATA() entries is using the wrong marks, - Several configurations are missing. Fix this by: - Renaming CTX0CTX1CTX2_MARK, CRX0CRX1_PJ22_MARK, and CRX0CRX1CRX2_PJ20_MARK to CTX0_CTX1_CTX2_MARK, CRX0_CRX1_PJ22_MARK, resp. CRX0_CRX1_CRX2_PJ20_MARK for consistency with the corresponding enum IDs, - Adding all missing enum IDs and marks, - Use the right (*_PJ2x) variants for alternative pins, - Adding all missing configurations to pinmux_data[], - Adding all missing function GPIO definitions to pinmux_func_gpios[]. See SH7268 Group, SH7269 Group User’s Manual: Hardware, Rev. 2.00: [1] Table 1.4 List of Pins [2] Figure 23.29 Connection Example when Using Channels 0 and 1 as One Channel (64 Mailboxes × 1 Channel) and Channel 2 as One Channel (32 Mailboxes × 1 Channel), [3] Figure 23.30 Connection Example when Using Channels 0, 1, and 2 as One Channel (96 Mailboxes × 1 Channel), [4] Table 48.3 Multiplexed Pins (Port B), [5] Table 48.4 Multiplexed Pins (Port C), [6] Table 48.10 Multiplexed Pins (Port J), [7] Section 48.2.4 Port B Control Registers 0 to 5 (PBCR0 to PBCR5). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20191218194812.12741-5-geert+renesas@glider.be Signed-off-by: Sasha Levin <sashal@kernel.org> --- arch/sh/include/cpu-sh2a/cpu/sh7269.h | 11 ++++++-- drivers/pinctrl/sh-pfc/pfc-sh7269.c | 39 ++++++++++++++++++--------- 2 files changed, 36 insertions(+), 14 deletions(-) diff --git a/arch/sh/include/cpu-sh2a/cpu/sh7269.h b/arch/sh/include/cpu-sh2a/cpu/sh7269.h index d516e5d488180..b887cc402b712 100644 --- a/arch/sh/include/cpu-sh2a/cpu/sh7269.h +++ b/arch/sh/include/cpu-sh2a/cpu/sh7269.h @@ -78,8 +78,15 @@ enum { GPIO_FN_WDTOVF, /* CAN */ - GPIO_FN_CTX1, GPIO_FN_CRX1, GPIO_FN_CTX0, GPIO_FN_CTX0_CTX1, - GPIO_FN_CRX0, GPIO_FN_CRX0_CRX1, GPIO_FN_CRX0_CRX1_CRX2, + GPIO_FN_CTX2, GPIO_FN_CRX2, + GPIO_FN_CTX1, GPIO_FN_CRX1, + GPIO_FN_CTX0, GPIO_FN_CRX0, + GPIO_FN_CTX0_CTX1, GPIO_FN_CRX0_CRX1, + GPIO_FN_CTX0_CTX1_CTX2, GPIO_FN_CRX0_CRX1_CRX2, + GPIO_FN_CTX2_PJ21, GPIO_FN_CRX2_PJ20, + GPIO_FN_CTX1_PJ23, GPIO_FN_CRX1_PJ22, + GPIO_FN_CTX0_CTX1_PJ23, GPIO_FN_CRX0_CRX1_PJ22, + GPIO_FN_CTX0_CTX1_CTX2_PJ21, GPIO_FN_CRX0_CRX1_CRX2_PJ20, /* DMAC */ GPIO_FN_TEND0, GPIO_FN_DACK0, GPIO_FN_DREQ0, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c index 6cbb18ef77dc0..d20974a55d93a 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c @@ -737,13 +737,12 @@ enum { CRX0_MARK, CTX0_MARK, CRX1_MARK, CTX1_MARK, CRX2_MARK, CTX2_MARK, - CRX0_CRX1_MARK, - CRX0_CRX1_CRX2_MARK, - CTX0CTX1CTX2_MARK, + CRX0_CRX1_MARK, CTX0_CTX1_MARK, + CRX0_CRX1_CRX2_MARK, CTX0_CTX1_CTX2_MARK, CRX1_PJ22_MARK, CTX1_PJ23_MARK, CRX2_PJ20_MARK, CTX2_PJ21_MARK, - CRX0CRX1_PJ22_MARK, - CRX0CRX1CRX2_PJ20_MARK, + CRX0_CRX1_PJ22_MARK, CTX0_CTX1_PJ23_MARK, + CRX0_CRX1_CRX2_PJ20_MARK, CTX0_CTX1_CTX2_PJ21_MARK, /* VDC */ DV_CLK_MARK, @@ -821,6 +820,7 @@ static const u16 pinmux_data[] = { PINMUX_DATA(CS3_MARK, PC8MD_001), PINMUX_DATA(TXD7_MARK, PC8MD_010), PINMUX_DATA(CTX1_MARK, PC8MD_011), + PINMUX_DATA(CTX0_CTX1_MARK, PC8MD_100), PINMUX_DATA(PC7_DATA, PC7MD_000), PINMUX_DATA(CKE_MARK, PC7MD_001), @@ -833,11 +833,12 @@ static const u16 pinmux_data[] = { PINMUX_DATA(CAS_MARK, PC6MD_001), PINMUX_DATA(SCK7_MARK, PC6MD_010), PINMUX_DATA(CTX0_MARK, PC6MD_011), + PINMUX_DATA(CTX0_CTX1_CTX2_MARK, PC6MD_100), PINMUX_DATA(PC5_DATA, PC5MD_000), PINMUX_DATA(RAS_MARK, PC5MD_001), PINMUX_DATA(CRX0_MARK, PC5MD_011), - PINMUX_DATA(CTX0CTX1CTX2_MARK, PC5MD_100), + PINMUX_DATA(CTX0_CTX1_CTX2_MARK, PC5MD_100), PINMUX_DATA(IRQ0_PC_MARK, PC5MD_101), PINMUX_DATA(PC4_DATA, PC4MD_00), @@ -1289,30 +1290,32 @@ static const u16 pinmux_data[] = { PINMUX_DATA(LCD_DATA23_PJ23_MARK, PJ23MD_010), PINMUX_DATA(LCD_TCON6_MARK, PJ23MD_011), PINMUX_DATA(IRQ3_PJ_MARK, PJ23MD_100), - PINMUX_DATA(CTX1_MARK, PJ23MD_101), + PINMUX_DATA(CTX1_PJ23_MARK, PJ23MD_101), + PINMUX_DATA(CTX0_CTX1_PJ23_MARK, PJ23MD_110), PINMUX_DATA(PJ22_DATA, PJ22MD_000), PINMUX_DATA(DV_DATA22_MARK, PJ22MD_001), PINMUX_DATA(LCD_DATA22_PJ22_MARK, PJ22MD_010), PINMUX_DATA(LCD_TCON5_MARK, PJ22MD_011), PINMUX_DATA(IRQ2_PJ_MARK, PJ22MD_100), - PINMUX_DATA(CRX1_MARK, PJ22MD_101), - PINMUX_DATA(CRX0_CRX1_MARK, PJ22MD_110), + PINMUX_DATA(CRX1_PJ22_MARK, PJ22MD_101), + PINMUX_DATA(CRX0_CRX1_PJ22_MARK, PJ22MD_110), PINMUX_DATA(PJ21_DATA, PJ21MD_000), PINMUX_DATA(DV_DATA21_MARK, PJ21MD_001), PINMUX_DATA(LCD_DATA21_PJ21_MARK, PJ21MD_010), PINMUX_DATA(LCD_TCON4_MARK, PJ21MD_011), PINMUX_DATA(IRQ1_PJ_MARK, PJ21MD_100), - PINMUX_DATA(CTX2_MARK, PJ21MD_101), + PINMUX_DATA(CTX2_PJ21_MARK, PJ21MD_101), + PINMUX_DATA(CTX0_CTX1_CTX2_PJ21_MARK, PJ21MD_110), PINMUX_DATA(PJ20_DATA, PJ20MD_000), PINMUX_DATA(DV_DATA20_MARK, PJ20MD_001), PINMUX_DATA(LCD_DATA20_PJ20_MARK, PJ20MD_010), PINMUX_DATA(LCD_TCON3_MARK, PJ20MD_011), PINMUX_DATA(IRQ0_PJ_MARK, PJ20MD_100), - PINMUX_DATA(CRX2_MARK, PJ20MD_101), - PINMUX_DATA(CRX0CRX1CRX2_PJ20_MARK, PJ20MD_110), + PINMUX_DATA(CRX2_PJ20_MARK, PJ20MD_101), + PINMUX_DATA(CRX0_CRX1_CRX2_PJ20_MARK, PJ20MD_110), PINMUX_DATA(PJ19_DATA, PJ19MD_000), PINMUX_DATA(DV_DATA19_MARK, PJ19MD_001), @@ -1663,12 +1666,24 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(WDTOVF), /* CAN */ + GPIO_FN(CTX2), + GPIO_FN(CRX2), GPIO_FN(CTX1), GPIO_FN(CRX1), GPIO_FN(CTX0), GPIO_FN(CRX0), + GPIO_FN(CTX0_CTX1), GPIO_FN(CRX0_CRX1), + GPIO_FN(CTX0_CTX1_CTX2), GPIO_FN(CRX0_CRX1_CRX2), + GPIO_FN(CTX2_PJ21), + GPIO_FN(CRX2_PJ20), + GPIO_FN(CTX1_PJ23), + GPIO_FN(CRX1_PJ22), + GPIO_FN(CTX0_CTX1_PJ23), + GPIO_FN(CRX0_CRX1_PJ22), + GPIO_FN(CTX0_CTX1_CTX2_PJ21), + GPIO_FN(CRX0_CRX1_CRX2_PJ20), /* DMAC */ GPIO_FN(TEND0), -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH AUTOSEL 5.5 361/542] gpiolib: Set lockdep class for hierarchical irq domains [not found] <20200214154854.6746-1-sashal@kernel.org> ` (7 preceding siblings ...) 2020-02-14 15:44 ` [PATCH AUTOSEL 5.5 273/542] pinctrl: sh-pfc: sh7269: Fix CAN function GPIOs Sasha Levin @ 2020-02-14 15:45 ` Sasha Levin 2020-02-14 15:46 ` [PATCH AUTOSEL 5.5 383/542] gpio: Fix the no return statement warning Sasha Levin 2020-02-14 15:46 ` [PATCH AUTOSEL 5.5 384/542] pinctrl: tigerlake: Tiger Lake uses _HID enumeration Sasha Levin 10 siblings, 0 replies; 13+ messages in thread From: Sasha Levin @ 2020-02-14 15:45 UTC (permalink / raw) To: linux-kernel, stable Cc: Stephen Boyd, Thierry Reding, Brian Masney, Lina Iyer, Marc Zyngier, Maulik Shah, Linus Walleij, Sasha Levin, linux-gpio From: Stephen Boyd <swboyd@chromium.org> [ Upstream commit c34f6dc8c9e6bbe9fba1d53acd6d9a3889599da3 ] I see the following lockdep splat in the qcom pinctrl driver when attempting to suspend the device. ============================================ WARNING: possible recursive locking detected 5.4.2 #2 Tainted: G S -------------------------------------------- cat/6536 is trying to acquire lock: ffffff814787ccc0 (&irq_desc_lock_class){-.-.}, at: __irq_get_desc_lock+0x64/0x94 but task is already holding lock: ffffff81436740c0 (&irq_desc_lock_class){-.-.}, at: __irq_get_desc_lock+0x64/0x94 other info that might help us debug this: Possible unsafe locking scenario: CPU0 ---- lock(&irq_desc_lock_class); lock(&irq_desc_lock_class); *** DEADLOCK *** May be due to missing lock nesting notation 7 locks held by cat/6536: #0: ffffff8140e0c420 (sb_writers#7){.+.+}, at: vfs_write+0xc8/0x19c #1: ffffff8121eec480 (&of->mutex){+.+.}, at: kernfs_fop_write+0x128/0x1f4 #2: ffffff8147cad668 (kn->count#263){.+.+}, at: kernfs_fop_write+0x130/0x1f4 #3: ffffffd011446000 (system_transition_mutex){+.+.}, at: pm_suspend+0x108/0x354 #4: ffffff814302b970 (&dev->mutex){....}, at: __device_suspend+0x16c/0x420 #5: ffffff81436740c0 (&irq_desc_lock_class){-.-.}, at: __irq_get_desc_lock+0x64/0x94 #6: ffffff81479b8c10 (&pctrl->lock){....}, at: msm_gpio_irq_set_wake+0x48/0x7c stack backtrace: CPU: 4 PID: 6536 Comm: cat Tainted: G S 5.4.2 #2 Call trace: dump_backtrace+0x0/0x174 show_stack+0x20/0x2c dump_stack+0xdc/0x144 __lock_acquire+0x52c/0x2268 lock_acquire+0x1dc/0x220 _raw_spin_lock_irqsave+0x64/0x80 __irq_get_desc_lock+0x64/0x94 irq_set_irq_wake+0x40/0x144 msm_gpio_irq_set_wake+0x5c/0x7c set_irq_wake_real+0x40/0x5c irq_set_irq_wake+0x70/0x144 cros_ec_rtc_suspend+0x38/0x4c platform_pm_suspend+0x34/0x60 dpm_run_callback+0x64/0xcc __device_suspend+0x314/0x420 dpm_suspend+0xf8/0x298 dpm_suspend_start+0x84/0xb4 suspend_devices_and_enter+0xbc/0x628 pm_suspend+0x214/0x354 state_store+0xb0/0x108 kobj_attr_store+0x14/0x24 sysfs_kf_write+0x4c/0x64 kernfs_fop_write+0x158/0x1f4 __vfs_write+0x54/0x18c vfs_write+0xdc/0x19c ksys_write+0x7c/0xe4 __arm64_sys_write+0x20/0x2c el0_svc_common+0xa8/0x160 el0_svc_compat_handler+0x2c/0x38 el0_svc_compat+0x8/0x10 This is because the msm_gpio_irq_set_wake() function calls irq_set_irq_wake() as a backup in case the irq comes in during the path to idle. Given that we're calling irqchip functions from within an irqchip we need to set the lockdep class to be different for this child controller vs. the default one that the parent irqchip gets. This used to be done before this driver was converted to hierarchical irq domains in commit e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy") via the gpiochip_irq_map() function. With hierarchical irq domains this function has been replaced by gpiochip_hierarchy_irq_domain_alloc(). Therefore, set the lockdep class like was done previously in the irq domain path so we can avoid this lockdep warning. Fixes: fdd61a013a24 ("gpio: Add support for hierarchical IRQ domains") Cc: Thierry Reding <treding@nvidia.com> Cc: Brian Masney <masneyb@onstation.org> Cc: Lina Iyer <ilina@codeaurora.org> Cc: Marc Zyngier <maz@kernel.org> Cc: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20200114231103.85641-1-swboyd@chromium.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org> --- drivers/gpio/gpiolib.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 78a16e42f222e..0bfb4f9083993 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -2053,6 +2053,7 @@ static int gpiochip_hierarchy_irq_domain_alloc(struct irq_domain *d, parent_type); chip_info(gc, "alloc_irqs_parent for %d parent hwirq %d\n", irq, parent_hwirq); + irq_set_lockdep_class(irq, gc->irq.lock_key, gc->irq.request_key); ret = irq_domain_alloc_irqs_parent(d, irq, 1, &parent_fwspec); if (ret) chip_err(gc, -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH AUTOSEL 5.5 383/542] gpio: Fix the no return statement warning [not found] <20200214154854.6746-1-sashal@kernel.org> ` (8 preceding siblings ...) 2020-02-14 15:45 ` [PATCH AUTOSEL 5.5 361/542] gpiolib: Set lockdep class for hierarchical irq domains Sasha Levin @ 2020-02-14 15:46 ` Sasha Levin 2020-02-15 0:44 ` Kevin Hao 2020-02-14 15:46 ` [PATCH AUTOSEL 5.5 384/542] pinctrl: tigerlake: Tiger Lake uses _HID enumeration Sasha Levin 10 siblings, 1 reply; 13+ messages in thread From: Sasha Levin @ 2020-02-14 15:46 UTC (permalink / raw) To: linux-kernel, stable Cc: Kevin Hao, kbuild test robot, Linus Walleij, Sasha Levin, linux-gpio From: Kevin Hao <haokexin@gmail.com> [ Upstream commit 9c6722d85e92233082da2b3623685bba54d6093e ] In commit 242587616710 ("gpiolib: Add support for the irqdomain which doesn't use irq_fwspec as arg") we have changed the return type of gpiochip_populate_parent_fwspec_twocell/fourcell() from void to void *, but forgot to add a return statement for these two dummy functions. Add "return NULL" to fix the build warnings. Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Kevin Hao <haokexin@gmail.com> Link: https://lore.kernel.org/r/20200116095003.30324-1-haokexin@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org> --- include/linux/gpio/driver.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h index e2480ef94c559..5dce9c67a961e 100644 --- a/include/linux/gpio/driver.h +++ b/include/linux/gpio/driver.h @@ -553,6 +553,7 @@ static inline void gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *chi unsigned int parent_hwirq, unsigned int parent_type) { + return NULL; } static inline void gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *chip, @@ -560,6 +561,7 @@ static inline void gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *ch unsigned int parent_hwirq, unsigned int parent_type) { + return NULL; } #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */ -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH AUTOSEL 5.5 383/542] gpio: Fix the no return statement warning 2020-02-14 15:46 ` [PATCH AUTOSEL 5.5 383/542] gpio: Fix the no return statement warning Sasha Levin @ 2020-02-15 0:44 ` Kevin Hao 2020-02-20 17:20 ` Sasha Levin 0 siblings, 1 reply; 13+ messages in thread From: Kevin Hao @ 2020-02-15 0:44 UTC (permalink / raw) To: Sasha Levin Cc: linux-kernel, stable, kbuild test robot, Linus Walleij, linux-gpio [-- Attachment #1: Type: text/plain, Size: 1925 bytes --] On Fri, Feb 14, 2020 at 10:46:15AM -0500, Sasha Levin wrote: > From: Kevin Hao <haokexin@gmail.com> > > [ Upstream commit 9c6722d85e92233082da2b3623685bba54d6093e ] > > In commit 242587616710 ("gpiolib: Add support for the irqdomain which > doesn't use irq_fwspec as arg") we have changed the return type of > gpiochip_populate_parent_fwspec_twocell/fourcell() from void to void *, > but forgot to add a return statement for these two dummy functions. > Add "return NULL" to fix the build warnings. > > Reported-by: kbuild test robot <lkp@intel.com> > Signed-off-by: Kevin Hao <haokexin@gmail.com> > Link: https://lore.kernel.org/r/20200116095003.30324-1-haokexin@gmail.com > Signed-off-by: Linus Walleij <linus.walleij@linaro.org> > Signed-off-by: Sasha Levin <sashal@kernel.org> > --- > include/linux/gpio/driver.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h > index e2480ef94c559..5dce9c67a961e 100644 > --- a/include/linux/gpio/driver.h > +++ b/include/linux/gpio/driver.h > @@ -553,6 +553,7 @@ static inline void gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *chi > unsigned int parent_hwirq, > unsigned int parent_type) > { > + return NULL; Hi Sasha, This commit shouldn't go to the v5.5.x kernel. This is a fix for the commit 242587616710, but that commit doesn't exist in the v5.5.x kernel, then it will trigger a build warning due to the wrong returning type. Thanks, Kevin > } > > static inline void gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *chip, > @@ -560,6 +561,7 @@ static inline void gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *ch > unsigned int parent_hwirq, > unsigned int parent_type) > { > + return NULL; > } > > #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */ > -- > 2.20.1 > [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH AUTOSEL 5.5 383/542] gpio: Fix the no return statement warning 2020-02-15 0:44 ` Kevin Hao @ 2020-02-20 17:20 ` Sasha Levin 0 siblings, 0 replies; 13+ messages in thread From: Sasha Levin @ 2020-02-20 17:20 UTC (permalink / raw) To: Kevin Hao Cc: linux-kernel, stable, kbuild test robot, Linus Walleij, linux-gpio On Sat, Feb 15, 2020 at 08:44:55AM +0800, Kevin Hao wrote: >On Fri, Feb 14, 2020 at 10:46:15AM -0500, Sasha Levin wrote: >> From: Kevin Hao <haokexin@gmail.com> >> >> [ Upstream commit 9c6722d85e92233082da2b3623685bba54d6093e ] >> >> In commit 242587616710 ("gpiolib: Add support for the irqdomain which >> doesn't use irq_fwspec as arg") we have changed the return type of >> gpiochip_populate_parent_fwspec_twocell/fourcell() from void to void *, >> but forgot to add a return statement for these two dummy functions. >> Add "return NULL" to fix the build warnings. >> >> Reported-by: kbuild test robot <lkp@intel.com> >> Signed-off-by: Kevin Hao <haokexin@gmail.com> >> Link: https://lore.kernel.org/r/20200116095003.30324-1-haokexin@gmail.com >> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> >> Signed-off-by: Sasha Levin <sashal@kernel.org> >> --- >> include/linux/gpio/driver.h | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h >> index e2480ef94c559..5dce9c67a961e 100644 >> --- a/include/linux/gpio/driver.h >> +++ b/include/linux/gpio/driver.h >> @@ -553,6 +553,7 @@ static inline void gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *chi >> unsigned int parent_hwirq, >> unsigned int parent_type) >> { >> + return NULL; > >Hi Sasha, > >This commit shouldn't go to the v5.5.x kernel. This is a fix for the >commit 242587616710, but that commit doesn't exist in the v5.5.x kernel, >then it will trigger a build warning due to the wrong returning type. Now dropped, thank you. -- Thanks, Sasha ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH AUTOSEL 5.5 384/542] pinctrl: tigerlake: Tiger Lake uses _HID enumeration [not found] <20200214154854.6746-1-sashal@kernel.org> ` (9 preceding siblings ...) 2020-02-14 15:46 ` [PATCH AUTOSEL 5.5 383/542] gpio: Fix the no return statement warning Sasha Levin @ 2020-02-14 15:46 ` Sasha Levin 10 siblings, 0 replies; 13+ messages in thread From: Sasha Levin @ 2020-02-14 15:46 UTC (permalink / raw) To: linux-kernel, stable Cc: Mika Westerberg, Andy Shevchenko, Sasha Levin, linux-gpio From: Mika Westerberg <mika.westerberg@linux.intel.com> [ Upstream commit cd0a32371db73d0b50536a7ca4f036abddff0d1d ] Turns out that Tiger Lake GPIO will be enumerated using _HID method where there is only a single ACPI device and multiple BARs so rework the driver to support that scheme instead. Fixes: c9ccf71fc807 ("pinctrl: intel: Add Intel Tiger Lake pin controller support") Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Sasha Levin <sashal@kernel.org> --- drivers/pinctrl/intel/pinctrl-tigerlake.c | 547 ++++++++++------------ 1 file changed, 250 insertions(+), 297 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-tigerlake.c b/drivers/pinctrl/intel/pinctrl-tigerlake.c index 58572b15b3ce3..08a86f6fdea6e 100644 --- a/drivers/pinctrl/intel/pinctrl-tigerlake.c +++ b/drivers/pinctrl/intel/pinctrl-tigerlake.c @@ -2,7 +2,7 @@ /* * Intel Tiger Lake PCH pinctrl/GPIO driver * - * Copyright (C) 2019, Intel Corporation + * Copyright (C) 2019 - 2020, Intel Corporation * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> * Mika Westerberg <mika.westerberg@linux.intel.com> */ @@ -21,15 +21,19 @@ #define TGL_GPI_IS 0x100 #define TGL_GPI_IE 0x120 -#define TGL_GPP(r, s, e) \ +#define TGL_NO_GPIO -1 + +#define TGL_GPP(r, s, e, g) \ { \ .reg_num = (r), \ .base = (s), \ .size = ((e) - (s) + 1), \ + .gpio_base = (g), \ } -#define TGL_COMMUNITY(s, e, g) \ +#define TGL_COMMUNITY(b, s, e, g) \ { \ + .barno = (b), \ .padown_offset = TGL_PAD_OWN, \ .padcfglock_offset = TGL_PADCFGLOCK, \ .hostown_offset = TGL_HOSTSW_OWN, \ @@ -42,7 +46,7 @@ } /* Tiger Lake-LP */ -static const struct pinctrl_pin_desc tgllp_community0_pins[] = { +static const struct pinctrl_pin_desc tgllp_pins[] = { /* GPP_B */ PINCTRL_PIN(0, "CORE_VID_0"), PINCTRL_PIN(1, "CORE_VID_1"), @@ -113,324 +117,273 @@ static const struct pinctrl_pin_desc tgllp_community0_pins[] = { PINCTRL_PIN(64, "GPPC_A_22"), PINCTRL_PIN(65, "I2S1_SCLK"), PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"), -}; - -static const struct intel_padgroup tgllp_community0_gpps[] = { - TGL_GPP(0, 0, 25), /* GPP_B */ - TGL_GPP(1, 26, 41), /* GPP_T */ - TGL_GPP(2, 42, 66), /* GPP_A */ -}; - -static const struct intel_community tgllp_community0[] = { - TGL_COMMUNITY(0, 66, tgllp_community0_gpps), -}; - -static const struct intel_pinctrl_soc_data tgllp_community0_soc_data = { - .uid = "0", - .pins = tgllp_community0_pins, - .npins = ARRAY_SIZE(tgllp_community0_pins), - .communities = tgllp_community0, - .ncommunities = ARRAY_SIZE(tgllp_community0), -}; - -static const struct pinctrl_pin_desc tgllp_community1_pins[] = { /* GPP_S */ - PINCTRL_PIN(0, "SNDW0_CLK"), - PINCTRL_PIN(1, "SNDW0_DATA"), - PINCTRL_PIN(2, "SNDW1_CLK"), - PINCTRL_PIN(3, "SNDW1_DATA"), - PINCTRL_PIN(4, "SNDW2_CLK"), - PINCTRL_PIN(5, "SNDW2_DATA"), - PINCTRL_PIN(6, "SNDW3_CLK"), - PINCTRL_PIN(7, "SNDW3_DATA"), + PINCTRL_PIN(67, "SNDW0_CLK"), + PINCTRL_PIN(68, "SNDW0_DATA"), + PINCTRL_PIN(69, "SNDW1_CLK"), + PINCTRL_PIN(70, "SNDW1_DATA"), + PINCTRL_PIN(71, "SNDW2_CLK"), + PINCTRL_PIN(72, "SNDW2_DATA"), + PINCTRL_PIN(73, "SNDW3_CLK"), + PINCTRL_PIN(74, "SNDW3_DATA"), /* GPP_H */ - PINCTRL_PIN(8, "GPPC_H_0"), - PINCTRL_PIN(9, "GPPC_H_1"), - PINCTRL_PIN(10, "GPPC_H_2"), - PINCTRL_PIN(11, "SX_EXIT_HOLDOFFB"), - PINCTRL_PIN(12, "I2C2_SDA"), - PINCTRL_PIN(13, "I2C2_SCL"), - PINCTRL_PIN(14, "I2C3_SDA"), - PINCTRL_PIN(15, "I2C3_SCL"), - PINCTRL_PIN(16, "I2C4_SDA"), - PINCTRL_PIN(17, "I2C4_SCL"), - PINCTRL_PIN(18, "SRCCLKREQB_4"), - PINCTRL_PIN(19, "SRCCLKREQB_5"), - PINCTRL_PIN(20, "M2_SKT2_CFG_0"), - PINCTRL_PIN(21, "M2_SKT2_CFG_1"), - PINCTRL_PIN(22, "M2_SKT2_CFG_2"), - PINCTRL_PIN(23, "M2_SKT2_CFG_3"), - PINCTRL_PIN(24, "DDPB_CTRLCLK"), - PINCTRL_PIN(25, "DDPB_CTRLDATA"), - PINCTRL_PIN(26, "CPU_C10_GATEB"), - PINCTRL_PIN(27, "TIME_SYNC_0"), - PINCTRL_PIN(28, "IMGCLKOUT_1"), - PINCTRL_PIN(29, "IMGCLKOUT_2"), - PINCTRL_PIN(30, "IMGCLKOUT_3"), - PINCTRL_PIN(31, "IMGCLKOUT_4"), + PINCTRL_PIN(75, "GPPC_H_0"), + PINCTRL_PIN(76, "GPPC_H_1"), + PINCTRL_PIN(77, "GPPC_H_2"), + PINCTRL_PIN(78, "SX_EXIT_HOLDOFFB"), + PINCTRL_PIN(79, "I2C2_SDA"), + PINCTRL_PIN(80, "I2C2_SCL"), + PINCTRL_PIN(81, "I2C3_SDA"), + PINCTRL_PIN(82, "I2C3_SCL"), + PINCTRL_PIN(83, "I2C4_SDA"), + PINCTRL_PIN(84, "I2C4_SCL"), + PINCTRL_PIN(85, "SRCCLKREQB_4"), + PINCTRL_PIN(86, "SRCCLKREQB_5"), + PINCTRL_PIN(87, "M2_SKT2_CFG_0"), + PINCTRL_PIN(88, "M2_SKT2_CFG_1"), + PINCTRL_PIN(89, "M2_SKT2_CFG_2"), + PINCTRL_PIN(90, "M2_SKT2_CFG_3"), + PINCTRL_PIN(91, "DDPB_CTRLCLK"), + PINCTRL_PIN(92, "DDPB_CTRLDATA"), + PINCTRL_PIN(93, "CPU_C10_GATEB"), + PINCTRL_PIN(94, "TIME_SYNC_0"), + PINCTRL_PIN(95, "IMGCLKOUT_1"), + PINCTRL_PIN(96, "IMGCLKOUT_2"), + PINCTRL_PIN(97, "IMGCLKOUT_3"), + PINCTRL_PIN(98, "IMGCLKOUT_4"), /* GPP_D */ - PINCTRL_PIN(32, "ISH_GP_0"), - PINCTRL_PIN(33, "ISH_GP_1"), - PINCTRL_PIN(34, "ISH_GP_2"), - PINCTRL_PIN(35, "ISH_GP_3"), - PINCTRL_PIN(36, "IMGCLKOUT_0"), - PINCTRL_PIN(37, "SRCCLKREQB_0"), - PINCTRL_PIN(38, "SRCCLKREQB_1"), - PINCTRL_PIN(39, "SRCCLKREQB_2"), - PINCTRL_PIN(40, "SRCCLKREQB_3"), - PINCTRL_PIN(41, "ISH_SPI_CSB"), - PINCTRL_PIN(42, "ISH_SPI_CLK"), - PINCTRL_PIN(43, "ISH_SPI_MISO"), - PINCTRL_PIN(44, "ISH_SPI_MOSI"), - PINCTRL_PIN(45, "ISH_UART0_RXD"), - PINCTRL_PIN(46, "ISH_UART0_TXD"), - PINCTRL_PIN(47, "ISH_UART0_RTSB"), - PINCTRL_PIN(48, "ISH_UART0_CTSB"), - PINCTRL_PIN(49, "ISH_GP_4"), - PINCTRL_PIN(50, "ISH_GP_5"), - PINCTRL_PIN(51, "I2S_MCLK1_OUT"), - PINCTRL_PIN(52, "GSPI2_CLK_LOOPBK"), + PINCTRL_PIN(99, "ISH_GP_0"), + PINCTRL_PIN(100, "ISH_GP_1"), + PINCTRL_PIN(101, "ISH_GP_2"), + PINCTRL_PIN(102, "ISH_GP_3"), + PINCTRL_PIN(103, "IMGCLKOUT_0"), + PINCTRL_PIN(104, "SRCCLKREQB_0"), + PINCTRL_PIN(105, "SRCCLKREQB_1"), + PINCTRL_PIN(106, "SRCCLKREQB_2"), + PINCTRL_PIN(107, "SRCCLKREQB_3"), + PINCTRL_PIN(108, "ISH_SPI_CSB"), + PINCTRL_PIN(109, "ISH_SPI_CLK"), + PINCTRL_PIN(110, "ISH_SPI_MISO"), + PINCTRL_PIN(111, "ISH_SPI_MOSI"), + PINCTRL_PIN(112, "ISH_UART0_RXD"), + PINCTRL_PIN(113, "ISH_UART0_TXD"), + PINCTRL_PIN(114, "ISH_UART0_RTSB"), + PINCTRL_PIN(115, "ISH_UART0_CTSB"), + PINCTRL_PIN(116, "ISH_GP_4"), + PINCTRL_PIN(117, "ISH_GP_5"), + PINCTRL_PIN(118, "I2S_MCLK1_OUT"), + PINCTRL_PIN(119, "GSPI2_CLK_LOOPBK"), /* GPP_U */ - PINCTRL_PIN(53, "UART3_RXD"), - PINCTRL_PIN(54, "UART3_TXD"), - PINCTRL_PIN(55, "UART3_RTSB"), - PINCTRL_PIN(56, "UART3_CTSB"), - PINCTRL_PIN(57, "GSPI3_CS0B"), - PINCTRL_PIN(58, "GSPI3_CLK"), - PINCTRL_PIN(59, "GSPI3_MISO"), - PINCTRL_PIN(60, "GSPI3_MOSI"), - PINCTRL_PIN(61, "GSPI4_CS0B"), - PINCTRL_PIN(62, "GSPI4_CLK"), - PINCTRL_PIN(63, "GSPI4_MISO"), - PINCTRL_PIN(64, "GSPI4_MOSI"), - PINCTRL_PIN(65, "GSPI5_CS0B"), - PINCTRL_PIN(66, "GSPI5_CLK"), - PINCTRL_PIN(67, "GSPI5_MISO"), - PINCTRL_PIN(68, "GSPI5_MOSI"), - PINCTRL_PIN(69, "GSPI6_CS0B"), - PINCTRL_PIN(70, "GSPI6_CLK"), - PINCTRL_PIN(71, "GSPI6_MISO"), - PINCTRL_PIN(72, "GSPI6_MOSI"), - PINCTRL_PIN(73, "GSPI3_CLK_LOOPBK"), - PINCTRL_PIN(74, "GSPI4_CLK_LOOPBK"), - PINCTRL_PIN(75, "GSPI5_CLK_LOOPBK"), - PINCTRL_PIN(76, "GSPI6_CLK_LOOPBK"), + PINCTRL_PIN(120, "UART3_RXD"), + PINCTRL_PIN(121, "UART3_TXD"), + PINCTRL_PIN(122, "UART3_RTSB"), + PINCTRL_PIN(123, "UART3_CTSB"), + PINCTRL_PIN(124, "GSPI3_CS0B"), + PINCTRL_PIN(125, "GSPI3_CLK"), + PINCTRL_PIN(126, "GSPI3_MISO"), + PINCTRL_PIN(127, "GSPI3_MOSI"), + PINCTRL_PIN(128, "GSPI4_CS0B"), + PINCTRL_PIN(129, "GSPI4_CLK"), + PINCTRL_PIN(130, "GSPI4_MISO"), + PINCTRL_PIN(131, "GSPI4_MOSI"), + PINCTRL_PIN(132, "GSPI5_CS0B"), + PINCTRL_PIN(133, "GSPI5_CLK"), + PINCTRL_PIN(134, "GSPI5_MISO"), + PINCTRL_PIN(135, "GSPI5_MOSI"), + PINCTRL_PIN(136, "GSPI6_CS0B"), + PINCTRL_PIN(137, "GSPI6_CLK"), + PINCTRL_PIN(138, "GSPI6_MISO"), + PINCTRL_PIN(139, "GSPI6_MOSI"), + PINCTRL_PIN(140, "GSPI3_CLK_LOOPBK"), + PINCTRL_PIN(141, "GSPI4_CLK_LOOPBK"), + PINCTRL_PIN(142, "GSPI5_CLK_LOOPBK"), + PINCTRL_PIN(143, "GSPI6_CLK_LOOPBK"), /* vGPIO */ - PINCTRL_PIN(77, "CNV_BTEN"), - PINCTRL_PIN(78, "CNV_BT_HOST_WAKEB"), - PINCTRL_PIN(79, "CNV_BT_IF_SELECT"), - PINCTRL_PIN(80, "vCNV_BT_UART_TXD"), - PINCTRL_PIN(81, "vCNV_BT_UART_RXD"), - PINCTRL_PIN(82, "vCNV_BT_UART_CTS_B"), - PINCTRL_PIN(83, "vCNV_BT_UART_RTS_B"), - PINCTRL_PIN(84, "vCNV_MFUART1_TXD"), - PINCTRL_PIN(85, "vCNV_MFUART1_RXD"), - PINCTRL_PIN(86, "vCNV_MFUART1_CTS_B"), - PINCTRL_PIN(87, "vCNV_MFUART1_RTS_B"), - PINCTRL_PIN(88, "vUART0_TXD"), - PINCTRL_PIN(89, "vUART0_RXD"), - PINCTRL_PIN(90, "vUART0_CTS_B"), - PINCTRL_PIN(91, "vUART0_RTS_B"), - PINCTRL_PIN(92, "vISH_UART0_TXD"), - PINCTRL_PIN(93, "vISH_UART0_RXD"), - PINCTRL_PIN(94, "vISH_UART0_CTS_B"), - PINCTRL_PIN(95, "vISH_UART0_RTS_B"), - PINCTRL_PIN(96, "vCNV_BT_I2S_BCLK"), - PINCTRL_PIN(97, "vCNV_BT_I2S_WS_SYNC"), - PINCTRL_PIN(98, "vCNV_BT_I2S_SDO"), - PINCTRL_PIN(99, "vCNV_BT_I2S_SDI"), - PINCTRL_PIN(100, "vI2S2_SCLK"), - PINCTRL_PIN(101, "vI2S2_SFRM"), - PINCTRL_PIN(102, "vI2S2_TXD"), - PINCTRL_PIN(103, "vI2S2_RXD"), -}; - -static const struct intel_padgroup tgllp_community1_gpps[] = { - TGL_GPP(0, 0, 7), /* GPP_S */ - TGL_GPP(1, 8, 31), /* GPP_H */ - TGL_GPP(2, 32, 52), /* GPP_D */ - TGL_GPP(3, 53, 76), /* GPP_U */ - TGL_GPP(4, 77, 103), /* vGPIO */ -}; - -static const struct intel_community tgllp_community1[] = { - TGL_COMMUNITY(0, 103, tgllp_community1_gpps), -}; - -static const struct intel_pinctrl_soc_data tgllp_community1_soc_data = { - .uid = "1", - .pins = tgllp_community1_pins, - .npins = ARRAY_SIZE(tgllp_community1_pins), - .communities = tgllp_community1, - .ncommunities = ARRAY_SIZE(tgllp_community1), -}; - -static const struct pinctrl_pin_desc tgllp_community4_pins[] = { + PINCTRL_PIN(144, "CNV_BTEN"), + PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB"), + PINCTRL_PIN(146, "CNV_BT_IF_SELECT"), + PINCTRL_PIN(147, "vCNV_BT_UART_TXD"), + PINCTRL_PIN(148, "vCNV_BT_UART_RXD"), + PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B"), + PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B"), + PINCTRL_PIN(151, "vCNV_MFUART1_TXD"), + PINCTRL_PIN(152, "vCNV_MFUART1_RXD"), + PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B"), + PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B"), + PINCTRL_PIN(155, "vUART0_TXD"), + PINCTRL_PIN(156, "vUART0_RXD"), + PINCTRL_PIN(157, "vUART0_CTS_B"), + PINCTRL_PIN(158, "vUART0_RTS_B"), + PINCTRL_PIN(159, "vISH_UART0_TXD"), + PINCTRL_PIN(160, "vISH_UART0_RXD"), + PINCTRL_PIN(161, "vISH_UART0_CTS_B"), + PINCTRL_PIN(162, "vISH_UART0_RTS_B"), + PINCTRL_PIN(163, "vCNV_BT_I2S_BCLK"), + PINCTRL_PIN(164, "vCNV_BT_I2S_WS_SYNC"), + PINCTRL_PIN(165, "vCNV_BT_I2S_SDO"), + PINCTRL_PIN(166, "vCNV_BT_I2S_SDI"), + PINCTRL_PIN(167, "vI2S2_SCLK"), + PINCTRL_PIN(168, "vI2S2_SFRM"), + PINCTRL_PIN(169, "vI2S2_TXD"), + PINCTRL_PIN(170, "vI2S2_RXD"), /* GPP_C */ - PINCTRL_PIN(0, "SMBCLK"), - PINCTRL_PIN(1, "SMBDATA"), - PINCTRL_PIN(2, "SMBALERTB"), - PINCTRL_PIN(3, "SML0CLK"), - PINCTRL_PIN(4, "SML0DATA"), - PINCTRL_PIN(5, "SML0ALERTB"), - PINCTRL_PIN(6, "SML1CLK"), - PINCTRL_PIN(7, "SML1DATA"), - PINCTRL_PIN(8, "UART0_RXD"), - PINCTRL_PIN(9, "UART0_TXD"), - PINCTRL_PIN(10, "UART0_RTSB"), - PINCTRL_PIN(11, "UART0_CTSB"), - PINCTRL_PIN(12, "UART1_RXD"), - PINCTRL_PIN(13, "UART1_TXD"), - PINCTRL_PIN(14, "UART1_RTSB"), - PINCTRL_PIN(15, "UART1_CTSB"), - PINCTRL_PIN(16, "I2C0_SDA"), - PINCTRL_PIN(17, "I2C0_SCL"), - PINCTRL_PIN(18, "I2C1_SDA"), - PINCTRL_PIN(19, "I2C1_SCL"), - PINCTRL_PIN(20, "UART2_RXD"), - PINCTRL_PIN(21, "UART2_TXD"), - PINCTRL_PIN(22, "UART2_RTSB"), - PINCTRL_PIN(23, "UART2_CTSB"), + PINCTRL_PIN(171, "SMBCLK"), + PINCTRL_PIN(172, "SMBDATA"), + PINCTRL_PIN(173, "SMBALERTB"), + PINCTRL_PIN(174, "SML0CLK"), + PINCTRL_PIN(175, "SML0DATA"), + PINCTRL_PIN(176, "SML0ALERTB"), + PINCTRL_PIN(177, "SML1CLK"), + PINCTRL_PIN(178, "SML1DATA"), + PINCTRL_PIN(179, "UART0_RXD"), + PINCTRL_PIN(180, "UART0_TXD"), + PINCTRL_PIN(181, "UART0_RTSB"), + PINCTRL_PIN(182, "UART0_CTSB"), + PINCTRL_PIN(183, "UART1_RXD"), + PINCTRL_PIN(184, "UART1_TXD"), + PINCTRL_PIN(185, "UART1_RTSB"), + PINCTRL_PIN(186, "UART1_CTSB"), + PINCTRL_PIN(187, "I2C0_SDA"), + PINCTRL_PIN(188, "I2C0_SCL"), + PINCTRL_PIN(189, "I2C1_SDA"), + PINCTRL_PIN(190, "I2C1_SCL"), + PINCTRL_PIN(191, "UART2_RXD"), + PINCTRL_PIN(192, "UART2_TXD"), + PINCTRL_PIN(193, "UART2_RTSB"), + PINCTRL_PIN(194, "UART2_CTSB"), /* GPP_F */ - PINCTRL_PIN(24, "CNV_BRI_DT"), - PINCTRL_PIN(25, "CNV_BRI_RSP"), - PINCTRL_PIN(26, "CNV_RGI_DT"), - PINCTRL_PIN(27, "CNV_RGI_RSP"), - PINCTRL_PIN(28, "CNV_RF_RESET_B"), - PINCTRL_PIN(29, "GPPC_F_5"), - PINCTRL_PIN(30, "CNV_PA_BLANKING"), - PINCTRL_PIN(31, "GPPC_F_7"), - PINCTRL_PIN(32, "I2S_MCLK2_INOUT"), - PINCTRL_PIN(33, "BOOTMPC"), - PINCTRL_PIN(34, "GPPC_F_10"), - PINCTRL_PIN(35, "GPPC_F_11"), - PINCTRL_PIN(36, "GSXDOUT"), - PINCTRL_PIN(37, "GSXSLOAD"), - PINCTRL_PIN(38, "GSXDIN"), - PINCTRL_PIN(39, "GSXSRESETB"), - PINCTRL_PIN(40, "GSXCLK"), - PINCTRL_PIN(41, "GMII_MDC"), - PINCTRL_PIN(42, "GMII_MDIO"), - PINCTRL_PIN(43, "SRCCLKREQB_6"), - PINCTRL_PIN(44, "EXT_PWR_GATEB"), - PINCTRL_PIN(45, "EXT_PWR_GATE2B"), - PINCTRL_PIN(46, "VNN_CTRL"), - PINCTRL_PIN(47, "V1P05_CTRL"), - PINCTRL_PIN(48, "GPPF_CLK_LOOPBACK"), + PINCTRL_PIN(195, "CNV_BRI_DT"), + PINCTRL_PIN(196, "CNV_BRI_RSP"), + PINCTRL_PIN(197, "CNV_RGI_DT"), + PINCTRL_PIN(198, "CNV_RGI_RSP"), + PINCTRL_PIN(199, "CNV_RF_RESET_B"), + PINCTRL_PIN(200, "GPPC_F_5"), + PINCTRL_PIN(201, "CNV_PA_BLANKING"), + PINCTRL_PIN(202, "GPPC_F_7"), + PINCTRL_PIN(203, "I2S_MCLK2_INOUT"), + PINCTRL_PIN(204, "BOOTMPC"), + PINCTRL_PIN(205, "GPPC_F_10"), + PINCTRL_PIN(206, "GPPC_F_11"), + PINCTRL_PIN(207, "GSXDOUT"), + PINCTRL_PIN(208, "GSXSLOAD"), + PINCTRL_PIN(209, "GSXDIN"), + PINCTRL_PIN(210, "GSXSRESETB"), + PINCTRL_PIN(211, "GSXCLK"), + PINCTRL_PIN(212, "GMII_MDC"), + PINCTRL_PIN(213, "GMII_MDIO"), + PINCTRL_PIN(214, "SRCCLKREQB_6"), + PINCTRL_PIN(215, "EXT_PWR_GATEB"), + PINCTRL_PIN(216, "EXT_PWR_GATE2B"), + PINCTRL_PIN(217, "VNN_CTRL"), + PINCTRL_PIN(218, "V1P05_CTRL"), + PINCTRL_PIN(219, "GPPF_CLK_LOOPBACK"), /* HVCMOS */ - PINCTRL_PIN(49, "L_BKLTEN"), - PINCTRL_PIN(50, "L_BKLTCTL"), - PINCTRL_PIN(51, "L_VDDEN"), - PINCTRL_PIN(52, "SYS_PWROK"), - PINCTRL_PIN(53, "SYS_RESETB"), - PINCTRL_PIN(54, "MLK_RSTB"), + PINCTRL_PIN(220, "L_BKLTEN"), + PINCTRL_PIN(221, "L_BKLTCTL"), + PINCTRL_PIN(222, "L_VDDEN"), + PINCTRL_PIN(223, "SYS_PWROK"), + PINCTRL_PIN(224, "SYS_RESETB"), + PINCTRL_PIN(225, "MLK_RSTB"), /* GPP_E */ - PINCTRL_PIN(55, "SATAXPCIE_0"), - PINCTRL_PIN(56, "SPI1_IO_2"), - PINCTRL_PIN(57, "SPI1_IO_3"), - PINCTRL_PIN(58, "CPU_GP_0"), - PINCTRL_PIN(59, "SATA_DEVSLP_0"), - PINCTRL_PIN(60, "SATA_DEVSLP_1"), - PINCTRL_PIN(61, "GPPC_E_6"), - PINCTRL_PIN(62, "CPU_GP_1"), - PINCTRL_PIN(63, "SPI1_CS1B"), - PINCTRL_PIN(64, "USB2_OCB_0"), - PINCTRL_PIN(65, "SPI1_CSB"), - PINCTRL_PIN(66, "SPI1_CLK"), - PINCTRL_PIN(67, "SPI1_MISO_IO_1"), - PINCTRL_PIN(68, "SPI1_MOSI_IO_0"), - PINCTRL_PIN(69, "DDSP_HPD_A"), - PINCTRL_PIN(70, "ISH_GP_6"), - PINCTRL_PIN(71, "ISH_GP_7"), - PINCTRL_PIN(72, "GPPC_E_17"), - PINCTRL_PIN(73, "DDP1_CTRLCLK"), - PINCTRL_PIN(74, "DDP1_CTRLDATA"), - PINCTRL_PIN(75, "DDP2_CTRLCLK"), - PINCTRL_PIN(76, "DDP2_CTRLDATA"), - PINCTRL_PIN(77, "DDPA_CTRLCLK"), - PINCTRL_PIN(78, "DDPA_CTRLDATA"), - PINCTRL_PIN(79, "SPI1_CLK_LOOPBK"), + PINCTRL_PIN(226, "SATAXPCIE_0"), + PINCTRL_PIN(227, "SPI1_IO_2"), + PINCTRL_PIN(228, "SPI1_IO_3"), + PINCTRL_PIN(229, "CPU_GP_0"), + PINCTRL_PIN(230, "SATA_DEVSLP_0"), + PINCTRL_PIN(231, "SATA_DEVSLP_1"), + PINCTRL_PIN(232, "GPPC_E_6"), + PINCTRL_PIN(233, "CPU_GP_1"), + PINCTRL_PIN(234, "SPI1_CS1B"), + PINCTRL_PIN(235, "USB2_OCB_0"), + PINCTRL_PIN(236, "SPI1_CSB"), + PINCTRL_PIN(237, "SPI1_CLK"), + PINCTRL_PIN(238, "SPI1_MISO_IO_1"), + PINCTRL_PIN(239, "SPI1_MOSI_IO_0"), + PINCTRL_PIN(240, "DDSP_HPD_A"), + PINCTRL_PIN(241, "ISH_GP_6"), + PINCTRL_PIN(242, "ISH_GP_7"), + PINCTRL_PIN(243, "GPPC_E_17"), + PINCTRL_PIN(244, "DDP1_CTRLCLK"), + PINCTRL_PIN(245, "DDP1_CTRLDATA"), + PINCTRL_PIN(246, "DDP2_CTRLCLK"), + PINCTRL_PIN(247, "DDP2_CTRLDATA"), + PINCTRL_PIN(248, "DDPA_CTRLCLK"), + PINCTRL_PIN(249, "DDPA_CTRLDATA"), + PINCTRL_PIN(250, "SPI1_CLK_LOOPBK"), /* JTAG */ - PINCTRL_PIN(80, "JTAG_TDO"), - PINCTRL_PIN(81, "JTAGX"), - PINCTRL_PIN(82, "PRDYB"), - PINCTRL_PIN(83, "PREQB"), - PINCTRL_PIN(84, "CPU_TRSTB"), - PINCTRL_PIN(85, "JTAG_TDI"), - PINCTRL_PIN(86, "JTAG_TMS"), - PINCTRL_PIN(87, "JTAG_TCK"), - PINCTRL_PIN(88, "DBG_PMODE"), -}; - -static const struct intel_padgroup tgllp_community4_gpps[] = { - TGL_GPP(0, 0, 23), /* GPP_C */ - TGL_GPP(1, 24, 48), /* GPP_F */ - TGL_GPP(2, 49, 54), /* HVCMOS */ - TGL_GPP(3, 55, 79), /* GPP_E */ - TGL_GPP(4, 80, 88), /* JTAG */ + PINCTRL_PIN(251, "JTAG_TDO"), + PINCTRL_PIN(252, "JTAGX"), + PINCTRL_PIN(253, "PRDYB"), + PINCTRL_PIN(254, "PREQB"), + PINCTRL_PIN(255, "CPU_TRSTB"), + PINCTRL_PIN(256, "JTAG_TDI"), + PINCTRL_PIN(257, "JTAG_TMS"), + PINCTRL_PIN(258, "JTAG_TCK"), + PINCTRL_PIN(259, "DBG_PMODE"), + /* GPP_R */ + PINCTRL_PIN(260, "HDA_BCLK"), + PINCTRL_PIN(261, "HDA_SYNC"), + PINCTRL_PIN(262, "HDA_SDO"), + PINCTRL_PIN(263, "HDA_SDI_0"), + PINCTRL_PIN(264, "HDA_RSTB"), + PINCTRL_PIN(265, "HDA_SDI_1"), + PINCTRL_PIN(266, "GPP_R_6"), + PINCTRL_PIN(267, "GPP_R_7"), + /* SPI */ + PINCTRL_PIN(268, "SPI0_IO_2"), + PINCTRL_PIN(269, "SPI0_IO_3"), + PINCTRL_PIN(270, "SPI0_MOSI_IO_0"), + PINCTRL_PIN(271, "SPI0_MISO_IO_1"), + PINCTRL_PIN(272, "SPI0_TPM_CSB"), + PINCTRL_PIN(273, "SPI0_FLASH_0_CSB"), + PINCTRL_PIN(274, "SPI0_FLASH_1_CSB"), + PINCTRL_PIN(275, "SPI0_CLK"), + PINCTRL_PIN(276, "SPI0_CLK_LOOPBK"), }; -static const struct intel_community tgllp_community4[] = { - TGL_COMMUNITY(0, 88, tgllp_community4_gpps), +static const struct intel_padgroup tgllp_community0_gpps[] = { + TGL_GPP(0, 0, 25, 0), /* GPP_B */ + TGL_GPP(1, 26, 41, 32), /* GPP_T */ + TGL_GPP(2, 42, 66, 64), /* GPP_A */ }; -static const struct intel_pinctrl_soc_data tgllp_community4_soc_data = { - .uid = "4", - .pins = tgllp_community4_pins, - .npins = ARRAY_SIZE(tgllp_community4_pins), - .communities = tgllp_community4, - .ncommunities = ARRAY_SIZE(tgllp_community4), +static const struct intel_padgroup tgllp_community1_gpps[] = { + TGL_GPP(0, 67, 74, 96), /* GPP_S */ + TGL_GPP(1, 75, 98, 128), /* GPP_H */ + TGL_GPP(2, 99, 119, 160), /* GPP_D */ + TGL_GPP(3, 120, 143, 192), /* GPP_U */ + TGL_GPP(4, 144, 170, 224), /* vGPIO */ }; -static const struct pinctrl_pin_desc tgllp_community5_pins[] = { - /* GPP_R */ - PINCTRL_PIN(0, "HDA_BCLK"), - PINCTRL_PIN(1, "HDA_SYNC"), - PINCTRL_PIN(2, "HDA_SDO"), - PINCTRL_PIN(3, "HDA_SDI_0"), - PINCTRL_PIN(4, "HDA_RSTB"), - PINCTRL_PIN(5, "HDA_SDI_1"), - PINCTRL_PIN(6, "GPP_R_6"), - PINCTRL_PIN(7, "GPP_R_7"), - /* SPI */ - PINCTRL_PIN(8, "SPI0_IO_2"), - PINCTRL_PIN(9, "SPI0_IO_3"), - PINCTRL_PIN(10, "SPI0_MOSI_IO_0"), - PINCTRL_PIN(11, "SPI0_MISO_IO_1"), - PINCTRL_PIN(12, "SPI0_TPM_CSB"), - PINCTRL_PIN(13, "SPI0_FLASH_0_CSB"), - PINCTRL_PIN(14, "SPI0_FLASH_1_CSB"), - PINCTRL_PIN(15, "SPI0_CLK"), - PINCTRL_PIN(16, "SPI0_CLK_LOOPBK"), +static const struct intel_padgroup tgllp_community4_gpps[] = { + TGL_GPP(0, 171, 194, 256), /* GPP_C */ + TGL_GPP(1, 195, 219, 288), /* GPP_F */ + TGL_GPP(2, 220, 225, TGL_NO_GPIO), /* HVCMOS */ + TGL_GPP(3, 226, 250, 320), /* GPP_E */ + TGL_GPP(4, 251, 259, TGL_NO_GPIO), /* JTAG */ }; static const struct intel_padgroup tgllp_community5_gpps[] = { - TGL_GPP(0, 0, 7), /* GPP_R */ - TGL_GPP(1, 8, 16), /* SPI */ -}; - -static const struct intel_community tgllp_community5[] = { - TGL_COMMUNITY(0, 16, tgllp_community5_gpps), + TGL_GPP(0, 260, 267, 352), /* GPP_R */ + TGL_GPP(1, 268, 276, TGL_NO_GPIO), /* SPI */ }; -static const struct intel_pinctrl_soc_data tgllp_community5_soc_data = { - .uid = "5", - .pins = tgllp_community5_pins, - .npins = ARRAY_SIZE(tgllp_community5_pins), - .communities = tgllp_community5, - .ncommunities = ARRAY_SIZE(tgllp_community5), +static const struct intel_community tgllp_communities[] = { + TGL_COMMUNITY(0, 0, 66, tgllp_community0_gpps), + TGL_COMMUNITY(1, 67, 170, tgllp_community1_gpps), + TGL_COMMUNITY(2, 171, 259, tgllp_community4_gpps), + TGL_COMMUNITY(3, 260, 276, tgllp_community5_gpps), }; -static const struct intel_pinctrl_soc_data *tgllp_soc_data_array[] = { - &tgllp_community0_soc_data, - &tgllp_community1_soc_data, - &tgllp_community4_soc_data, - &tgllp_community5_soc_data, - NULL +static const struct intel_pinctrl_soc_data tgllp_soc_data = { + .pins = tgllp_pins, + .npins = ARRAY_SIZE(tgllp_pins), + .communities = tgllp_communities, + .ncommunities = ARRAY_SIZE(tgllp_communities), }; static const struct acpi_device_id tgl_pinctrl_acpi_match[] = { - { "INT34C5", (kernel_ulong_t)tgllp_soc_data_array }, + { "INT34C5", (kernel_ulong_t)&tgllp_soc_data }, { } }; MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match); @@ -438,7 +391,7 @@ MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match); static INTEL_PINCTRL_PM_OPS(tgl_pinctrl_pm_ops); static struct platform_driver tgl_pinctrl_driver = { - .probe = intel_pinctrl_probe_by_uid, + .probe = intel_pinctrl_probe_by_hid, .driver = { .name = "tigerlake-pinctrl", .acpi_match_table = tgl_pinctrl_acpi_match, -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
end of thread, other threads:[~2020-02-20 17:20 UTC | newest] Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- [not found] <20200214154854.6746-1-sashal@kernel.org> 2020-02-14 15:40 ` [PATCH AUTOSEL 5.5 008/542] pinctrl: baytrail: Allocate IRQ chip dynamic Sasha Levin 2020-02-14 15:40 ` [PATCH AUTOSEL 5.5 030/542] pinctrl: sh-pfc: r8a77965: Fix DU_DOTCLKIN3 drive/bias control Sasha Levin 2020-02-14 15:40 ` [PATCH AUTOSEL 5.5 035/542] pinctrl: sh-pfc: sh7264: Fix CAN function GPIOs Sasha Levin 2020-02-14 15:40 ` [PATCH AUTOSEL 5.5 050/542] gpio: gpio-grgpio: fix possible sleep-in-atomic-context bugs in grgpio_irq_map/unmap() Sasha Levin 2020-02-14 15:40 ` [PATCH AUTOSEL 5.5 060/542] pinctrl: baytrail: Do not clear IRQ flags on direct-irq enabled pins Sasha Levin 2020-02-14 15:41 ` [PATCH AUTOSEL 5.5 100/542] pinctrl: qcom: Don't lock around irq_set_irq_wake() Sasha Levin 2020-02-14 15:44 ` [PATCH AUTOSEL 5.5 272/542] pinctrl: sh-pfc: r8a7778: Fix duplicate SDSELF_B and SD1_CLK_B Sasha Levin 2020-02-14 15:44 ` [PATCH AUTOSEL 5.5 273/542] pinctrl: sh-pfc: sh7269: Fix CAN function GPIOs Sasha Levin 2020-02-14 15:45 ` [PATCH AUTOSEL 5.5 361/542] gpiolib: Set lockdep class for hierarchical irq domains Sasha Levin 2020-02-14 15:46 ` [PATCH AUTOSEL 5.5 383/542] gpio: Fix the no return statement warning Sasha Levin 2020-02-15 0:44 ` Kevin Hao 2020-02-20 17:20 ` Sasha Levin 2020-02-14 15:46 ` [PATCH AUTOSEL 5.5 384/542] pinctrl: tigerlake: Tiger Lake uses _HID enumeration Sasha Levin
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