From: Michael Walle <michael@walle.cc>
To: Linus Walleij <linus.walleij@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
Lars Povlsen <lars.povlsen@microchip.com>,
Steen Hegelund <Steen.Hegelund@microchip.com>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Gregory CLEMENT <gregory.clement@bootlin.com>,
Paul Burton <paulburton@kernel.org>,
Quentin Schulz <quentin.schulz@bootlin.com>,
Antoine Tenart <atenart@kernel.org>,
Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>,
Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: "David S . Miller" <davem@davemloft.net>,
UNGLinuxDriver@microchip.com, linux-gpio@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org,
Michael Walle <michael@walle.cc>
Subject: [PATCH v3 4/6] arm64: dts: sparx5: rename pinctrl nodes
Date: Sat, 19 Mar 2022 21:46:26 +0100 [thread overview]
Message-ID: <20220319204628.1759635-5-michael@walle.cc> (raw)
In-Reply-To: <20220319204628.1759635-1-michael@walle.cc>
The pinctrl device tree binding will be converted to YAML format. Rename
the pin nodes so they end with "-pins" to match the schema.
Signed-off-by: Michael Walle <michael@walle.cc>
---
.../dts/microchip/sparx5_pcb134_board.dtsi | 26 +++++++++----------
.../dts/microchip/sparx5_pcb135_board.dtsi | 10 +++----
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
index 33faf1f3264f..6f488e774215 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
@@ -325,69 +325,69 @@ &sgpio2 {
};
&gpio {
- i2cmux_pins_i: i2cmux-pins-i {
+ i2cmux_pins_i: i2cmux-pins {
pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19",
"GPIO_20", "GPIO_22", "GPIO_36", "GPIO_35",
"GPIO_50", "GPIO_51", "GPIO_56", "GPIO_57";
function = "twi_scl_m";
output-low;
};
- i2cmux_0: i2cmux-0 {
+ i2cmux_0: i2cmux-0-pins {
pins = "GPIO_16";
function = "twi_scl_m";
output-high;
};
- i2cmux_1: i2cmux-1 {
+ i2cmux_1: i2cmux-1-pins {
pins = "GPIO_17";
function = "twi_scl_m";
output-high;
};
- i2cmux_2: i2cmux-2 {
+ i2cmux_2: i2cmux-2-pins {
pins = "GPIO_18";
function = "twi_scl_m";
output-high;
};
- i2cmux_3: i2cmux-3 {
+ i2cmux_3: i2cmux-3-pins {
pins = "GPIO_19";
function = "twi_scl_m";
output-high;
};
- i2cmux_4: i2cmux-4 {
+ i2cmux_4: i2cmux-4-pins {
pins = "GPIO_20";
function = "twi_scl_m";
output-high;
};
- i2cmux_5: i2cmux-5 {
+ i2cmux_5: i2cmux-5-pins {
pins = "GPIO_22";
function = "twi_scl_m";
output-high;
};
- i2cmux_6: i2cmux-6 {
+ i2cmux_6: i2cmux-6-pins {
pins = "GPIO_36";
function = "twi_scl_m";
output-high;
};
- i2cmux_7: i2cmux-7 {
+ i2cmux_7: i2cmux-7-pins {
pins = "GPIO_35";
function = "twi_scl_m";
output-high;
};
- i2cmux_8: i2cmux-8 {
+ i2cmux_8: i2cmux-8-pins {
pins = "GPIO_50";
function = "twi_scl_m";
output-high;
};
- i2cmux_9: i2cmux-9 {
+ i2cmux_9: i2cmux-9-pins {
pins = "GPIO_51";
function = "twi_scl_m";
output-high;
};
- i2cmux_10: i2cmux-10 {
+ i2cmux_10: i2cmux-10-pins {
pins = "GPIO_56";
function = "twi_scl_m";
output-high;
};
- i2cmux_11: i2cmux-11 {
+ i2cmux_11: i2cmux-11-pins {
pins = "GPIO_57";
function = "twi_scl_m";
output-high;
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
index ef96e6d8c6b3..d9e519bfbf68 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
@@ -59,28 +59,28 @@ led@7 {
};
&gpio {
- i2cmux_pins_i: i2cmux-pins-i {
+ i2cmux_pins_i: i2cmux-pins {
pins = "GPIO_35", "GPIO_36",
"GPIO_50", "GPIO_51";
function = "twi_scl_m";
output-low;
};
- i2cmux_s29: i2cmux-0 {
+ i2cmux_s29: i2cmux-0-pins {
pins = "GPIO_35";
function = "twi_scl_m";
output-high;
};
- i2cmux_s30: i2cmux-1 {
+ i2cmux_s30: i2cmux-1-pins {
pins = "GPIO_36";
function = "twi_scl_m";
output-high;
};
- i2cmux_s31: i2cmux-2 {
+ i2cmux_s31: i2cmux-2-pins {
pins = "GPIO_50";
function = "twi_scl_m";
output-high;
};
- i2cmux_s32: i2cmux-3 {
+ i2cmux_s32: i2cmux-3-pins {
pins = "GPIO_51";
function = "twi_scl_m";
output-high;
--
2.30.2
next prev parent reply other threads:[~2022-03-19 20:47 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-19 20:46 [PATCH v3 0/6] pinctrl: ocelot: convert to YAML format Michael Walle
2022-03-19 20:46 ` [PATCH v3 1/6] MIPS: mscc: jaguar2: rename pinctrl nodes Michael Walle
2022-03-19 20:46 ` [PATCH v3 2/6] MIPS: mscc: ocelot: " Michael Walle
2022-03-19 20:46 ` [PATCH v3 3/6] MIPS: mscc: serval: " Michael Walle
2022-03-19 20:46 ` Michael Walle [this message]
2023-05-17 12:23 ` (subset) [PATCH v3 4/6] arm64: dts: sparx5: " Krzysztof Kozlowski
2022-03-19 20:46 ` [PATCH v3 5/6] ARM: dts: lan966x: " Michael Walle
2022-05-17 14:36 ` Nicolas Ferre
2022-03-19 20:46 ` [PATCH v3 6/6] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format Michael Walle
2022-03-20 10:54 ` Krzysztof Kozlowski
2022-03-20 11:08 ` Michael Walle
2022-03-20 11:17 ` Krzysztof Kozlowski
2022-04-17 23:41 ` Linus Walleij
2022-04-18 8:16 ` Michael Walle
2022-04-18 8:19 ` Michael Walle
2022-04-18 11:13 ` Krzysztof Kozlowski
2022-04-18 12:04 ` Michael Walle
2022-04-19 22:33 ` Linus Walleij
2022-04-04 11:45 ` [PATCH v3 0/6] pinctrl: ocelot: convert " Michael Walle
2022-04-19 22:28 ` Linus Walleij
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