Re: [PATCH v3 6/6] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

[Krzysztof Kozlowski <krzk@kernel.org>]

On 20/03/2022 12:08, Michael Walle wrote:
> Am 2022-03-20 11:54, schrieb Krzysztof Kozlowski:
>> On 19/03/2022 21:46, Michael Walle wrote:
>>> Convert the ocelot-pinctrl device tree binding to the new YAML format.
>>>
>>> Additionally to the original binding documentation, add interrupt
>>> properties which are optional and already used on several SoCs like
>>> SparX-5, Luton, Ocelot and LAN966x but were not documented before.
>>>
>>> Also, on the sparx5 and the lan966x SoCs there are two items for the
>>> reg property.
>>>
>>> Signed-off-by: Michael Walle <michael@walle.cc>
>>> ---
>>>  .../bindings/pinctrl/mscc,ocelot-pinctrl.txt  |  42 -------
>>>  .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 108 
>>> ++++++++++++++++++
>>>  2 files changed, 108 insertions(+), 42 deletions(-)
>>>  delete mode 100644 
>>> Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
>>>  create mode 100644 
>>> Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
>>>
>>> diff --git 
>>> a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt 
>>> b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
>>> deleted file mode 100644
>>> index 5d84fd299ccf..000000000000
>>> --- 
>>> a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
>>> +++ /dev/null
>>> @@ -1,42 +0,0 @@
>>> -Microsemi Ocelot pin controller Device Tree Bindings
>>> -----------------------------------------------------
>>> -
>>> -Required properties:
>>> - - compatible		: Should be "mscc,ocelot-pinctrl",
>>> -			  "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl",
>>> -			  "mscc,luton-pinctrl", "mscc,serval-pinctrl",
>>> -			  "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl"
>>> - - reg			: Address and length of the register set for the device
>>> - - gpio-controller	: Indicates this device is a GPIO controller
>>> - - #gpio-cells		: Must be 2.
>>> -			  The first cell is the pin number and the
>>> -			  second cell specifies GPIO flags, as defined in
>>> -			  <dt-bindings/gpio/gpio.h>.
>>> - - gpio-ranges		: Range of pins managed by the GPIO controller.
>>> -
>>> -
>>> -The ocelot-pinctrl driver uses the generic pin multiplexing and 
>>> generic pin
>>> -configuration documented in pinctrl-bindings.txt.
>>> -
>>> -The following generic properties are supported:
>>> - - function
>>> - - pins
>>> -
>>> -Example:
>>> -	gpio: pinctrl@71070034 {
>>> -		compatible = "mscc,ocelot-pinctrl";
>>> -		reg = <0x71070034 0x28>;
>>> -		gpio-controller;
>>> -		#gpio-cells = <2>;
>>> -		gpio-ranges = <&gpio 0 0 22>;
>>> -
>>> -		uart_pins: uart-pins {
>>> -				pins = "GPIO_6", "GPIO_7";
>>> -				function = "uart";
>>> -		};
>>> -
>>> -		uart2_pins: uart2-pins {
>>> -				pins = "GPIO_12", "GPIO_13";
>>> -				function = "uart2";
>>> -		};
>>> -	};
>>> diff --git 
>>> a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml 
>>> b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
>>> new file mode 100644
>>> index 000000000000..7149a6655623
>>> --- /dev/null
>>> +++ 
>>> b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
>>> @@ -0,0 +1,108 @@
>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Microsemi Ocelot pin controller
>>> +
>>> +maintainers:
>>> +  - Alexandre Belloni <alexandre.belloni@bootlin.com>
>>> +  - Lars Povlsen <lars.povlsen@microchip.com>
>>> +
>>> +properties:
>>> +  compatible:
>>> +    enum:
>>> +      - microchip,lan966x-pinctrl
>>> +      - microchip,sparx5-pinctrl
>>> +      - mscc,jaguar2-pinctrl
>>> +      - mscc,luton-pinctrl
>>> +      - mscc,ocelot-pinctrl
>>> +      - mscc,serval-pinctrl
>>> +      - mscc,servalt-pinctrl
>>> +
>>> +  reg:
>>> +    items:
>>> +      - description: Base address
>>> +      - description: Extended pin configuration registers
>>> +    minItems: 1
>>> +
>>> +  gpio-controller: true
>>> +
>>> +  '#gpio-cells':
>>> +    const: 2
>>> +
>>> +  gpio-ranges: true
>>> +
>>> +  interrupts:
>>> +    maxItems: 1
>>> +
>>> +  interrupt-controller: true
>>> +
>>> +  "#interrupt-cells":
>>> +    const: 2
>>
>> Thanks for the changes in other files, but I think you did not respond
>> to my comments here. Can you address them?
> 
> Sorry, I might missunderstood you. They are currently used on all except
> on serval and servalt SoCs like described in the updated commit message.
> I thought it was clear from the commit message, so I didn't answer your
> questions in v2. Or is there something else?
> 

No, it's okay.

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>


Best regards,
Krzysztof