[PATCH v2 0/2] Disable SATA DPLM on Fizz chromebox

[PATCH v2 0/2] Disable SATA DPLM on Fizz chromebox

[Gwendal Grignou]

On some chromebox, the CPU will hard freeze when the root SATA SSD link
goes in minimal power powermode.
Chromeboxes affected are of type Fizz, using Kabylake CPU.
Using existing ahci_broken_lpm() function to set ATA_FLAG_NO_LPM for the
controller which enables horkage ATA_HORKAGE_NOLPM for the SSD.
Once set, it is guaranteed DLPM (Data Link Power Manegement) SATA feature is
not enabled and DLPM can not be set to minimal power from user space.

The first patch allows disabling DLPM for all version of BIOSes,
the second disable DLPM for Fizz.

Gwendal Grignou (2):
  driver: ahci: Allow disabling dlpm for all bios version
  driver: ahci: Disable DLPM on Fizz chromebox

 drivers/ata/ahci.c | 9 +++++++++
 1 file changed, 9 insertions(+)

-- 
2.31.0.291.g576ba9dcdaf-goog

[PATCH v2 1/2] driver: ahci: Allow disabling dlpm for all bios version

[Gwendal Grignou]

In ahci_broken_lpm(), dmi->driver_data is encoded as a date: if the
date of the current BIOS is older than driver_data, the LPM horkage is
not applied.
Allow dmi->driver_data to be empty in case a problem is not fixed in any
BIOS version.

Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
---
 Changes in v2:
 Fix cut and paste error in commit message.

 drivers/ata/ahci.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 5f1f049063dd2..9132201f1353e 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -1279,6 +1279,9 @@ static bool ahci_broken_lpm(struct pci_dev *pdev)
 	if (!dmi)
 		return false;
 
+	if (!dmi->driver_data)
+		return true;
+
 	dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
 	snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
 
-- 
2.31.0.291.g576ba9dcdaf-goog

[PATCH v2 2/2] driver: ahci: Disable DLPM on Fizz chromebox

[Gwendal Grignou]

On Chromebox Fizz platform, (HP Chromebox G2, ASUS Chromebox 3, ...),
hard CPU freeze were observed when the SSD DLPM is engaged at
'min_power'.

Ensure we can not change the |link_power_management_policy| of the host
controller connected to the root SSD. (Operation not supported).

Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
---
 No changes in v2.

 drivers/ata/ahci.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 9132201f1353e..4b932bb4ed570 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -1270,6 +1270,12 @@ static bool ahci_broken_lpm(struct pci_dev *pdev)
 			 */
 			.driver_data = "20180310", /* 2.35 */
 		},
+		{
+			.matches = {
+				DMI_MATCH(DMI_BOARD_VENDOR, "Google"),
+				DMI_MATCH(DMI_BOARD_NAME, "Fizz"),
+			},
+		},
 		{ }	/* terminate list */
 	};
 	const struct dmi_system_id *dmi = dmi_first_match(sysids);
-- 
2.31.0.291.g576ba9dcdaf-goog