From: Matthias Brugger <matthias.bgg@gmail.com>
To: Chao Hao <chao.hao@mediatek.com>, Joerg Roedel <joro@8bytes.org>,
Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org, FY Yang <fy.yang@mediatek.com>,
wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org,
iommu@lists.linux-foundation.org, TH Yang <th.yang@mediatek.com>,
linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v6 09/10] iommu/mediatek: Modify MMU_CTRL register setting
Date: Mon, 6 Jul 2020 17:22:59 +0200 [thread overview]
Message-ID: <17fe4a7b-8732-7bad-6aaa-1a20a4921c7b@gmail.com> (raw)
In-Reply-To: <20200703044127.27438-10-chao.hao@mediatek.com>
On 03/07/2020 06:41, Chao Hao wrote:
> The MMU_CTRL register of MT8173 is different from other SoCs.
> The in_order_wr_en is bit[9] which is zero by default.
> Other SoCs have the vitcim_tlb_en feature mapped to bit[12].
> This bit is set to one by default. We need to preserve the bit
> when setting F_MMU_TF_PROT_TO_PROGRAM_ADDR as otherwise the
> bit will be cleared and IOMMU performance will drop.
>
> Cc: Matthias Brugger <matthias.bgg@gmail.com>
> Cc: Yong Wu <yong.wu@mediatek.com>
> Signed-off-by: Chao Hao <chao.hao@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> ---
> drivers/iommu/mtk_iommu.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index e71003037ffa..a816030d00f1 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -555,11 +555,13 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
> return ret;
> }
>
> - if (data->plat_data->m4u_plat == M4U_MT8173)
> + if (data->plat_data->m4u_plat == M4U_MT8173) {
> regval = F_MMU_PREFETCH_RT_REPLACE_MOD |
> F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173;
> - else
> - regval = F_MMU_TF_PROT_TO_PROGRAM_ADDR;
> + } else {
> + regval = readl_relaxed(data->base + REG_MMU_CTRL_REG);
> + regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR;
> + }
> writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
>
> regval = F_L2_MULIT_HIT_EN |
>
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next prev parent reply other threads:[~2020-07-06 15:23 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-03 4:41 [PATCH v6 00/10] MT6779 IOMMU SUPPORT Chao Hao
2020-07-03 4:41 ` [PATCH v6 01/10] dt-bindings: mediatek: Add bindings for MT6779 Chao Hao
2020-07-03 4:41 ` [PATCH v6 02/10] iommu/mediatek: Rename the register STANDARD_AXI_MODE(0x48) to MISC_CTRL Chao Hao
2020-07-03 4:41 ` [PATCH v6 03/10] iommu/mediatek: Use a u32 flags to describe different HW features Chao Hao
2020-07-04 1:16 ` Yingjoe Chen
2020-07-06 15:17 ` Matthias Brugger
2020-07-08 10:44 ` chao hao
2020-07-03 4:41 ` [PATCH v6 04/10] iommu/mediatek: Setting MISC_CTRL register Chao Hao
2020-07-06 15:18 ` Matthias Brugger
2020-07-03 4:41 ` [PATCH v6 05/10] iommu/mediatek: Move inv_sel_reg into the plat_data Chao Hao
2020-07-03 4:41 ` [PATCH v6 06/10] iommu/mediatek: Add sub_comm id in translation fault Chao Hao
2020-07-06 15:20 ` Matthias Brugger
2020-07-03 4:41 ` [PATCH v6 07/10] iommu/mediatek: Add REG_MMU_WR_LEN_CTRL register definition Chao Hao
2020-07-10 13:49 ` Matthias Brugger
2020-07-03 4:41 ` [PATCH v6 08/10] iommu/mediatek: Extend protect pa alignment value Chao Hao
2020-07-03 4:41 ` [PATCH v6 09/10] iommu/mediatek: Modify MMU_CTRL register setting Chao Hao
2020-07-06 15:22 ` Matthias Brugger [this message]
2020-07-03 4:41 ` [PATCH v6 10/10] iommu/mediatek: Add mt6779 basic support Chao Hao
2020-07-10 14:13 ` [PATCH v6 00/10] MT6779 IOMMU SUPPORT Joerg Roedel
2020-07-11 7:11 ` Yong Wu
2020-07-13 13:29 ` Joerg Roedel
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