From: Matthias Brugger <matthias.bgg@gmail.com>
To: Yingjoe Chen <yingjoe.chen@mediatek.com>,
Chao Hao <chao.hao@mediatek.com>
Cc: devicetree@vger.kernel.org, FY Yang <fy.yang@mediatek.com>,
wsd_upstream@mediatek.com, TH Yang <th.yang@mediatek.com>,
linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org,
Rob Herring <robh+dt@kernel.org>,
linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v6 03/10] iommu/mediatek: Use a u32 flags to describe different HW features
Date: Mon, 6 Jul 2020 17:17:03 +0200 [thread overview]
Message-ID: <bce3e1e0-f0b0-8c77-d966-3b6e37b3b647@gmail.com> (raw)
In-Reply-To: <1593825398.4355.1.camel@mtksdaap41>
On 04/07/2020 03:16, Yingjoe Chen wrote:
> On Fri, 2020-07-03 at 12:41 +0800, Chao Hao wrote:
>> Given the fact that we are adding more and more plat_data bool values,
>> it would make sense to use a u32 flags register and add the appropriate
>> macro definitions to set and check for a flag present.
>> No functional change.
>>
>> Cc: Yong Wu <yong.wu@mediatek.com>
>> Suggested-by: Matthias Brugger <matthias.bgg@gmail.com>
>> Signed-off-by: Chao Hao <chao.hao@mediatek.com>
>> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
>> ---
>> drivers/iommu/mtk_iommu.c | 28 +++++++++++++++++-----------
>> drivers/iommu/mtk_iommu.h | 7 +------
>> 2 files changed, 18 insertions(+), 17 deletions(-)
>>
>> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
>> index 88d3df5b91c2..40ca564d97af 100644
>> --- a/drivers/iommu/mtk_iommu.c
>> +++ b/drivers/iommu/mtk_iommu.c
>> @@ -100,6 +100,15 @@
>> #define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0xf)
>> #define MTK_M4U_TO_PORT(id) ((id) & 0x1f)
>>
>> +#define HAS_4GB_MODE BIT(0)
>> +/* HW will use the EMI clock if there isn't the "bclk". */
>> +#define HAS_BCLK BIT(1)
>> +#define HAS_VLD_PA_RNG BIT(2)
>> +#define RESET_AXI BIT(3)
>> +
>> +#define MTK_IOMMU_HAS_FLAG(pdata, _x) \
>> + ((((pdata)->flags) & (_x)) == (_x))
>> +
>> struct mtk_iommu_domain {
>> struct io_pgtable_cfg cfg;
>> struct io_pgtable_ops *iop;
>> @@ -563,7 +572,8 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
>> upper_32_bits(data->protect_base);
>> writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
>>
>> - if (data->enable_4GB && data->plat_data->has_vld_pa_rng) {
>> + if (data->enable_4GB &&
>> + MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) {
>> /*
>> * If 4GB mode is enabled, the validate PA range is from
>> * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
>> @@ -573,7 +583,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
>> }
>> writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
>>
>> - if (data->plat_data->reset_axi) {
>> + if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) {
>> /* The register is called STANDARD_AXI_MODE in this case */
>> writel_relaxed(0, data->base + REG_MMU_MISC_CTRL);
>> }
>> @@ -618,7 +628,7 @@ static int mtk_iommu_probe(struct platform_device *pdev)
>>
>> /* Whether the current dram is over 4GB */
>> data->enable_4GB = !!(max_pfn > (BIT_ULL(32) >> PAGE_SHIFT));
>> - if (!data->plat_data->has_4gb_mode)
>> + if (!MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE))
>> data->enable_4GB = false;
>>
>> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> @@ -631,7 +641,7 @@ static int mtk_iommu_probe(struct platform_device *pdev)
>> if (data->irq < 0)
>> return data->irq;
>>
>> - if (data->plat_data->has_bclk) {
>> + if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) {
>> data->bclk = devm_clk_get(dev, "bclk");
>> if (IS_ERR(data->bclk))
>> return PTR_ERR(data->bclk);
>> @@ -763,23 +773,19 @@ static const struct dev_pm_ops mtk_iommu_pm_ops = {
>>
>> static const struct mtk_iommu_plat_data mt2712_data = {
>> .m4u_plat = M4U_MT2712,
>> - .has_4gb_mode = true,
>> - .has_bclk = true,
>> - .has_vld_pa_rng = true,
>> + .flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG,
>> .larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
>> };
>>
>> static const struct mtk_iommu_plat_data mt8173_data = {
>> .m4u_plat = M4U_MT8173,
>> - .has_4gb_mode = true,
>> - .has_bclk = true,
>> - .reset_axi = true,
>> + .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI,
>> .larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */
>> };
>>
>> static const struct mtk_iommu_plat_data mt8183_data = {
>> .m4u_plat = M4U_MT8183,
>> - .reset_axi = true,
>> + .flags = RESET_AXI,
>> .larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1},
>> };
>>
>> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
>> index 7212e6fcf982..5225a9170aaa 100644
>> --- a/drivers/iommu/mtk_iommu.h
>> +++ b/drivers/iommu/mtk_iommu.h
>> @@ -39,12 +39,7 @@ enum mtk_iommu_plat {
>>
>> struct mtk_iommu_plat_data {
>> enum mtk_iommu_plat m4u_plat;
>> - bool has_4gb_mode;
>> -
>> - /* HW will use the EMI clock if there isn't the "bclk". */
>> - bool has_bclk;
>> - bool has_vld_pa_rng;
>> - bool reset_axi;
>> + u32 flags;
>
>
> How about using bit field instead? eg
>
> u32 has_bclk:1;
>
> In this way, we don't need to change code.
>
Actually I proposed to use the flag approach because I didn't want to bloat the
mtk_iommu_plat_data structure with new variables for every new feature, being it
a bit field or a bool.
Regards,
Matthias
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iommu@lists.linux-foundation.org
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next prev parent reply other threads:[~2020-07-06 15:17 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-03 4:41 [PATCH v6 00/10] MT6779 IOMMU SUPPORT Chao Hao
2020-07-03 4:41 ` [PATCH v6 01/10] dt-bindings: mediatek: Add bindings for MT6779 Chao Hao
2020-07-03 4:41 ` [PATCH v6 02/10] iommu/mediatek: Rename the register STANDARD_AXI_MODE(0x48) to MISC_CTRL Chao Hao
2020-07-03 4:41 ` [PATCH v6 03/10] iommu/mediatek: Use a u32 flags to describe different HW features Chao Hao
2020-07-04 1:16 ` Yingjoe Chen
2020-07-06 15:17 ` Matthias Brugger [this message]
2020-07-08 10:44 ` chao hao
2020-07-03 4:41 ` [PATCH v6 04/10] iommu/mediatek: Setting MISC_CTRL register Chao Hao
2020-07-06 15:18 ` Matthias Brugger
2020-07-03 4:41 ` [PATCH v6 05/10] iommu/mediatek: Move inv_sel_reg into the plat_data Chao Hao
2020-07-03 4:41 ` [PATCH v6 06/10] iommu/mediatek: Add sub_comm id in translation fault Chao Hao
2020-07-06 15:20 ` Matthias Brugger
2020-07-03 4:41 ` [PATCH v6 07/10] iommu/mediatek: Add REG_MMU_WR_LEN_CTRL register definition Chao Hao
2020-07-10 13:49 ` Matthias Brugger
2020-07-03 4:41 ` [PATCH v6 08/10] iommu/mediatek: Extend protect pa alignment value Chao Hao
2020-07-03 4:41 ` [PATCH v6 09/10] iommu/mediatek: Modify MMU_CTRL register setting Chao Hao
2020-07-06 15:22 ` Matthias Brugger
2020-07-03 4:41 ` [PATCH v6 10/10] iommu/mediatek: Add mt6779 basic support Chao Hao
2020-07-10 14:13 ` [PATCH v6 00/10] MT6779 IOMMU SUPPORT Joerg Roedel
2020-07-11 7:11 ` Yong Wu
2020-07-13 13:29 ` Joerg Roedel
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