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From: Matthias Brugger <matthias.bgg@gmail.com>
To: Chao Hao <chao.hao@mediatek.com>, Joerg Roedel <joro@8bytes.org>,
	Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org, FY Yang <fy.yang@mediatek.com>,
	wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org,
	iommu@lists.linux-foundation.org, TH Yang <th.yang@mediatek.com>,
	linux-mediatek@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v6 07/10] iommu/mediatek: Add REG_MMU_WR_LEN_CTRL register definition
Date: Fri, 10 Jul 2020 15:49:39 +0200	[thread overview]
Message-ID: <2500e311-983a-2d79-cd31-a9ff948b2883@gmail.com> (raw)
In-Reply-To: <20200703044127.27438-8-chao.hao@mediatek.com>



On 03/07/2020 06:41, Chao Hao wrote:
> Some platforms(ex: mt6779) need to improve performance by setting
> REG_MMU_WR_LEN_CTRL register. And we can use WR_THROT_EN macro to control
> whether we need to set the register. If the register uses default value,
> iommu will send command to EMI without restriction, when the number of
> commands become more and more, it will drop the EMI performance. So when
> more than ten_commands(default value) don't be handled for EMI, iommu will
> stop send command to EMI for keeping EMI's performace by enabling write
> throttling mechanism(bit[5][21]=0) in MMU_WR_LEN_CTRL register.
> 
> Cc: Matthias Brugger <matthias.bgg@gmail.com>
> Signed-off-by: Chao Hao <chao.hao@mediatek.com>

Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>

> ---
>   drivers/iommu/mtk_iommu.c | 11 +++++++++++
>   drivers/iommu/mtk_iommu.h |  1 +
>   2 files changed, 12 insertions(+)
> 
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index 0d96dcd8612b..5c8e141668fc 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -46,6 +46,8 @@
>   #define F_MMU_STANDARD_AXI_MODE_MASK		(BIT(3) | BIT(19))
>   
>   #define REG_MMU_DCM_DIS				0x050
> +#define REG_MMU_WR_LEN_CTRL			0x054
> +#define F_MMU_WR_THROT_DIS_MASK			(BIT(5) | BIT(21))
>   
>   #define REG_MMU_CTRL_REG			0x110
>   #define F_MMU_TF_PROT_TO_PROGRAM_ADDR		(2 << 4)
> @@ -112,6 +114,7 @@
>   #define RESET_AXI			BIT(3)
>   #define OUT_ORDER_WR_EN			BIT(4)
>   #define HAS_SUB_COMM			BIT(5)
> +#define WR_THROT_EN			BIT(6)
>   
>   #define MTK_IOMMU_HAS_FLAG(pdata, _x) \
>   		((((pdata)->flags) & (_x)) == (_x))
> @@ -593,6 +596,12 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
>   		writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG);
>   	}
>   	writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
> +	if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) {
> +		/* write command throttling mode */
> +		regval = readl_relaxed(data->base + REG_MMU_WR_LEN_CTRL);
> +		regval &= ~F_MMU_WR_THROT_DIS_MASK;
> +		writel_relaxed(regval, data->base + REG_MMU_WR_LEN_CTRL);
> +	}
>   
>   	if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) {
>   		/* The register is called STANDARD_AXI_MODE in this case */
> @@ -747,6 +756,7 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev)
>   	struct mtk_iommu_suspend_reg *reg = &data->reg;
>   	void __iomem *base = data->base;
>   
> +	reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL);
>   	reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL);
>   	reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
>   	reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
> @@ -771,6 +781,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
>   		dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret);
>   		return ret;
>   	}
> +	writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL);
>   	writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL);
>   	writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
>   	writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> index 46d0d47b22e1..31edd05e2eb1 100644
> --- a/drivers/iommu/mtk_iommu.h
> +++ b/drivers/iommu/mtk_iommu.h
> @@ -31,6 +31,7 @@ struct mtk_iommu_suspend_reg {
>   	u32				int_main_control;
>   	u32				ivrp_paddr;
>   	u32				vld_pa_rng;
> +	u32				wr_len_ctrl;
>   };
>   
>   enum mtk_iommu_plat {
> 
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  reply	other threads:[~2020-07-10 13:49 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-03  4:41 [PATCH v6 00/10] MT6779 IOMMU SUPPORT Chao Hao
2020-07-03  4:41 ` [PATCH v6 01/10] dt-bindings: mediatek: Add bindings for MT6779 Chao Hao
2020-07-03  4:41 ` [PATCH v6 02/10] iommu/mediatek: Rename the register STANDARD_AXI_MODE(0x48) to MISC_CTRL Chao Hao
2020-07-03  4:41 ` [PATCH v6 03/10] iommu/mediatek: Use a u32 flags to describe different HW features Chao Hao
2020-07-04  1:16   ` Yingjoe Chen
2020-07-06 15:17     ` Matthias Brugger
2020-07-08 10:44       ` chao hao
2020-07-03  4:41 ` [PATCH v6 04/10] iommu/mediatek: Setting MISC_CTRL register Chao Hao
2020-07-06 15:18   ` Matthias Brugger
2020-07-03  4:41 ` [PATCH v6 05/10] iommu/mediatek: Move inv_sel_reg into the plat_data Chao Hao
2020-07-03  4:41 ` [PATCH v6 06/10] iommu/mediatek: Add sub_comm id in translation fault Chao Hao
2020-07-06 15:20   ` Matthias Brugger
2020-07-03  4:41 ` [PATCH v6 07/10] iommu/mediatek: Add REG_MMU_WR_LEN_CTRL register definition Chao Hao
2020-07-10 13:49   ` Matthias Brugger [this message]
2020-07-03  4:41 ` [PATCH v6 08/10] iommu/mediatek: Extend protect pa alignment value Chao Hao
2020-07-03  4:41 ` [PATCH v6 09/10] iommu/mediatek: Modify MMU_CTRL register setting Chao Hao
2020-07-06 15:22   ` Matthias Brugger
2020-07-03  4:41 ` [PATCH v6 10/10] iommu/mediatek: Add mt6779 basic support Chao Hao
2020-07-10 14:13 ` [PATCH v6 00/10] MT6779 IOMMU SUPPORT Joerg Roedel
2020-07-11  7:11   ` Yong Wu
2020-07-13 13:29     ` Joerg Roedel

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