From: Konrad Dybcio <konrad.dybcio@somainline.org>
To: ~postmarketos/upstreaming@lists.sr.ht,
linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org,
linux-arm-kernel@lists.infradead.org,
iommu@lists.linux-foundation.org
Cc: Robin Murphy <robin.murphy@arm.com>,
Konrad Dybcio <konrad.dybcio@somainline.org>,
linux-kernel@vger.kernel.org, jamipkettunen@somainline.org,
martin.botka@somainline.org,
angelogioacchino.delregno@somainline.org,
marijn.suijten@somainline.org, Will Deacon <will@kernel.org>
Subject: [PATCH 2/6] iommu/qcom: Write TCR before TTBRs to fix ASID access behavior
Date: Fri, 27 May 2022 23:28:57 +0200 [thread overview]
Message-ID: <20220527212901.29268-3-konrad.dybcio@somainline.org> (raw)
In-Reply-To: <20220527212901.29268-1-konrad.dybcio@somainline.org>
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
As also stated in the arm-smmu driver, we must write the TCR before
writing the TTBRs, since the TCR determines the access behavior of
some fields.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
drivers/iommu/arm/arm-smmu/qcom_iommu.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
index 1728d4d7fe25..75f353866c40 100644
--- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
+++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
@@ -273,18 +273,18 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
ctx->secure_init = true;
}
- /* TTBRs */
- iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
- pgtbl_cfg.arm_lpae_s1_cfg.ttbr |
- FIELD_PREP(ARM_SMMU_TTBRn_ASID, ctx->asid));
- iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0);
-
/* TCR */
iommu_writel(ctx, ARM_SMMU_CB_TCR2,
arm_smmu_lpae_tcr2(&pgtbl_cfg));
iommu_writel(ctx, ARM_SMMU_CB_TCR,
arm_smmu_lpae_tcr(&pgtbl_cfg) | ARM_SMMU_TCR_EAE);
+ /* TTBRs */
+ iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
+ pgtbl_cfg.arm_lpae_s1_cfg.ttbr |
+ FIELD_PREP(ARM_SMMU_TTBRn_ASID, ctx->asid));
+ iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0);
+
/* MAIRs (stage-1 only) */
iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0,
pgtbl_cfg.arm_lpae_s1_cfg.mair);
--
2.36.1
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next prev parent reply other threads:[~2022-05-27 21:39 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-27 21:28 [PATCH 0/6] Fix and extend Qualcomm IOMMU support Konrad Dybcio
2022-05-27 21:28 ` [PATCH 1/6] iommu/qcom: Use the asid read from device-tree if specified Konrad Dybcio
2022-05-31 15:46 ` Will Deacon
2022-05-31 16:15 ` Rob Clark
2022-05-31 16:19 ` Will Deacon
2022-05-31 20:57 ` Rob Clark
2022-06-03 18:03 ` Konrad Dybcio
2022-06-08 10:25 ` AngeloGioacchino Del Regno
2022-05-27 21:28 ` Konrad Dybcio [this message]
2022-05-31 15:55 ` [PATCH 2/6] iommu/qcom: Write TCR before TTBRs to fix ASID access behavior Will Deacon
2022-05-31 16:26 ` Robin Murphy
2022-06-05 22:06 ` Marijn Suijten
2022-06-08 10:27 ` AngeloGioacchino Del Regno
2022-06-08 10:54 ` Robin Murphy
2022-06-08 11:03 ` AngeloGioacchino Del Regno
2022-05-27 21:28 ` [PATCH 3/6] iommu/qcom: Properly reset the IOMMU context Konrad Dybcio
2022-05-27 21:28 ` [PATCH 4/6] iommu/qcom: Add support for AArch64 IOMMU pagetables Konrad Dybcio
2022-05-28 2:03 ` kernel test robot
2022-06-02 14:17 ` Rob Herring
2022-05-27 21:29 ` [PATCH 5/6] iommu/qcom: Index contexts by asid number to allow asid 0 Konrad Dybcio
2022-06-03 15:14 ` Brian Masney
2022-05-27 21:29 ` [PATCH 6/6] iommu/qcom: Add support for QCIOMMUv2 and QCIOMMU-500 secured contexts Konrad Dybcio
-- strict thread matches above, loose matches on Subject: below --
2019-09-26 12:05 [PATCH 0/6] Add support for QCOM IOMMU v2 and 500 kholk11
2019-09-26 12:05 ` [PATCH 2/6] iommu/qcom: Write TCR before TTBRs to fix ASID access behavior kholk11
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