From: Tomasz Jeznach <tjeznach@rivosinc.com>
To: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Paul Walmsley <paul.walmsley@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Anup Patel <apatel@ventanamicro.com>,
Sunil V L <sunilvl@ventanamicro.com>,
Nick Kossifidis <mick@ics.forth.gr>,
Sebastien Boeuf <seb@rivosinc.com>,
iommu@lists.linux.dev, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, linux@rivosinc.com,
Tomasz Jeznach <tjeznach@rivosinc.com>
Subject: [PATCH 05/11] RISC-V: drivers/iommu/riscv: Add sysfs interface
Date: Wed, 19 Jul 2023 12:33:49 -0700 [thread overview]
Message-ID: <610abe685f90870be52bc7c2ca45ab5235bd8eb4.1689792825.git.tjeznach@rivosinc.com> (raw)
In-Reply-To: <cover.1689792825.git.tjeznach@rivosinc.com>
Enable sysfs debug / visibility interface providing restricted
access to hardware registers.
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
---
drivers/iommu/riscv/Makefile | 2 +-
drivers/iommu/riscv/iommu-sysfs.c | 183 ++++++++++++++++++++++++++++++
drivers/iommu/riscv/iommu.c | 7 ++
drivers/iommu/riscv/iommu.h | 2 +
4 files changed, 193 insertions(+), 1 deletion(-)
create mode 100644 drivers/iommu/riscv/iommu-sysfs.c
diff --git a/drivers/iommu/riscv/Makefile b/drivers/iommu/riscv/Makefile
index 38730c11e4a8..9523eb053cfc 100644
--- a/drivers/iommu/riscv/Makefile
+++ b/drivers/iommu/riscv/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_RISCV_IOMMU) += iommu.o iommu-pci.o iommu-platform.o
\ No newline at end of file
+obj-$(CONFIG_RISCV_IOMMU) += iommu.o iommu-pci.o iommu-platform.o iommu-sysfs.o
\ No newline at end of file
diff --git a/drivers/iommu/riscv/iommu-sysfs.c b/drivers/iommu/riscv/iommu-sysfs.c
new file mode 100644
index 000000000000..f038ea8445c5
--- /dev/null
+++ b/drivers/iommu/riscv/iommu-sysfs.c
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * IOMMU API for RISC-V architected Ziommu implementations.
+ *
+ * Copyright © 2022-2023 Rivos Inc.
+ *
+ * Author: Tomasz Jeznach <tjeznach@rivosinc.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/compiler.h>
+#include <linux/iommu.h>
+#include <linux/platform_device.h>
+#include <asm/page.h>
+
+#include "iommu.h"
+
+#define sysfs_dev_to_iommu(dev) \
+ container_of(dev_get_drvdata(dev), struct riscv_iommu_device, iommu)
+
+static ssize_t address_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct riscv_iommu_device *iommu = sysfs_dev_to_iommu(dev);
+ return sprintf(buf, "%llx\n", iommu->reg_phys);
+}
+
+static DEVICE_ATTR_RO(address);
+
+#define ATTR_RD_REG32(name, offset) \
+ ssize_t reg_ ## name ## _show(struct device *dev, \
+ struct device_attribute *attr, char *buf) \
+{ \
+ struct riscv_iommu_device *iommu = sysfs_dev_to_iommu(dev); \
+ return sprintf(buf, "0x%x\n", \
+ riscv_iommu_readl(iommu, offset)); \
+}
+
+#define ATTR_RD_REG64(name, offset) \
+ ssize_t reg_ ## name ## _show(struct device *dev, \
+ struct device_attribute *attr, char *buf) \
+{ \
+ struct riscv_iommu_device *iommu = sysfs_dev_to_iommu(dev); \
+ return sprintf(buf, "0x%llx\n", \
+ riscv_iommu_readq(iommu, offset)); \
+}
+
+#define ATTR_WR_REG32(name, offset) \
+ ssize_t reg_ ## name ## _store(struct device *dev, \
+ struct device_attribute *attr, \
+ const char *buf, size_t len) \
+{ \
+ struct riscv_iommu_device *iommu = sysfs_dev_to_iommu(dev); \
+ unsigned long val; \
+ int ret; \
+ ret = kstrtoul(buf, 0, &val); \
+ if (ret) \
+ return ret; \
+ riscv_iommu_writel(iommu, offset, val); \
+ return len; \
+}
+
+#define ATTR_WR_REG64(name, offset) \
+ ssize_t reg_ ## name ## _store(struct device *dev, \
+ struct device_attribute *attr, \
+ const char *buf, size_t len) \
+{ \
+ struct riscv_iommu_device *iommu = sysfs_dev_to_iommu(dev); \
+ unsigned long long val; \
+ int ret; \
+ ret = kstrtoull(buf, 0, &val); \
+ if (ret) \
+ return ret; \
+ riscv_iommu_writeq(iommu, offset, val); \
+ return len; \
+}
+
+#define ATTR_RO_REG32(name, offset) \
+static ATTR_RD_REG32(name, offset); \
+static DEVICE_ATTR_RO(reg_ ## name)
+
+#define ATTR_RW_REG32(name, offset) \
+static ATTR_RD_REG32(name, offset); \
+static ATTR_WR_REG32(name, offset); \
+static DEVICE_ATTR_RW(reg_ ## name)
+
+#define ATTR_RO_REG64(name, offset) \
+static ATTR_RD_REG64(name, offset); \
+static DEVICE_ATTR_RO(reg_ ## name)
+
+#define ATTR_RW_REG64(name, offset) \
+static ATTR_RD_REG64(name, offset); \
+static ATTR_WR_REG64(name, offset); \
+static DEVICE_ATTR_RW(reg_ ## name)
+
+ATTR_RO_REG64(cap, RISCV_IOMMU_REG_CAP);
+ATTR_RO_REG64(fctl, RISCV_IOMMU_REG_FCTL);
+ATTR_RO_REG32(cqh, RISCV_IOMMU_REG_CQH);
+ATTR_RO_REG32(cqt, RISCV_IOMMU_REG_CQT);
+ATTR_RO_REG32(cqcsr, RISCV_IOMMU_REG_CQCSR);
+ATTR_RO_REG32(fqh, RISCV_IOMMU_REG_FQH);
+ATTR_RO_REG32(fqt, RISCV_IOMMU_REG_FQT);
+ATTR_RO_REG32(fqcsr, RISCV_IOMMU_REG_FQCSR);
+ATTR_RO_REG32(pqh, RISCV_IOMMU_REG_PQH);
+ATTR_RO_REG32(pqt, RISCV_IOMMU_REG_PQT);
+ATTR_RO_REG32(pqcsr, RISCV_IOMMU_REG_PQCSR);
+ATTR_RO_REG32(ipsr, RISCV_IOMMU_REG_IPSR);
+ATTR_RO_REG32(ivec, RISCV_IOMMU_REG_IVEC);
+ATTR_RW_REG64(tr_iova, RISCV_IOMMU_REG_TR_REQ_IOVA);
+ATTR_RW_REG64(tr_ctrl, RISCV_IOMMU_REG_TR_REQ_CTL);
+ATTR_RW_REG64(tr_response, RISCV_IOMMU_REG_TR_RESPONSE);
+ATTR_RW_REG32(iocntovf, RISCV_IOMMU_REG_IOCOUNTOVF);
+ATTR_RW_REG32(iocntinh, RISCV_IOMMU_REG_IOCOUNTINH);
+ATTR_RW_REG64(iohpmcycles, RISCV_IOMMU_REG_IOHPMCYCLES);
+ATTR_RW_REG64(iohpmevt_1, RISCV_IOMMU_REG_IOHPMEVT(0));
+ATTR_RW_REG64(iohpmevt_2, RISCV_IOMMU_REG_IOHPMEVT(1));
+ATTR_RW_REG64(iohpmevt_3, RISCV_IOMMU_REG_IOHPMEVT(2));
+ATTR_RW_REG64(iohpmevt_4, RISCV_IOMMU_REG_IOHPMEVT(3));
+ATTR_RW_REG64(iohpmevt_5, RISCV_IOMMU_REG_IOHPMEVT(4));
+ATTR_RW_REG64(iohpmevt_6, RISCV_IOMMU_REG_IOHPMEVT(5));
+ATTR_RW_REG64(iohpmevt_7, RISCV_IOMMU_REG_IOHPMEVT(6));
+ATTR_RW_REG64(iohpmctr_1, RISCV_IOMMU_REG_IOHPMCTR(0));
+ATTR_RW_REG64(iohpmctr_2, RISCV_IOMMU_REG_IOHPMCTR(1));
+ATTR_RW_REG64(iohpmctr_3, RISCV_IOMMU_REG_IOHPMCTR(2));
+ATTR_RW_REG64(iohpmctr_4, RISCV_IOMMU_REG_IOHPMCTR(3));
+ATTR_RW_REG64(iohpmctr_5, RISCV_IOMMU_REG_IOHPMCTR(4));
+ATTR_RW_REG64(iohpmctr_6, RISCV_IOMMU_REG_IOHPMCTR(5));
+ATTR_RW_REG64(iohpmctr_7, RISCV_IOMMU_REG_IOHPMCTR(6));
+
+static struct attribute *riscv_iommu_attrs[] = {
+ &dev_attr_address.attr,
+ &dev_attr_reg_cap.attr,
+ &dev_attr_reg_fctl.attr,
+ &dev_attr_reg_cqh.attr,
+ &dev_attr_reg_cqt.attr,
+ &dev_attr_reg_cqcsr.attr,
+ &dev_attr_reg_fqh.attr,
+ &dev_attr_reg_fqt.attr,
+ &dev_attr_reg_fqcsr.attr,
+ &dev_attr_reg_pqh.attr,
+ &dev_attr_reg_pqt.attr,
+ &dev_attr_reg_pqcsr.attr,
+ &dev_attr_reg_ipsr.attr,
+ &dev_attr_reg_ivec.attr,
+ &dev_attr_reg_tr_iova.attr,
+ &dev_attr_reg_tr_ctrl.attr,
+ &dev_attr_reg_tr_response.attr,
+ &dev_attr_reg_iocntovf.attr,
+ &dev_attr_reg_iocntinh.attr,
+ &dev_attr_reg_iohpmcycles.attr,
+ &dev_attr_reg_iohpmctr_1.attr,
+ &dev_attr_reg_iohpmevt_1.attr,
+ &dev_attr_reg_iohpmctr_2.attr,
+ &dev_attr_reg_iohpmevt_2.attr,
+ &dev_attr_reg_iohpmctr_3.attr,
+ &dev_attr_reg_iohpmevt_3.attr,
+ &dev_attr_reg_iohpmctr_4.attr,
+ &dev_attr_reg_iohpmevt_4.attr,
+ &dev_attr_reg_iohpmctr_5.attr,
+ &dev_attr_reg_iohpmevt_5.attr,
+ &dev_attr_reg_iohpmctr_6.attr,
+ &dev_attr_reg_iohpmevt_6.attr,
+ &dev_attr_reg_iohpmctr_7.attr,
+ &dev_attr_reg_iohpmevt_7.attr,
+ NULL,
+};
+
+static struct attribute_group riscv_iommu_group = {
+ .name = "riscv-iommu",
+ .attrs = riscv_iommu_attrs,
+};
+
+const struct attribute_group *riscv_iommu_groups[] = {
+ &riscv_iommu_group,
+ NULL,
+};
+
+int riscv_iommu_sysfs_add(struct riscv_iommu_device *iommu) {
+ return iommu_device_sysfs_add(&iommu->iommu, NULL,
+ riscv_iommu_groups, "riscv-iommu@%llx", iommu->reg_phys);
+}
+
diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c
index 8c236242e2cc..31dc3c458e13 100644
--- a/drivers/iommu/riscv/iommu.c
+++ b/drivers/iommu/riscv/iommu.c
@@ -608,6 +608,7 @@ static const struct iommu_ops riscv_iommu_ops = {
void riscv_iommu_remove(struct riscv_iommu_device *iommu)
{
iommu_device_unregister(&iommu->iommu);
+ iommu_device_sysfs_remove(&iommu->iommu);
riscv_iommu_enable(iommu, RISCV_IOMMU_DDTP_MODE_OFF);
}
@@ -646,6 +647,12 @@ int riscv_iommu_init(struct riscv_iommu_device *iommu)
goto fail;
}
+ ret = riscv_iommu_sysfs_add(iommu);
+ if (ret) {
+ dev_err(dev, "cannot register sysfs interface (%d)\n", ret);
+ goto fail;
+ }
+
ret = iommu_device_register(&iommu->iommu, &riscv_iommu_ops, dev);
if (ret) {
dev_err(dev, "cannot register iommu interface (%d)\n", ret);
diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h
index 7baefd3630b3..7dc9baa59a50 100644
--- a/drivers/iommu/riscv/iommu.h
+++ b/drivers/iommu/riscv/iommu.h
@@ -112,4 +112,6 @@ static inline void riscv_iommu_writeq(struct riscv_iommu_device *iommu,
int riscv_iommu_init(struct riscv_iommu_device *iommu);
void riscv_iommu_remove(struct riscv_iommu_device *iommu);
+int riscv_iommu_sysfs_add(struct riscv_iommu_device *iommu);
+
#endif
--
2.34.1
next prev parent reply other threads:[~2023-07-19 19:34 UTC|newest]
Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-19 19:33 [PATCH 00/13] Linux RISC-V IOMMU Support Tomasz Jeznach
2023-07-19 19:33 ` [PATCH 01/11] RISC-V: drivers/iommu: Add RISC-V IOMMU - Ziommu support Tomasz Jeznach
2023-07-19 20:49 ` Conor Dooley
2023-07-19 21:43 ` Tomasz Jeznach
2023-07-20 19:27 ` Conor Dooley
2023-07-21 9:44 ` Conor Dooley
2023-07-20 10:38 ` Baolu Lu
2023-07-20 12:31 ` Baolu Lu
2023-07-20 17:30 ` Tomasz Jeznach
2023-07-28 2:42 ` Zong Li
2023-08-02 20:15 ` Tomasz Jeznach
2023-08-02 20:25 ` Conor Dooley
2023-08-03 3:37 ` Zong Li
2023-08-03 0:18 ` Jason Gunthorpe
2023-08-03 8:27 ` Zong Li
2023-08-16 18:05 ` Robin Murphy
2024-04-13 10:15 ` Xingyou Chen
2023-07-19 19:33 ` [PATCH 02/11] RISC-V: arch/riscv/config: enable RISC-V IOMMU support Tomasz Jeznach
2023-07-19 20:22 ` Conor Dooley
2023-07-19 21:07 ` Tomasz Jeznach
2023-07-20 6:37 ` Krzysztof Kozlowski
2023-07-19 19:33 ` [PATCH 03/11] dt-bindings: Add RISC-V IOMMU bindings Tomasz Jeznach
2023-07-19 20:19 ` Conor Dooley
[not found] ` <CAH2o1u6CZSb7pXcaXmh7dJQmNZYh3uORk4x7vJPrb+uCwFdU5g@mail.gmail.com>
2023-07-19 20:57 ` Conor Dooley
2023-07-19 21:37 ` Rob Herring
2023-07-19 23:04 ` Tomasz Jeznach
2023-07-24 8:03 ` Zong Li
2023-07-24 10:02 ` Anup Patel
2023-07-24 11:31 ` Zong Li
2023-07-24 12:10 ` Anup Patel
2023-07-24 13:23 ` Zong Li
2023-07-26 3:21 ` Baolu Lu
2023-07-26 4:26 ` Zong Li
2023-07-26 12:17 ` Jason Gunthorpe
2023-07-27 2:42 ` Zong Li
2023-08-09 14:57 ` Jason Gunthorpe
2023-08-15 1:28 ` Zong Li
2023-08-15 18:38 ` Jason Gunthorpe
2023-08-16 2:16 ` Zong Li
2023-08-16 4:10 ` Baolu Lu
2023-07-19 19:33 ` [PATCH 04/11] MAINTAINERS: Add myself for RISC-V IOMMU driver Tomasz Jeznach
2023-07-20 12:42 ` Baolu Lu
2023-07-20 17:32 ` Tomasz Jeznach
2023-07-19 19:33 ` Tomasz Jeznach [this message]
2023-07-20 6:38 ` [PATCH 05/11] RISC-V: drivers/iommu/riscv: Add sysfs interface Krzysztof Kozlowski
2023-07-20 18:30 ` Tomasz Jeznach
2023-07-20 21:37 ` Krzysztof Kozlowski
2023-07-20 22:08 ` Conor Dooley
2023-07-21 3:49 ` Tomasz Jeznach
2023-07-20 12:50 ` Baolu Lu
2023-07-20 17:47 ` Tomasz Jeznach
2023-07-19 19:33 ` [PATCH 06/11] RISC-V: drivers/iommu/riscv: Add command, fault, page-req queues Tomasz Jeznach
2023-07-20 3:11 ` Nick Kossifidis
2023-07-20 18:00 ` Tomasz Jeznach
2023-07-20 18:43 ` Conor Dooley
2023-07-24 9:47 ` Zong Li
2023-07-28 5:18 ` Tomasz Jeznach
2023-07-28 8:48 ` Zong Li
2023-07-20 13:08 ` Baolu Lu
2023-07-20 17:49 ` Tomasz Jeznach
2023-07-29 12:58 ` Zong Li
2023-07-31 9:32 ` Nick Kossifidis
2023-07-31 13:15 ` Zong Li
2023-07-31 23:35 ` Nick Kossifidis
2023-08-01 0:37 ` Zong Li
2023-08-02 20:28 ` Tomasz Jeznach
2023-08-02 20:50 ` Tomasz Jeznach
2023-08-03 8:24 ` Zong Li
2023-08-16 18:49 ` Robin Murphy
2023-07-19 19:33 ` [PATCH 07/11] RISC-V: drivers/iommu/riscv: Add device context support Tomasz Jeznach
2023-08-16 19:08 ` Robin Murphy
2023-07-19 19:33 ` [PATCH 08/11] RISC-V: drivers/iommu/riscv: Add page table support Tomasz Jeznach
2023-07-25 13:13 ` Zong Li
2023-07-31 7:19 ` Zong Li
2023-08-16 21:04 ` Robin Murphy
2023-07-19 19:33 ` [PATCH 09/11] RISC-V: drivers/iommu/riscv: Add SVA with PASID/ATS/PRI support Tomasz Jeznach
2023-07-31 9:04 ` Zong Li
2023-07-19 19:33 ` [PATCH 10/11] RISC-V: drivers/iommu/riscv: Add MSI identity remapping Tomasz Jeznach
2023-07-31 8:02 ` Zong Li
2023-08-16 21:43 ` Robin Murphy
2023-07-19 19:33 ` [PATCH 11/11] RISC-V: drivers/iommu/riscv: Add G-Stage translation support Tomasz Jeznach
2023-07-31 8:12 ` Zong Li
2023-08-16 21:13 ` Robin Murphy
[not found] ` <CAHCEehJKYu3-GSX2L6L4_VVvYt1MagRgPJvYTbqekrjPw3ZSkA@mail.gmail.com>
2024-02-23 14:04 ` [PATCH 00/13] Linux RISC-V IOMMU Support Zong Li
2024-04-04 17:37 ` Tomasz Jeznach
2024-04-10 5:38 ` Zong Li
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