From: Tomasz Jeznach <tjeznach@rivosinc.com>
To: Zong Li <zong.li@sifive.com>
Cc: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Anup Patel <apatel@ventanamicro.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux@rivosinc.com, linux-kernel@vger.kernel.org,
Sebastien Boeuf <seb@rivosinc.com>,
iommu@lists.linux.dev, Palmer Dabbelt <palmer@dabbelt.com>,
Nick Kossifidis <mick@ics.forth.gr>,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH 01/11] RISC-V: drivers/iommu: Add RISC-V IOMMU - Ziommu support.
Date: Wed, 2 Aug 2023 13:15:22 -0700 [thread overview]
Message-ID: <CAH2o1u5Sr0XigUbhna0E-Zk=U76CLZZ4LbM0u4ahPaN5+nOK6A@mail.gmail.com> (raw)
In-Reply-To: <CANXhq0qRYvTffMnep-aQyTq2tMxbP-s_Lunc+cZ2Rio+BvAE=g@mail.gmail.com>
On Thu, Jul 27, 2023 at 7:42 PM Zong Li <zong.li@sifive.com> wrote:
>
> On Thu, Jul 20, 2023 at 3:34 AM Tomasz Jeznach <tjeznach@rivosinc.com> wrote:
> >
> > +static int riscv_iommu_platform_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct riscv_iommu_device *iommu = NULL;
> > + struct resource *res = NULL;
> > + int ret = 0;
> > +
> > + iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL);
> > + if (!iommu)
> > + return -ENOMEM;
> > +
> > + iommu->dev = dev;
> > + dev_set_drvdata(dev, iommu);
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + if (!res) {
> > + dev_err(dev, "could not find resource for register region\n");
> > + return -EINVAL;
> > + }
> > +
> > + iommu->reg = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
> > + if (IS_ERR(iommu->reg)) {
> > + ret = dev_err_probe(dev, PTR_ERR(iommu->reg),
> > + "could not map register region\n");
> > + goto fail;
> > + };
> > +
> > + iommu->reg_phys = res->start;
> > +
> > + ret = -ENODEV;
> > +
> > + /* Sanity check: Did we get the whole register space ? */
> > + if ((res->end - res->start + 1) < RISCV_IOMMU_REG_SIZE) {
> > + dev_err(dev, "device region smaller than register file (0x%llx)\n",
> > + res->end - res->start);
> > + goto fail;
> > + }
>
> Could we assume that DT should be responsible for specifying the right size?
>
This only to validate DT provided info and driver expected register
file size. Expectation is that DT will provide right size.
> > +static struct iommu_domain *riscv_iommu_domain_alloc(unsigned type)
> > +{
> > + struct riscv_iommu_domain *domain;
> > +
> > + if (type != IOMMU_DOMAIN_IDENTITY &&
> > + type != IOMMU_DOMAIN_BLOCKED)
> > + return NULL;
> > +
> > + domain = kzalloc(sizeof(*domain), GFP_KERNEL);
> > + if (!domain)
> > + return NULL;
> > +
> > + mutex_init(&domain->lock);
> > + INIT_LIST_HEAD(&domain->endpoints);
> > +
> > + domain->domain.ops = &riscv_iommu_domain_ops;
> > + domain->mode = RISCV_IOMMU_DC_FSC_MODE_BARE;
> > + domain->pscid = ida_alloc_range(&riscv_iommu_pscids, 1,
> > + RISCV_IOMMU_MAX_PSCID, GFP_KERNEL);
> > +
> > + printk("domain type %x alloc %u\n", type, domain->pscid);
> > +
>
> Could it uses pr_xxx instead of printk?
>
Absolutely, fixed here and elsewhere. Also, used dev_dbg wherever applicable.
> > +
> > +static int riscv_iommu_enable(struct riscv_iommu_device *iommu, unsigned requested_mode)
> > +{
> > + struct device *dev = iommu->dev;
> > + u64 ddtp = 0;
> > + u64 ddtp_paddr = 0;
> > + unsigned mode = requested_mode;
> > + unsigned mode_readback = 0;
> > +
> > + ddtp = riscv_iommu_get_ddtp(iommu);
> > + if (ddtp & RISCV_IOMMU_DDTP_BUSY)
> > + return -EBUSY;
> > +
> > + /* Disallow state transtion from xLVL to xLVL. */
> > + switch (FIELD_GET(RISCV_IOMMU_DDTP_MODE, ddtp)) {
> > + case RISCV_IOMMU_DDTP_MODE_BARE:
> > + case RISCV_IOMMU_DDTP_MODE_OFF:
> > + break;
> > + default:
> > + if ((mode != RISCV_IOMMU_DDTP_MODE_BARE)
> > + && (mode != RISCV_IOMMU_DDTP_MODE_OFF))
> > + return -EINVAL;
> > + break;
> > + }
> > +
> > + retry:
>
> We need to consider the `iommu.passthrough` before we set up the mode
> in switch case, something like
>
This function is only to execute configuration and set device directory mode.
Handling global iommu.passthrough policy is implemented in
riscv_iommu_init() call (patch #7).
Best,
- Tomasz
next prev parent reply other threads:[~2023-08-02 20:15 UTC|newest]
Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-19 19:33 [PATCH 00/13] Linux RISC-V IOMMU Support Tomasz Jeznach
2023-07-19 19:33 ` [PATCH 01/11] RISC-V: drivers/iommu: Add RISC-V IOMMU - Ziommu support Tomasz Jeznach
2023-07-19 20:49 ` Conor Dooley
2023-07-19 21:43 ` Tomasz Jeznach
2023-07-20 19:27 ` Conor Dooley
2023-07-21 9:44 ` Conor Dooley
2023-07-20 10:38 ` Baolu Lu
2023-07-20 12:31 ` Baolu Lu
2023-07-20 17:30 ` Tomasz Jeznach
2023-07-28 2:42 ` Zong Li
2023-08-02 20:15 ` Tomasz Jeznach [this message]
2023-08-02 20:25 ` Conor Dooley
2023-08-03 3:37 ` Zong Li
2023-08-03 0:18 ` Jason Gunthorpe
2023-08-03 8:27 ` Zong Li
2023-08-16 18:05 ` Robin Murphy
2024-04-13 10:15 ` Xingyou Chen
2023-07-19 19:33 ` [PATCH 02/11] RISC-V: arch/riscv/config: enable RISC-V IOMMU support Tomasz Jeznach
2023-07-19 20:22 ` Conor Dooley
2023-07-19 21:07 ` Tomasz Jeznach
2023-07-20 6:37 ` Krzysztof Kozlowski
2023-07-19 19:33 ` [PATCH 03/11] dt-bindings: Add RISC-V IOMMU bindings Tomasz Jeznach
2023-07-19 20:19 ` Conor Dooley
[not found] ` <CAH2o1u6CZSb7pXcaXmh7dJQmNZYh3uORk4x7vJPrb+uCwFdU5g@mail.gmail.com>
2023-07-19 20:57 ` Conor Dooley
2023-07-19 21:37 ` Rob Herring
2023-07-19 23:04 ` Tomasz Jeznach
2023-07-24 8:03 ` Zong Li
2023-07-24 10:02 ` Anup Patel
2023-07-24 11:31 ` Zong Li
2023-07-24 12:10 ` Anup Patel
2023-07-24 13:23 ` Zong Li
2023-07-26 3:21 ` Baolu Lu
2023-07-26 4:26 ` Zong Li
2023-07-26 12:17 ` Jason Gunthorpe
2023-07-27 2:42 ` Zong Li
2023-08-09 14:57 ` Jason Gunthorpe
2023-08-15 1:28 ` Zong Li
2023-08-15 18:38 ` Jason Gunthorpe
2023-08-16 2:16 ` Zong Li
2023-08-16 4:10 ` Baolu Lu
2023-07-19 19:33 ` [PATCH 04/11] MAINTAINERS: Add myself for RISC-V IOMMU driver Tomasz Jeznach
2023-07-20 12:42 ` Baolu Lu
2023-07-20 17:32 ` Tomasz Jeznach
2023-07-19 19:33 ` [PATCH 05/11] RISC-V: drivers/iommu/riscv: Add sysfs interface Tomasz Jeznach
2023-07-20 6:38 ` Krzysztof Kozlowski
2023-07-20 18:30 ` Tomasz Jeznach
2023-07-20 21:37 ` Krzysztof Kozlowski
2023-07-20 22:08 ` Conor Dooley
2023-07-21 3:49 ` Tomasz Jeznach
2023-07-20 12:50 ` Baolu Lu
2023-07-20 17:47 ` Tomasz Jeznach
2023-07-19 19:33 ` [PATCH 06/11] RISC-V: drivers/iommu/riscv: Add command, fault, page-req queues Tomasz Jeznach
2023-07-20 3:11 ` Nick Kossifidis
2023-07-20 18:00 ` Tomasz Jeznach
2023-07-20 18:43 ` Conor Dooley
2023-07-24 9:47 ` Zong Li
2023-07-28 5:18 ` Tomasz Jeznach
2023-07-28 8:48 ` Zong Li
2023-07-20 13:08 ` Baolu Lu
2023-07-20 17:49 ` Tomasz Jeznach
2023-07-29 12:58 ` Zong Li
2023-07-31 9:32 ` Nick Kossifidis
2023-07-31 13:15 ` Zong Li
2023-07-31 23:35 ` Nick Kossifidis
2023-08-01 0:37 ` Zong Li
2023-08-02 20:28 ` Tomasz Jeznach
2023-08-02 20:50 ` Tomasz Jeznach
2023-08-03 8:24 ` Zong Li
2023-08-16 18:49 ` Robin Murphy
2023-07-19 19:33 ` [PATCH 07/11] RISC-V: drivers/iommu/riscv: Add device context support Tomasz Jeznach
2023-08-16 19:08 ` Robin Murphy
2023-07-19 19:33 ` [PATCH 08/11] RISC-V: drivers/iommu/riscv: Add page table support Tomasz Jeznach
2023-07-25 13:13 ` Zong Li
2023-07-31 7:19 ` Zong Li
2023-08-16 21:04 ` Robin Murphy
2023-07-19 19:33 ` [PATCH 09/11] RISC-V: drivers/iommu/riscv: Add SVA with PASID/ATS/PRI support Tomasz Jeznach
2023-07-31 9:04 ` Zong Li
2023-07-19 19:33 ` [PATCH 10/11] RISC-V: drivers/iommu/riscv: Add MSI identity remapping Tomasz Jeznach
2023-07-31 8:02 ` Zong Li
2023-08-16 21:43 ` Robin Murphy
2023-07-19 19:33 ` [PATCH 11/11] RISC-V: drivers/iommu/riscv: Add G-Stage translation support Tomasz Jeznach
2023-07-31 8:12 ` Zong Li
2023-08-16 21:13 ` Robin Murphy
[not found] ` <CAHCEehJKYu3-GSX2L6L4_VVvYt1MagRgPJvYTbqekrjPw3ZSkA@mail.gmail.com>
2024-02-23 14:04 ` [PATCH 00/13] Linux RISC-V IOMMU Support Zong Li
2024-04-04 17:37 ` Tomasz Jeznach
2024-04-10 5:38 ` Zong Li
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