From: Matthias Brugger <matthias.bgg@gmail.com>
To: Yong Wu <yong.wu@mediatek.com>, Joerg Roedel <joro@8bytes.org>,
Robin Murphy <robin.murphy@arm.com>,
Rob Herring <robh+dt@kernel.org>
Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org,
Nicolas Boichat <drinkcat@chromium.org>,
srv_heupstream@mediatek.com, Will Deacon <will.deacon@arm.com>,
linux-kernel@vger.kernel.org, Evan Green <evgreen@chromium.org>,
Tomasz Figa <tfiga@google.com>,
iommu@lists.linux-foundation.org,
Matthias Kaehlcke <mka@chromium.org>,
linux-mediatek@lists.infradead.org, yingjoe.chen@mediatek.com,
anan.sun@mediatek.com, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v7 14/21] iommu/mediatek: Add mmu1 support
Date: Mon, 17 Jun 2019 17:58:28 +0200 [thread overview]
Message-ID: <dbed27ec-381e-8feb-736b-508d9d6e40cf@gmail.com> (raw)
In-Reply-To: <1560169080-27134-15-git-send-email-yong.wu@mediatek.com>
On 10/06/2019 14:17, Yong Wu wrote:
> Normally the M4U HW connect EMI with smi. the diagram is like below:
> EMI
> |
> M4U
> |
> smi-common
> |
> -----------------
> | | | | ...
> larb0 larb1 larb2 larb3
>
> Actually there are 2 mmu cells in the M4U HW, like this diagram:
>
> EMI
> ---------
> | |
> mmu0 mmu1 <- M4U
> | |
> ---------
> |
> smi-common
> |
> -----------------
> | | | | ...
> larb0 larb1 larb2 larb3
>
> This patch add support for mmu1. In order to get better performance,
> we could adjust some larbs go to mmu1 while the others still go to
> mmu0. This is controlled by a SMI COMMON register SMI_BUS_SEL(0x220).
>
> mt2712, mt8173 and mt8183 M4U HW all have 2 mmu cells. the default
> value of that register is 0 which means all the larbs go to mmu0
> defaultly.
>
> This is a preparing patch for adjusting SMI_BUS_SEL for mt8183.
>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> ---
> drivers/iommu/mtk_iommu.c | 46 +++++++++++++++++++++++++++++-----------------
> 1 file changed, 29 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index 3a14301..ec4ce74 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -72,26 +72,32 @@
> #define F_INT_CLR_BIT BIT(12)
>
> #define REG_MMU_INT_MAIN_CONTROL 0x124
> -#define F_INT_TRANSLATION_FAULT BIT(0)
> -#define F_INT_MAIN_MULTI_HIT_FAULT BIT(1)
> -#define F_INT_INVALID_PA_FAULT BIT(2)
> -#define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3)
> -#define F_INT_TLB_MISS_FAULT BIT(4)
> -#define F_INT_MISS_TRANSACTION_FIFO_FAULT BIT(5)
> -#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT BIT(6)
> + /* mmu0 | mmu1 */
> +#define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7))
> +#define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8))
> +#define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9))
> +#define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10))
> +#define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11))
> +#define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12))
> +#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13))
>
> #define REG_MMU_CPE_DONE 0x12C
>
> #define REG_MMU_FAULT_ST1 0x134
> +#define F_REG_MMU0_FAULT_MASK GENMASK(6, 0)
> +#define F_REG_MMU1_FAULT_MASK GENMASK(13, 7)
>
> -#define REG_MMU_FAULT_VA 0x13c
> +#define REG_MMU0_FAULT_VA 0x13c
> #define F_MMU_FAULT_VA_WRITE_BIT BIT(1)
> #define F_MMU_FAULT_VA_LAYER_BIT BIT(0)
>
> -#define REG_MMU_INVLD_PA 0x140
> -#define REG_MMU_INT_ID 0x150
> -#define F_MMU0_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
> -#define F_MMU0_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
> +#define REG_MMU0_INVLD_PA 0x140
> +#define REG_MMU1_FAULT_VA 0x144
> +#define REG_MMU1_INVLD_PA 0x148
> +#define REG_MMU0_INT_ID 0x150
> +#define REG_MMU1_INT_ID 0x154
> +#define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
> +#define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
>
> #define MTK_PROTECT_PA_ALIGN 128
>
> @@ -210,13 +216,19 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
>
> /* Read error info from registers */
> int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1);
> - fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA);
> + if (int_state & F_REG_MMU0_FAULT_MASK) {
> + regval = readl_relaxed(data->base + REG_MMU0_INT_ID);
> + fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA);
> + fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA);
> + } else {
> + regval = readl_relaxed(data->base + REG_MMU1_INT_ID);
> + fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA);
> + fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA);
> + }
> layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
> write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
> - fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA);
> - regval = readl_relaxed(data->base + REG_MMU_INT_ID);
> - fault_larb = F_MMU0_INT_ID_LARB_ID(regval);
> - fault_port = F_MMU0_INT_ID_PORT_ID(regval);
> + fault_larb = F_MMU_INT_ID_LARB_ID(regval);
> + fault_port = F_MMU_INT_ID_PORT_ID(regval);
>
> fault_larb = data->plat_data->larbid_remap[fault_larb];
>
>
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next prev parent reply other threads:[~2019-06-17 15:58 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-10 12:17 [PATCH v7 00/21] MT8183 IOMMU SUPPORT Yong Wu
2019-06-10 12:17 ` [PATCH v7 01/21] dt-bindings: mediatek: Add binding for mt8183 IOMMU and SMI Yong Wu
2019-06-10 12:17 ` [PATCH v7 02/21] iommu/mediatek: Use a struct as the platform data Yong Wu
2019-06-10 12:17 ` [PATCH v7 03/21] memory: mtk-smi: Use a general config_port interface Yong Wu
2019-06-10 12:17 ` [PATCH v7 04/21] memory: mtk-smi: Use a struct for the platform data for smi-common Yong Wu
2019-06-10 12:17 ` [PATCH v7 05/21] iommu/io-pgtable-arm-v7s: Add paddr_to_iopte and iopte_to_paddr helpers Yong Wu
2019-06-10 12:17 ` [PATCH v7 06/21] iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB Mode Yong Wu
2019-06-10 12:17 ` [PATCH v7 07/21] iommu/mediatek: Add bclk can be supported optionally Yong Wu
2019-06-15 19:18 ` Matthias Brugger
2019-06-10 12:17 ` [PATCH v7 08/21] iommu/mediatek: Add larb-id remapped support Yong Wu
2019-06-17 9:25 ` Matthias Brugger
2019-06-10 12:17 ` [PATCH v7 09/21] iommu/mediatek: Refine protect memory definition Yong Wu
2019-06-17 9:59 ` Matthias Brugger
2019-06-10 12:17 ` [PATCH v7 10/21] iommu/mediatek: Move reset_axi into plat_data Yong Wu
2019-06-17 10:19 ` Matthias Brugger
2019-06-10 12:17 ` [PATCH v7 11/21] iommu/mediatek: Move vld_pa_rng " Yong Wu
2019-06-17 10:27 ` Matthias Brugger
2019-06-10 12:17 ` [PATCH v7 12/21] memory: mtk-smi: Add gals support Yong Wu
2019-06-17 15:43 ` Matthias Brugger
2019-06-10 12:17 ` [PATCH v7 13/21] iommu/mediatek: Add mt8183 IOMMU support Yong Wu
2019-06-17 15:51 ` Matthias Brugger
2019-06-10 12:17 ` [PATCH v7 14/21] iommu/mediatek: Add mmu1 support Yong Wu
2019-06-17 15:58 ` Matthias Brugger [this message]
2019-06-18 6:19 ` Tomasz Figa via iommu
2019-06-18 12:09 ` Yong Wu
2019-06-18 14:05 ` Tomasz Figa via iommu
2019-06-10 12:17 ` [PATCH v7 15/21] memory: mtk-smi: Invoke pm runtime_callback to enable clocks Yong Wu
2019-06-17 16:13 ` Matthias Brugger
2019-06-10 12:17 ` [PATCH v7 16/21] memory: mtk-smi: Add bus_sel for mt8183 Yong Wu
2019-06-13 8:14 ` Pi-Hsun Shih
2019-06-20 9:35 ` Matthias Brugger
2019-06-20 11:38 ` Matthias Brugger
2019-06-21 3:57 ` Pi-Hsun Shih
2019-06-13 8:20 ` Pi-Hsun Shih
2019-06-17 16:28 ` Matthias Brugger
2019-06-17 16:23 ` Matthias Brugger
2019-06-18 12:10 ` Yong Wu
2019-06-18 21:07 ` Matthias Brugger
2019-06-10 12:17 ` [PATCH v7 17/21] memory: mtk-smi: Get rid of need_larbid Yong Wu
2019-06-18 13:45 ` Matthias Brugger
2019-06-20 13:59 ` Yong Wu
2019-06-10 12:17 ` [PATCH v7 18/21] iommu/mediatek: Fix VLD_PA_RNG register backup when suspend Yong Wu
2019-06-17 16:30 ` Matthias Brugger
2019-06-10 12:17 ` [PATCH v7 19/21] iommu/mediatek: Rename enable_4GB to dram_is_4gb Yong Wu
2019-06-18 16:06 ` Matthias Brugger
2019-06-20 13:59 ` Yong Wu
2019-06-21 10:10 ` Matthias Brugger
2019-06-22 2:42 ` Yong Wu
2019-06-10 12:17 ` [PATCH v7 20/21] iommu/mediatek: Fix iova_to_phys PA start for 4GB mode Yong Wu
2019-06-18 16:35 ` Matthias Brugger
2019-06-20 14:00 ` Yong Wu
2019-06-10 12:18 ` [PATCH v7 21/21] iommu/mediatek: Switch to SPDX license identifier Yong Wu
2019-06-17 16:33 ` Matthias Brugger
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