* [PATCH 0/1] Fix AST2600A2 APLL calculate formuula @ 2021-01-18 10:08 Ryan Chen 2021-01-18 10:08 ` [PATCH 1/1] clk: aspeed: Fix APLL calculate formula for ast2600-A2 Ryan Chen 0 siblings, 1 reply; 9+ messages in thread From: Ryan Chen @ 2021-01-18 10:08 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, linux-clk, linux-kernel, andrewrj, joel, BMC-SW Cc: Ryan Chen AST2600 A1/A2 have different pll, this patch fix for AST2600 A2 APLL calculate. Ryan Chen (1): clk: aspeed: Fix APLL calculate formula for ast2600-A2 drivers/clk/clk-ast2600.c | 37 +++++++++++++++++++++++++++---------- 1 file changed, 27 insertions(+), 10 deletions(-) -- 2.17.1 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/1] clk: aspeed: Fix APLL calculate formula for ast2600-A2 2021-01-18 10:08 [PATCH 0/1] Fix AST2600A2 APLL calculate formuula Ryan Chen @ 2021-01-18 10:08 ` Ryan Chen 2021-01-19 2:20 ` Joel Stanley 2021-01-19 6:17 ` [PATCH v2] clk: aspeed: Fix APLL calculate formula from ast2600-A2 Ryan Chen 0 siblings, 2 replies; 9+ messages in thread From: Ryan Chen @ 2021-01-18 10:08 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, linux-clk, linux-kernel, andrewrj, joel, BMC-SW Cc: Ryan Chen AST2600A1/A2 have different pll calculate formula. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> --- drivers/clk/clk-ast2600.c | 37 +++++++++++++++++++++++++++---------- 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c index bbacaccad554..8933bd1506b3 100644 --- a/drivers/clk/clk-ast2600.c +++ b/drivers/clk/clk-ast2600.c @@ -17,7 +17,8 @@ #define ASPEED_G6_NUM_CLKS 71 -#define ASPEED_G6_SILICON_REV 0x004 +#define ASPEED_G6_SILICON_REV 0x014 +#define CHIP_REVISION_ID GENMASK(23, 16) #define ASPEED_G6_RESET_CTRL 0x040 #define ASPEED_G6_RESET_CTRL2 0x050 @@ -190,18 +191,34 @@ static struct clk_hw *ast2600_calc_pll(const char *name, u32 val) static struct clk_hw *ast2600_calc_apll(const char *name, u32 val) { unsigned int mult, div; + u32 chip_id = readl(scu_g6_base + ASPEED_G6_SILICON_REV); - if (val & BIT(20)) { - /* Pass through mode */ - mult = div = 1; + if (((chip_id & CHIP_REVISION_ID) >> 16) >= 2) { + if (val & BIT(24)) { + /* Pass through mode */ + mult = div = 1; + } else { + /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */ + u32 m = val & 0x1fff; + u32 n = (val >> 13) & 0x3f; + u32 p = (val >> 19) & 0xf; + + mult = (m + 1); + div = (n + 1) * (p + 1); + } } else { - /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ - u32 m = (val >> 5) & 0x3f; - u32 od = (val >> 4) & 0x1; - u32 n = val & 0xf; + if (val & BIT(20)) { + /* Pass through mode */ + mult = div = 1; + } else { + /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ + u32 m = (val >> 5) & 0x3f; + u32 od = (val >> 4) & 0x1; + u32 n = val & 0xf; - mult = (2 - od) * (m + 2); - div = n + 1; + mult = (2 - od) * (m + 2); + div = n + 1; + } } return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, mult, div); -- 2.17.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/1] clk: aspeed: Fix APLL calculate formula for ast2600-A2 2021-01-18 10:08 ` [PATCH 1/1] clk: aspeed: Fix APLL calculate formula for ast2600-A2 Ryan Chen @ 2021-01-19 2:20 ` Joel Stanley 2021-01-19 3:04 ` Ryan Chen 2021-01-19 6:17 ` [PATCH v2] clk: aspeed: Fix APLL calculate formula from ast2600-A2 Ryan Chen 1 sibling, 1 reply; 9+ messages in thread From: Joel Stanley @ 2021-01-19 2:20 UTC (permalink / raw) To: Ryan Chen, Michael Turquette, Stephen Boyd, linux-clk, linux-kernel, andrewrj, BMC-SW Cc: joel, Andrew Jeffery On Mon, 2021-01-18 at 18:08 +0800, Ryan Chen wrote: > AST2600A1/A2 have different pll calculate formula. To clarify, only the A0 has the old calculation, and all subsequent revisions use the new calculation? If this is the case, do we need to support A0 in mainline linux, or should we drop support for A0 and only support A1, A2 and onwards? You should add a line to indicate this is a fix: Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC") Also, when sending single patches you do not need to include the cover letter. You should include all of the relevant information in the patch's commit message. > > Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> > --- > drivers/clk/clk-ast2600.c | 37 +++++++++++++++++++++++++++---------- > 1 file changed, 27 insertions(+), 10 deletions(-) > > diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c > index bbacaccad554..8933bd1506b3 100644 > --- a/drivers/clk/clk-ast2600.c > +++ b/drivers/clk/clk-ast2600.c > @@ -17,7 +17,8 @@ > > #define ASPEED_G6_NUM_CLKS 71 > > -#define ASPEED_G6_SILICON_REV 0x004 > +#define ASPEED_G6_SILICON_REV 0x014 > +#define CHIP_REVISION_ID GENMASK(23, 16) > > #define ASPEED_G6_RESET_CTRL 0x040 > #define ASPEED_G6_RESET_CTRL2 0x050 > @@ -190,18 +191,34 @@ static struct clk_hw *ast2600_calc_pll(const > char *name, u32 val) > static struct clk_hw *ast2600_calc_apll(const char *name, u32 val) > { > unsigned int mult, div; > + u32 chip_id = readl(scu_g6_base + ASPEED_G6_SILICON_REV); > > - if (val & BIT(20)) { > - /* Pass through mode */ > - mult = div = 1; > + if (((chip_id & CHIP_REVISION_ID) >> 16) >= 2) { > + if (val & BIT(24)) { > + /* Pass through mode */ > + mult = div = 1; > + } else { > + /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) > */ > + u32 m = val & 0x1fff; > + u32 n = (val >> 13) & 0x3f; > + u32 p = (val >> 19) & 0xf; > + > + mult = (m + 1); > + div = (n + 1) * (p + 1); > + } > } else { > - /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ > - u32 m = (val >> 5) & 0x3f; > - u32 od = (val >> 4) & 0x1; > - u32 n = val & 0xf; > + if (val & BIT(20)) { > + /* Pass through mode */ > + mult = div = 1; > + } else { > + /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] > */ > + u32 m = (val >> 5) & 0x3f; > + u32 od = (val >> 4) & 0x1; > + u32 n = val & 0xf; > > - mult = (2 - od) * (m + 2); > - div = n + 1; > + mult = (2 - od) * (m + 2); > + div = n + 1; > + } > } > return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, > mult, div); ^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH 1/1] clk: aspeed: Fix APLL calculate formula for ast2600-A2 2021-01-19 2:20 ` Joel Stanley @ 2021-01-19 3:04 ` Ryan Chen 2021-01-19 3:10 ` Joel Stanley 0 siblings, 1 reply; 9+ messages in thread From: Ryan Chen @ 2021-01-19 3:04 UTC (permalink / raw) To: Joel Stanley, Michael Turquette, Stephen Boyd, linux-clk, linux-kernel, andrewrj, BMC-SW Cc: joel, Andrew Jeffery > -----Original Message----- > From: Joel Stanley <joel@linux.ibm.com> > Sent: Tuesday, January 19, 2021 10:20 AM > To: Ryan Chen <ryan_chen@aspeedtech.com>; Michael Turquette > <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; > linux-clk@vger.kernel.org; linux-kernel@vger.kernel.org; > andrewrj@au1.ibm.com; BMC-SW <BMC-SW@aspeedtech.com> > Cc: joel@jms.id.au; Andrew Jeffery <andrew@aj.id.au> > Subject: Re: [PATCH 1/1] clk: aspeed: Fix APLL calculate formula for ast2600-A2 > > On Mon, 2021-01-18 at 18:08 +0800, Ryan Chen wrote: > > AST2600A1/A2 have different pll calculate formula. > > To clarify, only the A0 has the old calculation, and all subsequent revisions use > the new calculation? > > If this is the case, do we need to support A0 in mainline linux, or should we > drop support for A0 and only support A1, A2 and onwards? > A0/A1 is use older calculate formula After A2 is new calculate formula as the patch. > You should add a line to indicate this is a fix: > > Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC") > Got it. so should I send new patch? > Also, when sending single patches you do not need to include the cover letter. > You should include all of the relevant information in the patch's commit > message. > > > > > Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> > > --- > > drivers/clk/clk-ast2600.c | 37 +++++++++++++++++++++++++++---------- > > 1 file changed, 27 insertions(+), 10 deletions(-) > > > > diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c > > index bbacaccad554..8933bd1506b3 100644 > > --- a/drivers/clk/clk-ast2600.c > > +++ b/drivers/clk/clk-ast2600.c > > @@ -17,7 +17,8 @@ > > > > #define ASPEED_G6_NUM_CLKS 71 > > > > -#define ASPEED_G6_SILICON_REV 0x004 > > +#define ASPEED_G6_SILICON_REV 0x014 #define > CHIP_REVISION_ID > > +GENMASK(23, 16) > > > > #define ASPEED_G6_RESET_CTRL 0x040 > > #define ASPEED_G6_RESET_CTRL2 0x050 @@ -190,18 > +191,34 @@ > > static struct clk_hw *ast2600_calc_pll(const char *name, u32 val) > > static struct clk_hw *ast2600_calc_apll(const char *name, u32 val) > > { > > unsigned int mult, div; > > + u32 chip_id = readl(scu_g6_base + ASPEED_G6_SILICON_REV); > > > > - if (val & BIT(20)) { > > - /* Pass through mode */ > > - mult = div = 1; > > + if (((chip_id & CHIP_REVISION_ID) >> 16) >= 2) { > > + if (val & BIT(24)) { > > + /* Pass through mode */ > > + mult = div = 1; > > + } else { > > + /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + > 1) > > */ > > + u32 m = val & 0x1fff; > > + u32 n = (val >> 13) & 0x3f; > > + u32 p = (val >> 19) & 0xf; > > + > > + mult = (m + 1); > > + div = (n + 1) * (p + 1); > > + } > > } else { > > - /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ > > - u32 m = (val >> 5) & 0x3f; > > - u32 od = (val >> 4) & 0x1; > > - u32 n = val & 0xf; > > + if (val & BIT(20)) { > > + /* Pass through mode */ > > + mult = div = 1; > > + } else { > > + /* F = 25Mhz * (2-od) * [(m + 2) / (n + > 1)] > > */ > > + u32 m = (val >> 5) & 0x3f; > > + u32 od = (val >> 4) & 0x1; > > + u32 n = val & 0xf; > > > > - mult = (2 - od) * (m + 2); > > - div = n + 1; > > + mult = (2 - od) * (m + 2); > > + div = n + 1; > > + } > > } > > return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, > > mult, div); > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/1] clk: aspeed: Fix APLL calculate formula for ast2600-A2 2021-01-19 3:04 ` Ryan Chen @ 2021-01-19 3:10 ` Joel Stanley 2021-01-19 3:29 ` Ryan Chen 0 siblings, 1 reply; 9+ messages in thread From: Joel Stanley @ 2021-01-19 3:10 UTC (permalink / raw) To: Ryan Chen Cc: Joel Stanley, Michael Turquette, Stephen Boyd, linux-clk, linux-kernel, andrewrj, BMC-SW, Andrew Jeffery On Tue, 19 Jan 2021 at 03:04, Ryan Chen <ryan_chen@aspeedtech.com> wrote: > > > -----Original Message----- > > From: Joel Stanley <joel@linux.ibm.com> > > Sent: Tuesday, January 19, 2021 10:20 AM > > To: Ryan Chen <ryan_chen@aspeedtech.com>; Michael Turquette > > <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; > > linux-clk@vger.kernel.org; linux-kernel@vger.kernel.org; > > andrewrj@au1.ibm.com; BMC-SW <BMC-SW@aspeedtech.com> > > Cc: joel@jms.id.au; Andrew Jeffery <andrew@aj.id.au> > > Subject: Re: [PATCH 1/1] clk: aspeed: Fix APLL calculate formula for ast2600-A2 > > > > On Mon, 2021-01-18 at 18:08 +0800, Ryan Chen wrote: > > > AST2600A1/A2 have different pll calculate formula. > > > > To clarify, only the A0 has the old calculation, and all subsequent revisions use > > the new calculation? > > > > If this is the case, do we need to support A0 in mainline linux, or should we > > drop support for A0 and only support A1, A2 and onwards? > > > A0/A1 is use older calculate formula > After A2 is new calculate formula as the patch. Thanks for clarifying. I suggest you change the commit log to say something like this: Starting from A2, the A-PLL calculation has changed. Use the existing formula for A0/A1 and the new formula for A2 onwards. > > > You should add a line to indicate this is a fix: > > > > Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC") > > > Got it. so should I send new patch? Yes, please consider adjusting the commit message as I suggested above, and add the fixes line. > > > + u32 chip_id = readl(scu_g6_base + ASPEED_G6_SILICON_REV); > > > > > > - if (val & BIT(20)) { > > > - /* Pass through mode */ > > > - mult = div = 1; > > > + if (((chip_id & CHIP_REVISION_ID) >> 16) >= 2) { Will this test be true if there are future versions of the chip (A3, etc)? Cheers, Joel ^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH 1/1] clk: aspeed: Fix APLL calculate formula for ast2600-A2 2021-01-19 3:10 ` Joel Stanley @ 2021-01-19 3:29 ` Ryan Chen 0 siblings, 0 replies; 9+ messages in thread From: Ryan Chen @ 2021-01-19 3:29 UTC (permalink / raw) To: Joel Stanley Cc: Joel Stanley, Michael Turquette, Stephen Boyd, linux-clk, linux-kernel, andrewrj, BMC-SW, Andrew Jeffery > -----Original Message----- > From: Joel Stanley <joel@jms.id.au> > Sent: Tuesday, January 19, 2021 11:10 AM > To: Ryan Chen <ryan_chen@aspeedtech.com> > Cc: Joel Stanley <joel@linux.ibm.com>; Michael Turquette > <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; > linux-clk@vger.kernel.org; linux-kernel@vger.kernel.org; > andrewrj@au1.ibm.com; BMC-SW <BMC-SW@aspeedtech.com>; Andrew > Jeffery <andrew@aj.id.au> > Subject: Re: [PATCH 1/1] clk: aspeed: Fix APLL calculate formula for ast2600-A2 > > On Tue, 19 Jan 2021 at 03:04, Ryan Chen <ryan_chen@aspeedtech.com> > wrote: > > > > > -----Original Message----- > > > From: Joel Stanley <joel@linux.ibm.com> > > > Sent: Tuesday, January 19, 2021 10:20 AM > > > To: Ryan Chen <ryan_chen@aspeedtech.com>; Michael Turquette > > > <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; > > > linux-clk@vger.kernel.org; linux-kernel@vger.kernel.org; > > > andrewrj@au1.ibm.com; BMC-SW <BMC-SW@aspeedtech.com> > > > Cc: joel@jms.id.au; Andrew Jeffery <andrew@aj.id.au> > > > Subject: Re: [PATCH 1/1] clk: aspeed: Fix APLL calculate formula for > > > ast2600-A2 > > > > > > On Mon, 2021-01-18 at 18:08 +0800, Ryan Chen wrote: > > > > AST2600A1/A2 have different pll calculate formula. > > > > > > To clarify, only the A0 has the old calculation, and all subsequent > > > revisions use the new calculation? > > > > > > If this is the case, do we need to support A0 in mainline linux, or > > > should we drop support for A0 and only support A1, A2 and onwards? > > > > > A0/A1 is use older calculate formula > > After A2 is new calculate formula as the patch. > > Thanks for clarifying. I suggest you change the commit log to say something > like this: > > Starting from A2, the A-PLL calculation has changed. Use the existing formula > for A0/A1 and the new formula for A2 onwards. > > > > > > You should add a line to indicate this is a fix: > > > > > > Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC") > > > > > Got it. so should I send new patch? > > Yes, please consider adjusting the commit message as I suggested above, and > add the fixes line. > > > > > + u32 chip_id = readl(scu_g6_base + ASPEED_G6_SILICON_REV); > > > > > > > > - if (val & BIT(20)) { > > > > - /* Pass through mode */ > > > > - mult = div = 1; > > > > + if (((chip_id & CHIP_REVISION_ID) >> 16) >= 2) { > > Will this test be true if there are future versions of the chip (A3, etc)? Yes, is also support for A3. ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2] clk: aspeed: Fix APLL calculate formula from ast2600-A2 2021-01-18 10:08 ` [PATCH 1/1] clk: aspeed: Fix APLL calculate formula for ast2600-A2 Ryan Chen 2021-01-19 2:20 ` Joel Stanley @ 2021-01-19 6:17 ` Ryan Chen 2021-01-19 11:48 ` Joel Stanley 2021-02-11 20:36 ` Stephen Boyd 1 sibling, 2 replies; 9+ messages in thread From: Ryan Chen @ 2021-01-19 6:17 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, linux-clk, linux-kernel, andrewrj, joel, BMC-SW Cc: Ryan Chen Starting from A2, the A-PLL calculation has changed. Use the existing formula for A0/A1 and the new formula for A2 onwards. Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC") Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> --- drivers/clk/clk-ast2600.c | 37 +++++++++++++++++++++++++++---------- 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c index bbacaccad554..8933bd1506b3 100644 --- a/drivers/clk/clk-ast2600.c +++ b/drivers/clk/clk-ast2600.c @@ -17,7 +17,8 @@ #define ASPEED_G6_NUM_CLKS 71 -#define ASPEED_G6_SILICON_REV 0x004 +#define ASPEED_G6_SILICON_REV 0x014 +#define CHIP_REVISION_ID GENMASK(23, 16) #define ASPEED_G6_RESET_CTRL 0x040 #define ASPEED_G6_RESET_CTRL2 0x050 @@ -190,18 +191,34 @@ static struct clk_hw *ast2600_calc_pll(const char *name, u32 val) static struct clk_hw *ast2600_calc_apll(const char *name, u32 val) { unsigned int mult, div; + u32 chip_id = readl(scu_g6_base + ASPEED_G6_SILICON_REV); - if (val & BIT(20)) { - /* Pass through mode */ - mult = div = 1; + if (((chip_id & CHIP_REVISION_ID) >> 16) >= 2) { + if (val & BIT(24)) { + /* Pass through mode */ + mult = div = 1; + } else { + /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */ + u32 m = val & 0x1fff; + u32 n = (val >> 13) & 0x3f; + u32 p = (val >> 19) & 0xf; + + mult = (m + 1); + div = (n + 1) * (p + 1); + } } else { - /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ - u32 m = (val >> 5) & 0x3f; - u32 od = (val >> 4) & 0x1; - u32 n = val & 0xf; + if (val & BIT(20)) { + /* Pass through mode */ + mult = div = 1; + } else { + /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ + u32 m = (val >> 5) & 0x3f; + u32 od = (val >> 4) & 0x1; + u32 n = val & 0xf; - mult = (2 - od) * (m + 2); - div = n + 1; + mult = (2 - od) * (m + 2); + div = n + 1; + } } return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, mult, div); -- 2.17.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2] clk: aspeed: Fix APLL calculate formula from ast2600-A2 2021-01-19 6:17 ` [PATCH v2] clk: aspeed: Fix APLL calculate formula from ast2600-A2 Ryan Chen @ 2021-01-19 11:48 ` Joel Stanley 2021-02-11 20:36 ` Stephen Boyd 1 sibling, 0 replies; 9+ messages in thread From: Joel Stanley @ 2021-01-19 11:48 UTC (permalink / raw) To: Ryan Chen Cc: Michael Turquette, Stephen Boyd, linux-clk, Linux Kernel Mailing List, andrewrj, joel, BMC-SW On Tue, 19 Jan 2021 at 06:31, Ryan Chen <ryan_chen@aspeedtech.com> wrote: > > Starting from A2, the A-PLL calculation has changed. Use the > existing formula for A0/A1 and the new formula for A2 onwards. > > Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC") > Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> > --- > drivers/clk/clk-ast2600.c | 37 +++++++++++++++++++++++++++---------- > 1 file changed, 27 insertions(+), 10 deletions(-) > > diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c > index bbacaccad554..8933bd1506b3 100644 > --- a/drivers/clk/clk-ast2600.c > +++ b/drivers/clk/clk-ast2600.c > @@ -17,7 +17,8 @@ > > #define ASPEED_G6_NUM_CLKS 71 > > -#define ASPEED_G6_SILICON_REV 0x004 > +#define ASPEED_G6_SILICON_REV 0x014 > +#define CHIP_REVISION_ID GENMASK(23, 16) > > #define ASPEED_G6_RESET_CTRL 0x040 > #define ASPEED_G6_RESET_CTRL2 0x050 > @@ -190,18 +191,34 @@ static struct clk_hw *ast2600_calc_pll(const char *name, u32 val) > static struct clk_hw *ast2600_calc_apll(const char *name, u32 val) > { > unsigned int mult, div; > + u32 chip_id = readl(scu_g6_base + ASPEED_G6_SILICON_REV); > > - if (val & BIT(20)) { > - /* Pass through mode */ > - mult = div = 1; > + if (((chip_id & CHIP_REVISION_ID) >> 16) >= 2) { > + if (val & BIT(24)) { > + /* Pass through mode */ > + mult = div = 1; > + } else { > + /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */ > + u32 m = val & 0x1fff; > + u32 n = (val >> 13) & 0x3f; > + u32 p = (val >> 19) & 0xf; > + > + mult = (m + 1); > + div = (n + 1) * (p + 1); > + } > } else { > - /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ > - u32 m = (val >> 5) & 0x3f; > - u32 od = (val >> 4) & 0x1; > - u32 n = val & 0xf; > + if (val & BIT(20)) { > + /* Pass through mode */ > + mult = div = 1; > + } else { > + /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ > + u32 m = (val >> 5) & 0x3f; > + u32 od = (val >> 4) & 0x1; > + u32 n = val & 0xf; > > - mult = (2 - od) * (m + 2); > - div = n + 1; > + mult = (2 - od) * (m + 2); > + div = n + 1; > + } > } > return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, > mult, div); > -- > 2.17.1 > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] clk: aspeed: Fix APLL calculate formula from ast2600-A2 2021-01-19 6:17 ` [PATCH v2] clk: aspeed: Fix APLL calculate formula from ast2600-A2 Ryan Chen 2021-01-19 11:48 ` Joel Stanley @ 2021-02-11 20:36 ` Stephen Boyd 1 sibling, 0 replies; 9+ messages in thread From: Stephen Boyd @ 2021-02-11 20:36 UTC (permalink / raw) To: BMC-SW, Michael Turquette, Ryan Chen, andrewrj, joel, linux-clk, linux-kernel Cc: Ryan Chen Quoting Ryan Chen (2021-01-18 22:17:15) > Starting from A2, the A-PLL calculation has changed. Use the > existing formula for A0/A1 and the new formula for A2 onwards. > > Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC") > Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> > --- Applied to clk-next ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-02-11 20:37 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-01-18 10:08 [PATCH 0/1] Fix AST2600A2 APLL calculate formuula Ryan Chen 2021-01-18 10:08 ` [PATCH 1/1] clk: aspeed: Fix APLL calculate formula for ast2600-A2 Ryan Chen 2021-01-19 2:20 ` Joel Stanley 2021-01-19 3:04 ` Ryan Chen 2021-01-19 3:10 ` Joel Stanley 2021-01-19 3:29 ` Ryan Chen 2021-01-19 6:17 ` [PATCH v2] clk: aspeed: Fix APLL calculate formula from ast2600-A2 Ryan Chen 2021-01-19 11:48 ` Joel Stanley 2021-02-11 20:36 ` Stephen Boyd
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).