* [PATCH v6 1/8] MIPS: Loongson: Merge PRID macro for Loongson-1A/1B/1C
2017-03-30 2:44 [PATCH v6 0/8] MIPS: Loongson: Add the Loongson-1A processor support Binbin Zhou
@ 2017-03-30 2:44 ` Binbin Zhou
2017-03-30 9:50 ` Sergei Shtylyov
2017-03-30 2:44 ` [PATCH RESEND v6 2/8] MIPS: Loongson: Expand Loongson-1's register definition Binbin Zhou
` (6 subsequent siblings)
7 siblings, 1 reply; 11+ messages in thread
From: Binbin Zhou @ 2017-03-30 2:44 UTC (permalink / raw)
To: Ralf Baechle, James Hogan
Cc: John Crispin, Steven J . Hill, Aurelien Jarno, Fuxin Zhang,
Zhangjin Wu, Kelvin Cheung, Yang Ling, 谢致邦,
linux-mips, Binbin Zhou, HuaCai Chen
As we all know, the Loongson-1 series CPUs(1A/1B/1C) share the same PRID macro.
so I rename them for more readable.
Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: HuaCai Chen <chenhc@lemote.com>
---
arch/mips/include/asm/cpu.h | 3 +--
arch/mips/kernel/cpu-probe.c | 4 +++-
arch/mips/loongson32/common/setup.c | 2 +-
3 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 9a83724..76c0b56c3 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -239,8 +239,7 @@
#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
#define PRID_REV_VR4130 0x0080
#define PRID_REV_34K_V1_0_2 0x0022
-#define PRID_REV_LOONGSON1B 0x0020
-#define PRID_REV_LOONGSON1C 0x0020 /* Same as Loongson-1B */
+#define PRID_REV_LOONGSON1ABC 0x0020
#define PRID_REV_LOONGSON2E 0x0002
#define PRID_REV_LOONGSON2F 0x0003
#define PRID_REV_LOONGSON3A_R1 0x0005
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 07718bb..657d65d 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1502,8 +1502,10 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
c->cputype = CPU_LOONGSON1;
switch (c->processor_id & PRID_REV_MASK) {
- case PRID_REV_LOONGSON1B:
+ case PRID_REV_LOONGSON1ABC:
+#ifdef CONFIG_CPU_LOONGSON1B
__cpu_name[cpu] = "Loongson 1B";
+#endif
break;
}
diff --git a/arch/mips/loongson32/common/setup.c b/arch/mips/loongson32/common/setup.c
index 1640744..c8e8b3e 100644
--- a/arch/mips/loongson32/common/setup.c
+++ b/arch/mips/loongson32/common/setup.c
@@ -21,7 +21,7 @@ const char *get_system_type(void)
unsigned int processor_id = (¤t_cpu_data)->processor_id;
switch (processor_id & PRID_REV_MASK) {
- case PRID_REV_LOONGSON1B:
+ case PRID_REV_LOONGSON1ABC:
#if defined(CONFIG_LOONGSON1_LS1B)
return "LOONGSON LS1B";
#elif defined(CONFIG_LOONGSON1_LS1C)
--
2.9.3
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v6 1/8] MIPS: Loongson: Merge PRID macro for Loongson-1A/1B/1C
2017-03-30 2:44 ` [PATCH v6 1/8] MIPS: Loongson: Merge PRID macro for Loongson-1A/1B/1C Binbin Zhou
@ 2017-03-30 9:50 ` Sergei Shtylyov
2017-04-24 14:52 ` Yang Ling
0 siblings, 1 reply; 11+ messages in thread
From: Sergei Shtylyov @ 2017-03-30 9:50 UTC (permalink / raw)
To: Binbin Zhou, Ralf Baechle, James Hogan
Cc: John Crispin, Steven J . Hill, Aurelien Jarno, Fuxin Zhang,
Zhangjin Wu, Kelvin Cheung, Yang Ling, 谢致邦,
linux-mips, HuaCai Chen
Hello!
On 3/30/2017 5:44 AM, Binbin Zhou wrote:
> As we all know, the Loongson-1 series CPUs(1A/1B/1C) share the same PRID macro.
> so I rename them for more readable.
"Better readability", perhaps?
> Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
> Signed-off-by: HuaCai Chen <chenhc@lemote.com>
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v6 1/8] MIPS: Loongson: Merge PRID macro for Loongson-1A/1B/1C
2017-03-30 9:50 ` Sergei Shtylyov
@ 2017-04-24 14:52 ` Yang Ling
0 siblings, 0 replies; 11+ messages in thread
From: Yang Ling @ 2017-04-24 14:52 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Binbin Zhou, Ralf Baechle, James Hogan, John Crispin,
Steven J . Hill, Aurelien Jarno, Fuxin Zhang, Zhangjin Wu,
Kelvin Cheung, Yang Ling, ?????????,
linux-mips, HuaCai Chen
Hi, Sergei,
I think this modification is appropriate, otherwise if the future
support 1D, 1E and so on, the same PRID here will appear strange.
Yang
On Thu, Mar 30, 2017 at 12:50:55PM +0300, Sergei Shtylyov wrote:
> Hello!
>
> On 3/30/2017 5:44 AM, Binbin Zhou wrote:
>
> >As we all know, the Loongson-1 series CPUs(1A/1B/1C) share the same PRID macro.
> >so I rename them for more readable.
>
> "Better readability", perhaps?
>
> >Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
> >Signed-off-by: HuaCai Chen <chenhc@lemote.com>
> [...]
>
> MBR, Sergei
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH RESEND v6 2/8] MIPS: Loongson: Expand Loongson-1's register definition
2017-03-30 2:44 [PATCH v6 0/8] MIPS: Loongson: Add the Loongson-1A processor support Binbin Zhou
2017-03-30 2:44 ` [PATCH v6 1/8] MIPS: Loongson: Merge PRID macro for Loongson-1A/1B/1C Binbin Zhou
@ 2017-03-30 2:44 ` Binbin Zhou
2017-03-30 2:44 ` [PATCH v6 3/8] MIPS: Loongson: Add basic Loongson-1A CPU support Binbin Zhou
` (5 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Binbin Zhou @ 2017-03-30 2:44 UTC (permalink / raw)
To: Ralf Baechle, James Hogan
Cc: John Crispin, Steven J . Hill, Aurelien Jarno, Fuxin Zhang,
Zhangjin Wu, Kelvin Cheung, Yang Ling, 谢致邦,
linux-mips, Binbin Zhou, HuaCai Chen
Rewrite their names for more readable.
Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: HuaCai Chen <chenhc@lemote.com>
---
arch/mips/include/asm/mach-loongson32/loongson1.h | 170 ++++++++++++++++++----
arch/mips/loongson32/common/platform.c | 16 +-
2 files changed, 149 insertions(+), 37 deletions(-)
diff --git a/arch/mips/include/asm/mach-loongson32/loongson1.h b/arch/mips/include/asm/mach-loongson32/loongson1.h
index 84c28a8..8cfd4ba 100644
--- a/arch/mips/include/asm/mach-loongson32/loongson1.h
+++ b/arch/mips/include/asm/mach-loongson32/loongson1.h
@@ -19,35 +19,147 @@
#endif
/* Loongson 1 Register Bases */
-#define LS1X_MUX_BASE 0x1fd00420
-#define LS1X_INTC_BASE 0x1fd01040
-#define LS1X_GPIO0_BASE 0x1fd010c0
-#define LS1X_GPIO1_BASE 0x1fd010c4
-#define LS1X_DMAC_BASE 0x1fd01160
-#define LS1X_CBUS_BASE 0x1fd011c0
-#define LS1X_EHCI_BASE 0x1fe00000
-#define LS1X_OHCI_BASE 0x1fe08000
-#define LS1X_GMAC0_BASE 0x1fe10000
-#define LS1X_GMAC1_BASE 0x1fe20000
-
-#define LS1X_UART0_BASE 0x1fe40000
-#define LS1X_UART1_BASE 0x1fe44000
-#define LS1X_UART2_BASE 0x1fe48000
-#define LS1X_UART3_BASE 0x1fe4c000
-#define LS1X_CAN0_BASE 0x1fe50000
-#define LS1X_CAN1_BASE 0x1fe54000
-#define LS1X_I2C0_BASE 0x1fe58000
-#define LS1X_I2C1_BASE 0x1fe68000
-#define LS1X_I2C2_BASE 0x1fe70000
-#define LS1X_PWM0_BASE 0x1fe5c000
-#define LS1X_PWM1_BASE 0x1fe5c010
-#define LS1X_PWM2_BASE 0x1fe5c020
-#define LS1X_PWM3_BASE 0x1fe5c030
-#define LS1X_WDT_BASE 0x1fe5c060
-#define LS1X_RTC_BASE 0x1fe64000
-#define LS1X_AC97_BASE 0x1fe74000
-#define LS1X_NAND_BASE 0x1fe78000
-#define LS1X_CLK_BASE 0x1fe78030
+#define LS1X_DC_REG_BASE 0x1c200000
+#define LS1X_MUX_REG_BASE 0x1f000000
+
+#define LS1X_CFG_REG_BASE (LS1X_MUX_REG_BASE + 0x00d00000)
+
+#define LS1X_INTC_BASE (LS1X_CFG_REG_BASE + 0x1040)
+
+/* GPIO regs */
+#define LS1X_GPIO_REG_BASE (LS1X_CFG_REG_BASE + 0x1000)
+#define LS1X_GPIO_CFG0_REG (LS1X_GPIO_REG_BASE + 0xc0)
+#define LS1X_GPIO_CFG1_REG (LS1X_GPIO_REG_BASE + 0xc4)
+#define LS1X_GPIO_CFG2_REG (LS1X_GPIO_REG_BASE + 0xc8)
+#define LS1X_GPIO_OE0_REG (LS1X_GPIO_REG_BASE + 0xd0)
+#define LS1X_GPIO_OE1_REG (LS1X_GPIO_REG_BASE + 0xd4)
+#define LS1X_GPIO_OE2_REG (LS1X_GPIO_REG_BASE + 0xd8)
+#define LS1X_GPIO_IN0_REG (LS1X_GPIO_REG_BASE + 0xe0)
+#define LS1X_GPIO_IN1_REG (LS1X_GPIO_REG_BASE + 0xe4)
+#define LS1X_GPIO_IN2_REG (LS1X_GPIO_REG_BASE + 0xe8)
+#define LS1X_GPIO_OUT0_REG (LS1X_GPIO_REG_BASE + 0xf0)
+#define LS1X_GPIO_OUT1_REG (LS1X_GPIO_REG_BASE + 0xf4)
+#define LS1X_GPIO_OUT2_REG (LS1X_GPIO_REG_BASE + 0xf8)
+
+#define LS1X_DMA_ORDER_REG (LS1X_CFG_REG_BASE + 0x1160)
+
+#define LS1X_MUX_BASE (LS1X_CFG_REG_BASE + 0x0420)
+
+/* USB regs */
+#define LS1X_EHCI_BASE (LS1X_MUX_REG_BASE + 0x00e00000)
+#define LS1X_OHCI_BASE (LS1X_MUX_REG_BASE + 0x00e08000)
+
+/* GMAC regs */
+#define LS1X_GMAC0_BASE (LS1X_MUX_REG_BASE + 0x00e10000)
+#define LS1X_GMAC0_DMA_REG (LS1X_GMAC0_BASE + 0x1000)
+#define LS1X_GMAC1_BASE (LS1X_MUX_REG_BASE + 0x00e20000)
+#define LS1X_GMAC1_DMA_REG (LS1X_GMAC1_BASE + 0x1000)
+
+/* SATA regs */
+#define LS1X_AHCI_BASE (LS1X_MUX_REG_BASE + 0x00e30000)
+
+/* APB regs */
+#define LS1X_APB_REG_BASE (LS1X_MUX_REG_BASE + 0x00e40000)
+
+/* UART regs */
+#define LS1X_UART0_BASE (LS1X_APB_REG_BASE + 0x0000)
+#define LS1X_UART1_BASE (LS1X_APB_REG_BASE + 0x4000)
+#define LS1X_UART2_BASE (LS1X_APB_REG_BASE + 0x8000)
+#define LS1X_UART3_BASE (LS1X_APB_REG_BASE + 0xc000)
+
+/* CAN regs */
+#define LS1X_CAN0_BASE (LS1X_APB_REG_BASE + 0x10000)
+#define LS1X_CAN1_BASE (LS1X_APB_REG_BASE + 0x14000)
+
+#define LS1X_I2C0_BASE (LS1X_APB_REG_BASE + 0x18000)
+#define LS1X_I2C0_PRER_LO_REG (LS1X_I2C0_BASE + 0x0)
+#define LS1X_I2C0_PRER_HI_REG (LS1X_I2C0_BASE + 0x1)
+#define LS1X_I2C0_CTR_REG (LS1X_I2C0_BASE + 0x2)
+#define LS1X_I2C0_TXR_REG (LS1X_I2C0_BASE + 0x3)
+#define LS1X_I2C0_RXR_REG (LS1X_I2C0_BASE + 0x3)
+#define LS1X_I2C0_CR_REG (LS1X_I2C0_BASE + 0x4)
+#define LS1X_I2C0_SR_REG (LS1X_I2C0_BASE + 0x4)
+
+#define LS1X_I2C1_BASE (LS1X_APB_REG_BASE + 0x28000)
+#define LS1X_I2C1_PRER_LO_REG (LS1X_I2C1_BASE + 0x0)
+#define LS1X_I2C1_PRER_HI_REG (LS1X_I2C1_BASE + 0x1)
+#define LS1X_I2C1_CTR_REG (LS1X_I2C1_BASE + 0x2)
+#define LS1X_I2C1_TXR_REG (LS1X_I2C1_BASE + 0x3)
+#define LS1X_I2C1_RXR_REG (LS1X_I2C1_BASE + 0x3)
+#define LS1X_I2C1_CR_REG (LS1X_I2C1_BASE + 0x4)
+#define LS1X_I2C1_SR_REG (LS1X_I2C1_BASE + 0x4)
+
+#define LS1X_I2C2_BASE (LS1X_APB_REG_BASE + 0x30000)
+#define LS1X_I2C2_PRER_LO_REG (LS1X_I2C2_BASE + 0x0)
+#define LS1X_I2C2_PRER_HI_REG (LS1X_I2C2_BASE + 0x1)
+#define LS1X_I2C2_CTR_REG (LS1X_I2C2_BASE + 0x2)
+#define LS1X_I2C2_TXR_REG (LS1X_I2C2_BASE + 0x3)
+#define LS1X_I2C2_RXR_REG (LS1X_I2C2_BASE + 0x3)
+#define LS1X_I2C2_CR_REG (LS1X_I2C2_BASE + 0x4)
+#define LS1X_I2C2_SR_REG (LS1X_I2C2_BASE + 0x4)
+
+#define LS1X_PWM_REG_BASE (LS1X_APB_REG_BASE + 0x1c000)
+#define LS1X_PWM0_BASE (LS1X_PWM_REG_BASE + 0x00)
+#define LS1X_PWM1_BASE (LS1X_PWM_REG_BASE + 0x10)
+#define LS1X_PWM2_BASE (LS1X_PWM_REG_BASE + 0x20)
+#define LS1X_PWM3_BASE (LS1X_PWM_REG_BASE + 0x30)
+
+/* RTC regs */
+#define LS1X_RTC_BASE (LS1X_APB_REG_BASE + 0x24000)
+
+/* AC97 regs */
+#define LS1X_AC97_BASE (LS1X_APB_REG_BASE + 0x34000)
+
+/* Watchdog regs */
+#ifdef CONFIG_CPU_LOONGSON1A
+#define LS1X_WDT_BASE (LS1X_MUX_REG_BASE + 0x00e7c060)
+#else
+#define LS1X_WDT_BASE (LS1X_MUX_REG_BASE + 0x00e5c060)
+#endif
+
+/* CLK regs */
+#define LS1X_CLK_BASE (LS1X_MUX_REG_BASE + 0x00e78030)
+
+/* NAND regs */
+#define LS1X_NAND_REG_BASE (LS1X_APB_REG_BASE + 0x38000)
+#define LS1X_NAND_CMD_REG (LS1X_NAND_REG_BASE + 0x0000)
+#define LS1X_NAND_ADDR_C_REG (LS1X_NAND_REG_BASE + 0x0004)
+#define LS1X_NAND_ADDR_R_REG (LS1X_NAND_REG_BASE + 0x0008)
+#define LS1X_NAND_TIMING_REG (LS1X_NAND_REG_BASE + 0x000c)
+#define LS1X_NAND_IDL_REG (LS1X_NAND_REG_BASE + 0x0010)
+#define LS1X_NAND_STA_IDH_REG (LS1X_NAND_REG_BASE + 0x0014)
+#define LS1X_NAND_PARAM_REG (LS1X_NAND_REG_BASE + 0x0018)
+#define LS1X_NAND_OP_NUM_REG (LS1X_NAND_REG_BASE + 0x001c)
+#define LS1X_NAND_CSRDY_MAP_REG (LS1X_NAND_REG_BASE + 0x0020)
+#define LS1X_NAND_DMA_ACC_REG (LS1X_NAND_REG_BASE + 0x0040)
+
+/* ACPI regs for ls1a */
+#define LS1X_ACPI_REG_BASE (LS1X_APB_REG_BASE + 0x3c000)
+#define LS1X_PM1_STS_REG (LS1X_ACPI_REG_BASE + 0x0000)
+#define LS1X_PM1_EN_REG (LS1X_ACPI_REG_BASE + 0x0004)
+#define LS1X_PM1_CNT_REG (LS1X_ACPI_REG_BASE + 0x0008)
+#define LS1X_PM1_TMR_REG (LS1X_ACPI_REG_BASE + 0x000c)
+#define LS1X_P_CNT_REG (LS1X_ACPI_REG_BASE + 0x0010)
+#define LS1X_P_LVL2_REG (LS1X_ACPI_REG_BASE + 0x0014)
+#define LS1X_P_LVL3_REG (LS1X_ACPI_REG_BASE + 0x0018)
+#define LS1X_GPE0_STS_REG (LS1X_ACPI_REG_BASE + 0x0020)
+#define LS1X_GPE0_EN_REG (LS1X_ACPI_REG_BASE + 0x0024)
+#define LS1X_PM_CONF1_REG (LS1X_ACPI_REG_BASE + 0x0030)
+#define LS1X_PM_CONF2_REG (LS1X_ACPI_REG_BASE + 0x0034)
+#define LS1X_PM_CONF3_REG (LS1X_ACPI_REG_BASE + 0x0038)
+#define LS1X_RST_CNT_REG (LS1X_ACPI_REG_BASE + 0x0044)
+#define LS1X_CPU_INIT_REG (LS1X_ACPI_REG_BASE + 0x0050)
+
+#define LS1X_SPI0_REG_BASE (LS1X_MUX_REG_BASE + 0x00e80000)
+#define LS1X_SPI1_REG_BASE (LS1X_MUX_REG_BASE + 0x00ec0000)
+
+/* LPC regs */
+#define LS1X_LPC_IO_BASE (LS1X_MUX_REG_BASE + 0x00f00000)
+#define LS1X_LPC_REG_BASE (LS1X_MUX_REG_BASE + 0x00f10200)
+#define LS1X_LPC_CFG0_REG (LS1X_LPC_REG_BASE + 0x0)
+#define LS1X_LPC_CFG1_REG (LS1X_LPC_REG_BASE + 0x4)
+#define LS1X_LPC_CFG2_REG (LS1X_LPC_REG_BASE + 0x8)
+#define LS1X_LPC_CFG3_REG (LS1X_LPC_REG_BASE + 0xc)
#include <regs-clk.h>
#include <regs-mux.h>
diff --git a/arch/mips/loongson32/common/platform.c b/arch/mips/loongson32/common/platform.c
index 100f23d..f71392f 100644
--- a/arch/mips/loongson32/common/platform.c
+++ b/arch/mips/loongson32/common/platform.c
@@ -84,8 +84,8 @@ struct platform_device ls1x_cpufreq_pdev = {
/* DMA */
static struct resource ls1x_dma_resources[] = {
[0] = {
- .start = LS1X_DMAC_BASE,
- .end = LS1X_DMAC_BASE + SZ_4 - 1,
+ .start = LS1X_DMA_ORDER_REG,
+ .end = LS1X_DMA_ORDER_REG + SZ_4 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
@@ -259,8 +259,8 @@ struct platform_device ls1x_eth1_pdev = {
/* GPIO */
static struct resource ls1x_gpio0_resources[] = {
[0] = {
- .start = LS1X_GPIO0_BASE,
- .end = LS1X_GPIO0_BASE + SZ_4 - 1,
+ .start = LS1X_GPIO_CFG0_REG,
+ .end = LS1X_GPIO_CFG0_REG + SZ_4 - 1,
.flags = IORESOURCE_MEM,
},
};
@@ -274,8 +274,8 @@ struct platform_device ls1x_gpio0_pdev = {
static struct resource ls1x_gpio1_resources[] = {
[0] = {
- .start = LS1X_GPIO1_BASE,
- .end = LS1X_GPIO1_BASE + SZ_4 - 1,
+ .start = LS1X_GPIO_CFG1_REG,
+ .end = LS1X_GPIO_CFG1_REG + SZ_4 - 1,
.flags = IORESOURCE_MEM,
},
};
@@ -290,8 +290,8 @@ struct platform_device ls1x_gpio1_pdev = {
/* NAND Flash */
static struct resource ls1x_nand_resources[] = {
[0] = {
- .start = LS1X_NAND_BASE,
- .end = LS1X_NAND_BASE + SZ_32 - 1,
+ .start = LS1X_NAND_REG_BASE,
+ .end = LS1X_NAND_REG_BASE + SZ_32 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
--
2.9.3
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v6 3/8] MIPS: Loongson: Add basic Loongson-1A CPU support
2017-03-30 2:44 [PATCH v6 0/8] MIPS: Loongson: Add the Loongson-1A processor support Binbin Zhou
2017-03-30 2:44 ` [PATCH v6 1/8] MIPS: Loongson: Merge PRID macro for Loongson-1A/1B/1C Binbin Zhou
2017-03-30 2:44 ` [PATCH RESEND v6 2/8] MIPS: Loongson: Expand Loongson-1's register definition Binbin Zhou
@ 2017-03-30 2:44 ` Binbin Zhou
2017-03-30 2:44 ` [PATCH v6 4/8] MIPS: Loongson: Add Loongson-1A Kconfig options Binbin Zhou
` (4 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Binbin Zhou @ 2017-03-30 2:44 UTC (permalink / raw)
To: Ralf Baechle, James Hogan
Cc: John Crispin, Steven J . Hill, Aurelien Jarno, Fuxin Zhang,
Zhangjin Wu, Kelvin Cheung, Yang Ling, 谢致邦,
linux-mips, Binbin Zhou, HuaCai Chen
The Loongson-1A CPU is similar with Loongson-1B/1C, which is a 32-bit SoC.
It implements the MIPS32 release 2 instruction set.
It's a cost-effective single chip system based on LS232 processor core, and
is applicable to fields such as industrial control.
Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: HuaCai Chen <chenhc@lemote.com>
---
arch/mips/include/asm/cpu-type.h | 3 ++-
arch/mips/kernel/cpu-probe.c | 4 +++-
arch/mips/loongson32/Platform | 1 +
arch/mips/loongson32/common/setup.c | 4 +++-
arch/mips/mm/c-r4k.c | 10 ++++++++++
5 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index bdd6dc1..13ea1ea5 100644
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -24,7 +24,8 @@ static inline int __pure __get_cpu_type(const int cpu_type)
case CPU_LOONGSON3:
#endif
-#if defined(CONFIG_SYS_HAS_CPU_LOONGSON1B) || \
+#if defined(CONFIG_SYS_HAS_CPU_LOONGSON1A) || \
+ defined(CONFIG_SYS_HAS_CPU_LOONGSON1B) || \
defined(CONFIG_SYS_HAS_CPU_LOONGSON1C)
case CPU_LOONGSON1:
#endif
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 657d65d..59ad3b7 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1503,7 +1503,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
switch (c->processor_id & PRID_REV_MASK) {
case PRID_REV_LOONGSON1ABC:
-#ifdef CONFIG_CPU_LOONGSON1B
+#if defined(CONFIG_LOONGSON1_LS1A)
+ __cpu_name[cpu] = "Loongson 1A";
+#elif defined(CONFIG_CPU_LOONGSON1B)
__cpu_name[cpu] = "Loongson 1B";
#endif
break;
diff --git a/arch/mips/loongson32/Platform b/arch/mips/loongson32/Platform
index ffe01c6..a9e0fa7 100644
--- a/arch/mips/loongson32/Platform
+++ b/arch/mips/loongson32/Platform
@@ -4,5 +4,6 @@ cflags-$(CONFIG_CPU_LOONGSON1) += \
platform-$(CONFIG_MACH_LOONGSON32) += loongson32/
cflags-$(CONFIG_MACH_LOONGSON32) += -I$(srctree)/arch/mips/include/asm/mach-loongson32
+load-$(CONFIG_LOONGSON1_LS1A) += 0xffffffff80200000
load-$(CONFIG_LOONGSON1_LS1B) += 0xffffffff80100000
load-$(CONFIG_LOONGSON1_LS1C) += 0xffffffff80100000
diff --git a/arch/mips/loongson32/common/setup.c b/arch/mips/loongson32/common/setup.c
index c8e8b3e..1c3324a 100644
--- a/arch/mips/loongson32/common/setup.c
+++ b/arch/mips/loongson32/common/setup.c
@@ -22,7 +22,9 @@ const char *get_system_type(void)
switch (processor_id & PRID_REV_MASK) {
case PRID_REV_LOONGSON1ABC:
-#if defined(CONFIG_LOONGSON1_LS1B)
+#if defined(CONFIG_LOONGSON1_LS1A)
+ return "LOONGSON LS1A";
+#elif defined(CONFIG_LOONGSON1_LS1B)
return "LOONGSON LS1B";
#elif defined(CONFIG_LOONGSON1_LS1C)
return "LOONGSON LS1C";
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index e7f798d..44c4088 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1366,6 +1366,16 @@ static void probe_pcache(void)
c->options |= MIPS_CPU_PREFETCH;
break;
+ case CPU_LOONGSON1:
+ if (read_c0_config7() & MIPS_CONF7_AR) {
+ /*
+ * effectively physically indexed dcache,
+ * thus no virtual aliases.
+ */
+ c->dcache.flags |= MIPS_CACHE_PINDEX;
+ break;
+ }
+
default:
if (!(config & MIPS_CONF_M))
panic("Don't know how to probe P-caches on this cpu.");
--
2.9.3
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v6 4/8] MIPS: Loongson: Add Loongson-1A Kconfig options
2017-03-30 2:44 [PATCH v6 0/8] MIPS: Loongson: Add the Loongson-1A processor support Binbin Zhou
` (2 preceding siblings ...)
2017-03-30 2:44 ` [PATCH v6 3/8] MIPS: Loongson: Add basic Loongson-1A CPU support Binbin Zhou
@ 2017-03-30 2:44 ` Binbin Zhou
2017-03-30 2:44 ` [PATCH v6 5/8] MIPS: Loongson: Add platform devices for Loongson-1A Binbin Zhou
` (3 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Binbin Zhou @ 2017-03-30 2:44 UTC (permalink / raw)
To: Ralf Baechle, James Hogan
Cc: John Crispin, Steven J . Hill, Aurelien Jarno, Fuxin Zhang,
Zhangjin Wu, Kelvin Cheung, Yang Ling, 谢致邦,
linux-mips, Binbin Zhou, HuaCai Chen
Added Kconfig options include: Loongson-1A CPU and machine definition,
CPU cache features, 32-bit kernel and early printk support.
Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: HuaCai Chen <chenhc@lemote.com>
---
arch/mips/Kconfig | 12 ++++++++++++
arch/mips/loongson32/Kconfig | 20 ++++++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b969522..b4f59c5 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1420,6 +1420,15 @@ config CPU_LOONGSON2F
have a similar programming interface with FPGA northbridge used in
Loongson2E.
+config CPU_LOONGSON1A
+ bool "Loongson 1A"
+ depends on SYS_HAS_CPU_LOONGSON1A
+ select CPU_LOONGSON1
+ select LEDS_GPIO_REGISTER
+ help
+ The Loongson 1A is a 32-bit SoC, which implements the MIPS32
+ release 2 instruction set.
+
config CPU_LOONGSON1B
bool "Loongson 1B"
depends on SYS_HAS_CPU_LOONGSON1B
@@ -1884,6 +1893,9 @@ config SYS_HAS_CPU_LOONGSON2F
select CPU_SUPPORTS_ADDRWINCFG if 64BIT
select CPU_SUPPORTS_UNCACHED_ACCELERATED
+config SYS_HAS_CPU_LOONGSON1A
+ bool
+
config SYS_HAS_CPU_LOONGSON1B
bool
diff --git a/arch/mips/loongson32/Kconfig b/arch/mips/loongson32/Kconfig
index 3c0c2f2..6e0f6ec 100644
--- a/arch/mips/loongson32/Kconfig
+++ b/arch/mips/loongson32/Kconfig
@@ -1,8 +1,28 @@
if MACH_LOONGSON32
+config ZONE_DMA
+ prompt "Zone DMA"
+ bool
+
choice
prompt "Machine Type"
+config LOONGSON1_LS1A
+ bool "Loongson LS1A board"
+ select CEVT_R4K if !MIPS_EXTERNAL_TIMER
+ select CSRC_R4K if !MIPS_EXTERNAL_TIMER
+ select SYS_HAS_CPU_LOONGSON1A
+ select DMA_NONCOHERENT
+ select BOOT_ELF32
+ select IRQ_MIPS_CPU
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ select SYS_SUPPORTS_HIGHMEM
+ select SYS_SUPPORTS_MIPS16
+ select SYS_HAS_EARLY_PRINTK
+ select USE_GENERIC_EARLY_PRINTK_8250
+ select COMMON_CLK
+
config LOONGSON1_LS1B
bool "Loongson LS1B board"
select CEVT_R4K if !MIPS_EXTERNAL_TIMER
--
2.9.3
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v6 5/8] MIPS: Loongson: Add platform devices for Loongson-1A
2017-03-30 2:44 [PATCH v6 0/8] MIPS: Loongson: Add the Loongson-1A processor support Binbin Zhou
` (3 preceding siblings ...)
2017-03-30 2:44 ` [PATCH v6 4/8] MIPS: Loongson: Add Loongson-1A Kconfig options Binbin Zhou
@ 2017-03-30 2:44 ` Binbin Zhou
2017-03-30 2:44 ` [PATCH v6 6/8] MIPS: Loongson: Add Loongson-1A board support Binbin Zhou
` (2 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Binbin Zhou @ 2017-03-30 2:44 UTC (permalink / raw)
To: Ralf Baechle, James Hogan
Cc: John Crispin, Steven J . Hill, Aurelien Jarno, Fuxin Zhang,
Zhangjin Wu, Kelvin Cheung, Yang Ling, 谢致邦,
linux-mips, Binbin Zhou, HuaCai Chen
Added basic platform devices for Loongson-1A, including serial port,
ethernet, AHCI, USB and so on.
As we known, Most of them are shared with Loongson-1B/1C,
like serial port, ethernet and so on.
But something like AHCI is only supported by Loonson-1A.
Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: HuaCai Chen <chenhc@lemote.com>
---
arch/mips/include/asm/mach-loongson32/irq.h | 16 ++++--
arch/mips/include/asm/mach-loongson32/loongson1.h | 2 +-
arch/mips/include/asm/mach-loongson32/platform.h | 2 +
arch/mips/include/asm/mach-loongson32/regs-mux.h | 36 +++++++++++-
arch/mips/loongson32/common/irq.c | 2 +-
arch/mips/loongson32/common/platform.c | 67 +++++++++++++++++++++--
6 files changed, 111 insertions(+), 14 deletions(-)
diff --git a/arch/mips/include/asm/mach-loongson32/irq.h b/arch/mips/include/asm/mach-loongson32/irq.h
index 8c01b30..e790957 100644
--- a/arch/mips/include/asm/mach-loongson32/irq.h
+++ b/arch/mips/include/asm/mach-loongson32/irq.h
@@ -36,7 +36,7 @@
#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x))
#define LS1X_UART0_IRQ LS1X_IRQ(0, 2)
-#if defined(CONFIG_LOONGSON1_LS1B)
+#if defined(CONFIG_LOONGSON1_LS1A) || defined(CONFIG_LOONGSON1_LS1B)
#define LS1X_UART1_IRQ LS1X_IRQ(0, 3)
#define LS1X_UART2_IRQ LS1X_IRQ(0, 4)
#define LS1X_UART3_IRQ LS1X_IRQ(0, 5)
@@ -52,7 +52,9 @@
#define LS1X_DMA0_IRQ LS1X_IRQ(0, 13)
#define LS1X_DMA1_IRQ LS1X_IRQ(0, 14)
#define LS1X_DMA2_IRQ LS1X_IRQ(0, 15)
-#if defined(CONFIG_LOONGSON1_LS1C)
+#if defined(CONFIG_LOONGSON1_LS1A)
+#define LS1X_LPC_IRQ LS1X_IRQ(0, 16)
+#elif defined(CONFIG_LOONGSON1_LS1C)
#define LS1X_NAND_IRQ LS1X_IRQ(0, 16)
#endif
#define LS1X_PWM0_IRQ LS1X_IRQ(0, 17)
@@ -62,7 +64,7 @@
#define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21)
#define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22)
#define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23)
-#if defined(CONFIG_LOONGSON1_LS1B)
+#if defined(CONFIG_LOONGSON1_LS1A) || defined(CONFIG_LOONGSON1_LS1B)
#define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24)
#define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25)
#define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26)
@@ -78,7 +80,11 @@
#define LS1X_EHCI_IRQ LS1X_IRQ(1, 0)
#define LS1X_OHCI_IRQ LS1X_IRQ(1, 1)
-#if defined(CONFIG_LOONGSON1_LS1B)
+#if defined(CONFIG_LOONGSON1_LS1A)
+#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2)
+#define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3)
+#define LS1X_SATA_IRQ LS1X_IRQ(1, 4)
+#elif defined(CONFIG_LOONGSON1_LS1B)
#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2)
#define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3)
#elif defined(CONFIG_LOONGSON1_LS1C)
@@ -100,7 +106,7 @@
#if defined(CONFIG_LOONGSON1_LS1B)
#define INTN 4
-#elif defined(CONFIG_LOONGSON1_LS1C)
+#elif defined(CONFIG_LOONGSON1_LS1A) || defined(CONFIG_LOONGSON1_LS1C)
#define INTN 5
#endif
diff --git a/arch/mips/include/asm/mach-loongson32/loongson1.h b/arch/mips/include/asm/mach-loongson32/loongson1.h
index 8cfd4ba..029b3b7 100644
--- a/arch/mips/include/asm/mach-loongson32/loongson1.h
+++ b/arch/mips/include/asm/mach-loongson32/loongson1.h
@@ -12,7 +12,7 @@
#ifndef __ASM_MACH_LOONGSON32_LOONGSON1_H
#define __ASM_MACH_LOONGSON32_LOONGSON1_H
-#if defined(CONFIG_LOONGSON1_LS1B)
+#if defined(CONFIG_LOONGSON1_LS1A) || defined(CONFIG_LOONGSON1_LS1B)
#define DEFAULT_MEMSIZE 64 /* If no memsize provided */
#elif defined(CONFIG_LOONGSON1_LS1C)
#define DEFAULT_MEMSIZE 32
diff --git a/arch/mips/include/asm/mach-loongson32/platform.h b/arch/mips/include/asm/mach-loongson32/platform.h
index 8f8fa43..f28f814 100644
--- a/arch/mips/include/asm/mach-loongson32/platform.h
+++ b/arch/mips/include/asm/mach-loongson32/platform.h
@@ -26,6 +26,8 @@ extern struct platform_device ls1x_gpio1_pdev;
extern struct platform_device ls1x_nand_pdev;
extern struct platform_device ls1x_rtc_pdev;
extern struct platform_device ls1x_wdt_pdev;
+extern struct platform_device ls1x_ahci_pdev;
+extern struct platform_device ls1x_ohci_pdev;
void __init ls1x_clk_init(void);
void __init ls1x_dma_set_platdata(struct plat_ls1x_dma *pdata);
diff --git a/arch/mips/include/asm/mach-loongson32/regs-mux.h b/arch/mips/include/asm/mach-loongson32/regs-mux.h
index 4a0bdeb..2c22603 100644
--- a/arch/mips/include/asm/mach-loongson32/regs-mux.h
+++ b/arch/mips/include/asm/mach-loongson32/regs-mux.h
@@ -18,7 +18,41 @@
#define LS1X_MUX_CTRL0 LS1X_MUX_REG(0x0)
#define LS1X_MUX_CTRL1 LS1X_MUX_REG(0x4)
-#if defined(CONFIG_LOONGSON1_LS1B)
+#if defined(CONFIG_LOONGSON1_LS1A)
+/* GPIO CTRL0 Register Bits */
+#define NAND3_USE_CAN1 BIT(31)
+#define NAND2_USE_MS BIT(30)
+#define NAND1_USE_PWM01 BIT(29)
+#define NAND3_D45_USE_PWM23 BIT(28)
+#define NAND3_D45_USE_LPC BIT(27)
+#define NAND3_D03_USE_SPI1 BIT(26)
+#define NAND3_D03_USE_LPC BIT(25)
+#define GMAC1_SHUT BIT(24)
+#define GMAC0_SHUT BIT(23)
+#define SATA_SHUT BIT(22)
+#define USB_SHUT BIT(21)
+#define GPU_SHUT BIT(20)
+#define DDR2_SHUT BIT(19)
+#define VGA_USE_PCI BIT(18)
+#define I2C3_USE_CAN0 BIT(17)
+#define I2C2_USE_CAN1 BIT(16)
+#define SPI0_USE_CAN0_TX BIT(15)
+#define SPI0_USE_CAN0_RX BIT(14)
+#define SPI1_USE_CAN1_TX BIT(13)
+#define SPI1_USE_CAN1_RX BIT(12)
+#define GMAC1_USE_TXCLK BIT(11)
+#define GMAC0_USE_TXCLK BIT(10)
+#define GMAC1_USE_PWM23 BIT(9)
+#define GMAC0_USE_PWM01 BIT(8)
+#define GMAC1_USE_UART1 BIT(7)
+#define GMAC1_USE_UART0 BIT(6)
+#define GMAC1_USE_SPI1 BIT(5)
+#define GMAC1_USE_NAND BIT(4)
+#define PCI_REQ2_USE_GMAC1 BIT(2)
+#define DISABLE_DDR2_CONFSPACE BIT(1)
+#define DDE32TO16EN BIT(0)
+
+#elif defined(CONFIG_LOONGSON1_LS1B)
/* MUX CTRL0 Register Bits */
#define UART0_USE_PWM23 BIT(28)
#define UART0_USE_PWM01 BIT(27)
diff --git a/arch/mips/loongson32/common/irq.c b/arch/mips/loongson32/common/irq.c
index 635a4ab..b414eca 100644
--- a/arch/mips/loongson32/common/irq.c
+++ b/arch/mips/loongson32/common/irq.c
@@ -184,7 +184,7 @@ static void __init ls1x_irq_init(int base)
setup_irq(INT1_IRQ, &cascade_irqaction);
setup_irq(INT2_IRQ, &cascade_irqaction);
setup_irq(INT3_IRQ, &cascade_irqaction);
-#if defined(CONFIG_LOONGSON1_LS1C)
+#if defined(CONFIG_LOONGSON1_LS1A) || defined(CONFIG_LOONGSON1_LS1C)
setup_irq(INT4_IRQ, &cascade_irqaction);
#endif
}
diff --git a/arch/mips/loongson32/common/platform.c b/arch/mips/loongson32/common/platform.c
index f71392f..6b83fcf 100644
--- a/arch/mips/loongson32/common/platform.c
+++ b/arch/mips/loongson32/common/platform.c
@@ -16,6 +16,7 @@
#include <linux/serial_8250.h>
#include <linux/stmmac.h>
#include <linux/usb/ehci_pdriver.h>
+#include <linux/usb/ohci_pdriver.h>
#include <platform.h>
#include <loongson1.h>
@@ -133,7 +134,7 @@ int ls1x_eth_mux_init(struct platform_device *pdev, void *priv)
val = __raw_readl(LS1X_MUX_CTRL1);
-#if defined(CONFIG_LOONGSON1_LS1B)
+#if defined(CONFIG_LOONGSON1_LS1A) || defined(CONFIG_LOONGSON1_LS1B)
plat_dat = dev_get_platdata(&pdev->dev);
if (plat_dat->bus_id) {
__raw_writel(__raw_readl(LS1X_MUX_CTRL0) | GMAC1_USE_UART1 |
@@ -185,7 +186,7 @@ int ls1x_eth_mux_init(struct platform_device *pdev, void *priv)
static struct plat_stmmacenet_data ls1x_eth0_pdata = {
.bus_id = 0,
.phy_addr = -1,
-#if defined(CONFIG_LOONGSON1_LS1B)
+#if defined(CONFIG_LOONGSON1_LS1A) || defined(CONFIG_LOONGSON1_LS1B)
.interface = PHY_INTERFACE_MODE_MII,
#elif defined(CONFIG_LOONGSON1_LS1C)
.interface = PHY_INTERFACE_MODE_RMII,
@@ -220,7 +221,7 @@ struct platform_device ls1x_eth0_pdev = {
},
};
-#ifdef CONFIG_LOONGSON1_LS1B
+#if defined(CONFIG_LOONGSON1_LS1A) || defined(CONFIG_LOONGSON1_LS1B)
static struct plat_stmmacenet_data ls1x_eth1_pdata = {
.bus_id = 1,
.phy_addr = -1,
@@ -254,7 +255,7 @@ struct platform_device ls1x_eth1_pdev = {
.platform_data = &ls1x_eth1_pdata,
},
};
-#endif /* CONFIG_LOONGSON1_LS1B */
+#endif /* CONFIG_LOONGSON1_LS1A || CONFIG_LOONGSON1_LS1B */
/* GPIO */
static struct resource ls1x_gpio0_resources[] = {
@@ -315,7 +316,7 @@ void __init ls1x_nand_set_platdata(struct plat_ls1x_nand *pdata)
}
/* USB EHCI */
-static u64 ls1x_ehci_dmamask = DMA_BIT_MASK(32);
+static u64 ls1x_platform_dmamask = DMA_BIT_MASK(32);
static struct resource ls1x_ehci_resources[] = {
[0] = {
@@ -338,11 +339,65 @@ struct platform_device ls1x_ehci_pdev = {
.num_resources = ARRAY_SIZE(ls1x_ehci_resources),
.resource = ls1x_ehci_resources,
.dev = {
- .dma_mask = &ls1x_ehci_dmamask,
+ .dma_mask = &ls1x_platform_dmamask,
.platform_data = &ls1x_ehci_pdata,
},
};
+/* USB OHCI */
+static struct resource ls1x_ohci_resources[] = {
+ [0] = {
+ .start = LS1X_OHCI_BASE,
+ .end = LS1X_OHCI_BASE + SZ_32K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = LS1X_OHCI_IRQ,
+ .end = LS1X_OHCI_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct usb_ohci_pdata ls1x_ohci_data = {
+};
+
+struct platform_device ls1x_ohci_pdev = {
+ .name = "ohci-platform",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(ls1x_ohci_resources),
+ .resource = ls1x_ohci_resources,
+ .dev = {
+ .dma_mask = &ls1x_platform_dmamask,
+ .platform_data = &ls1x_ohci_data,
+ },
+};
+
+#ifdef CONFIG_LOONGSON1_LS1A
+/* AHCI */
+static struct resource ls1x_ahci_resources[] = {
+ [0] = {
+ .start = LS1X_AHCI_BASE,
+ .end = LS1X_AHCI_BASE + SZ_64K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = LS1X_SATA_IRQ,
+ .end = LS1X_SATA_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device ls1x_ahci_pdev = {
+ .name = "ahci",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(ls1x_ahci_resources),
+ .resource = ls1x_ahci_resources,
+ .dev = {
+ .dma_mask = &ls1x_platform_dmamask,
+ },
+};
+#endif
+
/* Real Time Clock */
void __init ls1x_rtc_set_extclk(struct platform_device *pdev)
{
--
2.9.3
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v6 6/8] MIPS: Loongson: Add Loongson-1A board support
2017-03-30 2:44 [PATCH v6 0/8] MIPS: Loongson: Add the Loongson-1A processor support Binbin Zhou
` (4 preceding siblings ...)
2017-03-30 2:44 ` [PATCH v6 5/8] MIPS: Loongson: Add platform devices for Loongson-1A Binbin Zhou
@ 2017-03-30 2:44 ` Binbin Zhou
2017-03-30 2:44 ` [PATCH v6 7/8] clk: Loongson: Add Loongson-1A clock support Binbin Zhou
2017-03-30 2:44 ` [PATCH v6 8/8] MIPS: Loongson: Add Loongson-1A default config file Binbin Zhou
7 siblings, 0 replies; 11+ messages in thread
From: Binbin Zhou @ 2017-03-30 2:44 UTC (permalink / raw)
To: Ralf Baechle, James Hogan
Cc: John Crispin, Steven J . Hill, Aurelien Jarno, Fuxin Zhang,
Zhangjin Wu, Kelvin Cheung, Yang Ling, 谢致邦,
linux-mips, Binbin Zhou, HuaCai Chen
Register basic devices for Loongson-1A, and setup clk for UART.
Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: HuaCai Chen <chenhc@lemote.com>
---
arch/mips/loongson32/Makefile | 6 ++++++
arch/mips/loongson32/ls1a/Makefile | 5 +++++
arch/mips/loongson32/ls1a/board.c | 31 +++++++++++++++++++++++++++++++
3 files changed, 42 insertions(+)
create mode 100644 arch/mips/loongson32/ls1a/Makefile
create mode 100644 arch/mips/loongson32/ls1a/board.c
diff --git a/arch/mips/loongson32/Makefile b/arch/mips/loongson32/Makefile
index 1ab2c5b..cd1f597 100644
--- a/arch/mips/loongson32/Makefile
+++ b/arch/mips/loongson32/Makefile
@@ -5,6 +5,12 @@
obj-$(CONFIG_MACH_LOONGSON32) += common/
#
+# Loongson LS1A board
+#
+
+obj-$(CONFIG_LOONGSON1_LS1A) += ls1a/
+
+#
# Loongson LS1B board
#
diff --git a/arch/mips/loongson32/ls1a/Makefile b/arch/mips/loongson32/ls1a/Makefile
new file mode 100644
index 0000000..dc23a9a
--- /dev/null
+++ b/arch/mips/loongson32/ls1a/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for loongson1A based machines.
+#
+
+obj-y += board.o
diff --git a/arch/mips/loongson32/ls1a/board.c b/arch/mips/loongson32/ls1a/board.c
new file mode 100644
index 0000000..7993f6c
--- /dev/null
+++ b/arch/mips/loongson32/ls1a/board.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2016 Binbin Zhou <zhoubb@lemote.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <platform.h>
+
+static struct platform_device *ls1a_platform_devices[] __initdata = {
+ &ls1x_uart_pdev,
+ &ls1x_eth0_pdev,
+ &ls1x_eth1_pdev,
+ &ls1x_rtc_pdev,
+ &ls1x_wdt_pdev,
+ &ls1x_ahci_pdev,
+ &ls1x_ohci_pdev,
+};
+
+static int __init ls1a_platform_init(void)
+{
+ ls1x_serial_set_uartclk(&ls1x_uart_pdev);
+ ls1x_rtc_set_extclk(&ls1x_rtc_pdev);
+
+ return platform_add_devices(ls1a_platform_devices,
+ ARRAY_SIZE(ls1a_platform_devices));
+}
+
+arch_initcall(ls1a_platform_init);
--
2.9.3
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v6 7/8] clk: Loongson: Add Loongson-1A clock support
2017-03-30 2:44 [PATCH v6 0/8] MIPS: Loongson: Add the Loongson-1A processor support Binbin Zhou
` (5 preceding siblings ...)
2017-03-30 2:44 ` [PATCH v6 6/8] MIPS: Loongson: Add Loongson-1A board support Binbin Zhou
@ 2017-03-30 2:44 ` Binbin Zhou
2017-03-30 2:44 ` [PATCH v6 8/8] MIPS: Loongson: Add Loongson-1A default config file Binbin Zhou
7 siblings, 0 replies; 11+ messages in thread
From: Binbin Zhou @ 2017-03-30 2:44 UTC (permalink / raw)
To: Ralf Baechle, James Hogan
Cc: John Crispin, Steven J . Hill, Aurelien Jarno, Fuxin Zhang,
Zhangjin Wu, Kelvin Cheung, Yang Ling, 谢致邦,
linux-mips, Binbin Zhou, HuaCai Chen, Michael Turquette,
Stephen Boyd, linux-clk
This patch adds clock support to Loongson-1A SoC.
Unfortunately, The Loongson-1A's PLL register is written only,
so we just set it with a fixed value.
Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: HuaCai Chen <chenhc@lemote.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
---
arch/mips/include/asm/mach-loongson32/regs-clk.h | 30 +++++++++-
drivers/clk/loongson1/Makefile | 1 +
drivers/clk/loongson1/clk-loongson1a.c | 75 ++++++++++++++++++++++++
3 files changed, 105 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/loongson1/clk-loongson1a.c
diff --git a/arch/mips/include/asm/mach-loongson32/regs-clk.h b/arch/mips/include/asm/mach-loongson32/regs-clk.h
index e5e8f11..d8278a4 100644
--- a/arch/mips/include/asm/mach-loongson32/regs-clk.h
+++ b/arch/mips/include/asm/mach-loongson32/regs-clk.h
@@ -18,7 +18,35 @@
#define LS1X_CLK_PLL_FREQ LS1X_CLK_REG(0x0)
#define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4)
-#if defined(CONFIG_LOONGSON1_LS1B)
+#if defined(CONFIG_LOONGSON1_LS1A)
+/* write only */
+#define CORE_PLL_CFG 0x1fe78030
+#define CPU_MUL GENMASK(2, 0)
+#define CPU_CFG_EN BIT(3)
+#define DDR_MUL GENMASK(6, 4)
+#define DDR_CFG_EN BIT(7)
+#define CPU_CFG_W_EN BIT(11)
+#define DDR_CFG_W_EN BIT(15)
+
+#define VGA_PLL_CFG 0x1fd00410
+#define VGA_M GENMASK(7, 0)
+#define VGA_N GENMASK(11, 8)
+#define VGA_OD GENMASK(13, 12)
+#define VGA_FRAC GENMASK(31, 14)
+
+#define LCD_PLL_CFG 0x1fd00410
+#define LCD_M GENMASK(7, 0)
+#define LCD_N GENMASK(11, 8)
+#define LCD_OD GENMASK(13, 12)
+#define LCD_FRAC GENMASK(31, 14)
+
+#define GPU_PLL_CFG 0x1fd00414
+#define GPU_M GENMASK(7, 0)
+#define GPU_N GENMASK(11, 8)
+#define GPU_OD GENMASK(13, 12)
+#define GPU_FRAC GENMASK(31, 14)
+
+#elif defined(CONFIG_LOONGSON1_LS1B)
/* Clock PLL Divisor Register Bits */
#define DIV_DC_EN BIT(31)
#define DIV_DC_RST BIT(30)
diff --git a/drivers/clk/loongson1/Makefile b/drivers/clk/loongson1/Makefile
index b7f6a16..da7b2dd 100644
--- a/drivers/clk/loongson1/Makefile
+++ b/drivers/clk/loongson1/Makefile
@@ -1,3 +1,4 @@
obj-y += clk.o
+obj-$(CONFIG_LOONGSON1_LS1A) += clk-loongson1a.o
obj-$(CONFIG_LOONGSON1_LS1B) += clk-loongson1b.o
obj-$(CONFIG_LOONGSON1_LS1C) += clk-loongson1c.o
diff --git a/drivers/clk/loongson1/clk-loongson1a.c b/drivers/clk/loongson1/clk-loongson1a.c
new file mode 100644
index 0000000..263a82c
--- /dev/null
+++ b/drivers/clk/loongson1/clk-loongson1a.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2012-2016 Binbin Zhou <zhoubb@lemote.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+#include <loongson1.h>
+#include "clk.h"
+
+#define OSC (33 * 1000000)
+#define DIV_APB 2
+
+static DEFINE_SPINLOCK(_lock);
+
+static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ /* Workaround, loongson-1A pll register is written only */
+ return OSC * 8;
+}
+
+static const struct clk_ops ls1x_pll_clk_ops = {
+ .recalc_rate = ls1x_pll_recalc_rate,
+};
+
+void __init ls1x_clk_init(void)
+{
+ struct clk_hw *hw;
+
+ hw = clk_hw_register_fixed_rate(NULL, "osc_clk", NULL, 0, OSC);
+ clk_hw_register_clkdev(hw, "osc_clk", NULL);
+
+ /* clock from 33 MHz OSC clk */
+ hw = clk_hw_register_pll(NULL, "pll_clk", "osc_clk",
+ &ls1x_pll_clk_ops, 0);
+ clk_hw_register_clkdev(hw, "pll_clk", NULL);
+
+ /* cpu clk */
+ hw = clk_hw_register_fixed_factor(NULL, "cpu_clk", "pll_clk",
+ 0, 1, 1);
+ clk_hw_register_clkdev(hw, "cpu_clk", NULL);
+
+ /* dc clk */
+ hw = clk_hw_register_fixed_factor(NULL, "ddr_clk", "pll_clk",
+ 0, 1, 1);
+ clk_hw_register_clkdev(hw, "ddr_clk", NULL);
+
+ /* ahb clk */
+ hw = clk_hw_register_fixed_factor(NULL, "ahb_clk", "pll_clk",
+ 0, 1, 2);
+ clk_hw_register_clkdev(hw, "ahb_clk", NULL);
+ clk_hw_register_clkdev(hw, "ls1x-dma", NULL);
+ clk_hw_register_clkdev(hw, "stmmaceth", NULL);
+
+ /* clock derived from AHB clk */
+ /* APB clk is always half of the AHB clk */
+ hw = clk_hw_register_fixed_factor(NULL, "apb_clk", "ahb_clk",
+ 0, 1, DIV_APB);
+ clk_hw_register_clkdev(hw, "apb_clk", NULL);
+ clk_hw_register_clkdev(hw, "ls1x-ac97", NULL);
+ clk_hw_register_clkdev(hw, "ls1x-i2c", NULL);
+ clk_hw_register_clkdev(hw, "ls1x-nand", NULL);
+ clk_hw_register_clkdev(hw, "ls1x-pwmtimer", NULL);
+ clk_hw_register_clkdev(hw, "ls1x-spi", NULL);
+ clk_hw_register_clkdev(hw, "ls1x-wdt", NULL);
+ clk_hw_register_clkdev(hw, "serial8250", NULL);
+}
--
2.9.3
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v6 8/8] MIPS: Loongson: Add Loongson-1A default config file
2017-03-30 2:44 [PATCH v6 0/8] MIPS: Loongson: Add the Loongson-1A processor support Binbin Zhou
` (6 preceding siblings ...)
2017-03-30 2:44 ` [PATCH v6 7/8] clk: Loongson: Add Loongson-1A clock support Binbin Zhou
@ 2017-03-30 2:44 ` Binbin Zhou
7 siblings, 0 replies; 11+ messages in thread
From: Binbin Zhou @ 2017-03-30 2:44 UTC (permalink / raw)
To: Ralf Baechle, James Hogan
Cc: John Crispin, Steven J . Hill, Aurelien Jarno, Fuxin Zhang,
Zhangjin Wu, Kelvin Cheung, Yang Ling, 谢致邦,
linux-mips, Binbin Zhou, HuaCai Chen
Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: HuaCai Chen <chenhc@lemote.com>
---
arch/mips/configs/loongson1a_defconfig | 130 +++++++++++++++++++++++++++++++++
1 file changed, 130 insertions(+)
create mode 100644 arch/mips/configs/loongson1a_defconfig
diff --git a/arch/mips/configs/loongson1a_defconfig b/arch/mips/configs/loongson1a_defconfig
new file mode 100644
index 0000000..1a8545e
--- /dev/null
+++ b/arch/mips/configs/loongson1a_defconfig
@@ -0,0 +1,130 @@
+CONFIG_MACH_LOONGSON32=y
+CONFIG_ZONE_DMA=y
+CONFIG_PAGE_SIZE_16KB=y
+CONFIG_HIGHMEM=y
+CONFIG_HZ_1000=y
+CONFIG_PREEMPT_VOLUNTARY=y
+# CONFIG_SECCOMP is not set
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_CGROUPS=y
+CONFIG_BLK_CGROUP=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_EXPERT=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+# CONFIG_BRIDGE_IGMP_SNOOPING is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_NFTL=y
+CONFIG_NFTL_RW=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_ATA=y
+# CONFIG_SATA_PMP is not set
+CONFIG_SATA_AHCI_PLATFORM=y
+# CONFIG_ATA_SFF is not set
+CONFIG_NETDEVICES=y
+CONFIG_NETCONSOLE=y
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_REALTEK_PHY=y
+# CONFIG_USB_NET_DRIVERS is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_LEGACY_PTY_COUNT=8
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_MON=y
+CONFIG_USB_XHCI_HCD=m
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=m
+CONFIG_USB_GADGET=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PCF8563=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_PRINTK_TIME=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_FTRACE is not set
+CONFIG_XZ_DEC=y
--
2.9.3
^ permalink raw reply related [flat|nested] 11+ messages in thread