From: Paul Burton <paul.burton@imgtec.com> To: Thomas Gleixner <tglx@linutronix.de>, Ralf Baechle <ralf@linux-mips.org> Cc: <dianders@chromium.org>, James Hogan <james.hogan@imgtec.com>, Brian Norris <briannorris@chromium.org>, Jason Cooper <jason@lakedaemon.net>, <jeffy.chen@rock-chips.com>, Marc Zyngier <marc.zyngier@arm.com>, <linux-kernel@vger.kernel.org>, <linux-mips@linux-mips.org>, <tfiga@chromium.org>, Paul Burton <paul.burton@imgtec.com> Subject: [RFC PATCH v1 5/9] MIPS: Remove perf_irq Date: Thu, 7 Sep 2017 16:25:38 -0700 [thread overview] Message-ID: <20170907232542.20589-6-paul.burton@imgtec.com> (raw) In-Reply-To: <20170907232542.20589-1-paul.burton@imgtec.com> Remove the perf_irq function pointer which we no longer use. The cevt-r4k clock event driver no longer needs to call it, which simplifies c0_compare_interrupt(), and we drop its definition & declarations. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org --- arch/mips/include/asm/time.h | 1 - arch/mips/kernel/cevt-r4k.c | 48 +++++++++----------------------------------- arch/mips/kernel/time.c | 9 --------- arch/mips/oprofile/op_impl.h | 2 -- 4 files changed, 10 insertions(+), 50 deletions(-) diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h index 17d4cd20f18c..7a21792826a6 100644 --- a/arch/mips/include/asm/time.h +++ b/arch/mips/include/asm/time.h @@ -45,7 +45,6 @@ extern unsigned int mips_hpt_frequency; * The performance counter IRQ on MIPS is a close relative to the timer IRQ * so it lives here. */ -extern int (*perf_irq)(void); extern int __weak get_c0_perfcount_int(void); /* diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index dd6a18bc10ab..893aa32759d9 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c @@ -108,54 +108,26 @@ static unsigned int calculate_min_delta(void) DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device); int cp0_timer_irq_installed; -/* - * Possibly handle a performance counter interrupt. - * Return true if the timer interrupt should not be checked - */ -static inline int handle_perf_irq(int r2) -{ - /* - * The performance counter overflow interrupt may be shared with the - * timer interrupt (cp0_perfcount_irq < 0). If it is and a - * performance counter has overflowed (perf_irq() == IRQ_HANDLED) - * and we can't reliably determine if a counter interrupt has also - * happened (!r2) then don't check for a timer interrupt. - */ - return (cp0_perfcount_irq < 0) && - perf_irq() == IRQ_HANDLED && - !r2; -} - irqreturn_t c0_compare_interrupt(int irq, void *dev_id) { - const int r2 = cpu_has_mips_r2_r6; struct clock_event_device *cd; int cpu = smp_processor_id(); /* - * Suckage alert: - * Before R2 of the architecture there was no way to see if a - * performance counter interrupt was pending, so we have to run - * the performance counter interrupt handler anyway. + * If we have the Cause.TI bit with which to decode whether this was in + * fact a timer interrupt, rather than another which shares the CPU + * pin, then check that & return if no timer interrupt is pending. */ - if (handle_perf_irq(r2)) - return IRQ_HANDLED; + if (cpu_has_mips_r2_r6 && !(read_c0_cause() & CAUSEF_TI)) + return IRQ_NONE; - /* - * The same applies to performance counter interrupts. But with the - * above we now know that the reason we got here must be a timer - * interrupt. Being the paranoiacs we are we check anyway. - */ - if (!r2 || (read_c0_cause() & CAUSEF_TI)) { - /* Clear Count/Compare Interrupt */ - write_c0_compare(read_c0_compare()); - cd = &per_cpu(mips_clockevent_device, cpu); - cd->event_handler(cd); + /* Clear Count/Compare Interrupt */ + write_c0_compare(read_c0_compare()); - return IRQ_HANDLED; - } + cd = &per_cpu(mips_clockevent_device, cpu); + cd->event_handler(cd); - return IRQ_NONE; + return IRQ_HANDLED; } struct irqaction c0_compare_irqaction = { diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index a6ebc8135112..1090d1c11afa 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -49,15 +49,6 @@ int update_persistent_clock(struct timespec now) return rtc_mips_set_mmss(now.tv_sec); } -static int null_perf_irq(void) -{ - return 0; -} - -int (*perf_irq)(void) = null_perf_irq; - -EXPORT_SYMBOL(perf_irq); - /* * time_init() - it does the following things. * diff --git a/arch/mips/oprofile/op_impl.h b/arch/mips/oprofile/op_impl.h index a4e758a39af4..9b0b295bdaf1 100644 --- a/arch/mips/oprofile/op_impl.h +++ b/arch/mips/oprofile/op_impl.h @@ -10,8 +10,6 @@ #ifndef OP_IMPL_H #define OP_IMPL_H 1 -extern int (*perf_irq)(void); - /* Per-counter configuration as set via oprofilefs. */ struct op_counter_config { unsigned long enabled; -- 2.14.1
WARNING: multiple messages have this Message-ID (diff)
From: Paul Burton <paul.burton@imgtec.com> To: Thomas Gleixner <tglx@linutronix.de>, Ralf Baechle <ralf@linux-mips.org> Cc: dianders@chromium.org, James Hogan <james.hogan@imgtec.com>, Brian Norris <briannorris@chromium.org>, Jason Cooper <jason@lakedaemon.net>, jeffy.chen@rock-chips.com, Marc Zyngier <marc.zyngier@arm.com>, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, tfiga@chromium.org, Paul Burton <paul.burton@imgtec.com> Subject: [RFC PATCH v1 5/9] MIPS: Remove perf_irq Date: Thu, 7 Sep 2017 16:25:38 -0700 [thread overview] Message-ID: <20170907232542.20589-6-paul.burton@imgtec.com> (raw) Message-ID: <20170907232538.KF1Beut_Ytv5LbVTN4_cavCOv2H3Sl9HGk8i_0yFTmU@z> (raw) In-Reply-To: <20170907232542.20589-1-paul.burton@imgtec.com> Remove the perf_irq function pointer which we no longer use. The cevt-r4k clock event driver no longer needs to call it, which simplifies c0_compare_interrupt(), and we drop its definition & declarations. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org --- arch/mips/include/asm/time.h | 1 - arch/mips/kernel/cevt-r4k.c | 48 +++++++++----------------------------------- arch/mips/kernel/time.c | 9 --------- arch/mips/oprofile/op_impl.h | 2 -- 4 files changed, 10 insertions(+), 50 deletions(-) diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h index 17d4cd20f18c..7a21792826a6 100644 --- a/arch/mips/include/asm/time.h +++ b/arch/mips/include/asm/time.h @@ -45,7 +45,6 @@ extern unsigned int mips_hpt_frequency; * The performance counter IRQ on MIPS is a close relative to the timer IRQ * so it lives here. */ -extern int (*perf_irq)(void); extern int __weak get_c0_perfcount_int(void); /* diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index dd6a18bc10ab..893aa32759d9 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c @@ -108,54 +108,26 @@ static unsigned int calculate_min_delta(void) DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device); int cp0_timer_irq_installed; -/* - * Possibly handle a performance counter interrupt. - * Return true if the timer interrupt should not be checked - */ -static inline int handle_perf_irq(int r2) -{ - /* - * The performance counter overflow interrupt may be shared with the - * timer interrupt (cp0_perfcount_irq < 0). If it is and a - * performance counter has overflowed (perf_irq() == IRQ_HANDLED) - * and we can't reliably determine if a counter interrupt has also - * happened (!r2) then don't check for a timer interrupt. - */ - return (cp0_perfcount_irq < 0) && - perf_irq() == IRQ_HANDLED && - !r2; -} - irqreturn_t c0_compare_interrupt(int irq, void *dev_id) { - const int r2 = cpu_has_mips_r2_r6; struct clock_event_device *cd; int cpu = smp_processor_id(); /* - * Suckage alert: - * Before R2 of the architecture there was no way to see if a - * performance counter interrupt was pending, so we have to run - * the performance counter interrupt handler anyway. + * If we have the Cause.TI bit with which to decode whether this was in + * fact a timer interrupt, rather than another which shares the CPU + * pin, then check that & return if no timer interrupt is pending. */ - if (handle_perf_irq(r2)) - return IRQ_HANDLED; + if (cpu_has_mips_r2_r6 && !(read_c0_cause() & CAUSEF_TI)) + return IRQ_NONE; - /* - * The same applies to performance counter interrupts. But with the - * above we now know that the reason we got here must be a timer - * interrupt. Being the paranoiacs we are we check anyway. - */ - if (!r2 || (read_c0_cause() & CAUSEF_TI)) { - /* Clear Count/Compare Interrupt */ - write_c0_compare(read_c0_compare()); - cd = &per_cpu(mips_clockevent_device, cpu); - cd->event_handler(cd); + /* Clear Count/Compare Interrupt */ + write_c0_compare(read_c0_compare()); - return IRQ_HANDLED; - } + cd = &per_cpu(mips_clockevent_device, cpu); + cd->event_handler(cd); - return IRQ_NONE; + return IRQ_HANDLED; } struct irqaction c0_compare_irqaction = { diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index a6ebc8135112..1090d1c11afa 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -49,15 +49,6 @@ int update_persistent_clock(struct timespec now) return rtc_mips_set_mmss(now.tv_sec); } -static int null_perf_irq(void) -{ - return 0; -} - -int (*perf_irq)(void) = null_perf_irq; - -EXPORT_SYMBOL(perf_irq); - /* * time_init() - it does the following things. * diff --git a/arch/mips/oprofile/op_impl.h b/arch/mips/oprofile/op_impl.h index a4e758a39af4..9b0b295bdaf1 100644 --- a/arch/mips/oprofile/op_impl.h +++ b/arch/mips/oprofile/op_impl.h @@ -10,8 +10,6 @@ #ifndef OP_IMPL_H #define OP_IMPL_H 1 -extern int (*perf_irq)(void); - /* Per-counter configuration as set via oprofilefs. */ struct op_counter_config { unsigned long enabled; -- 2.14.1
next prev parent reply other threads:[~2017-09-07 23:29 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top [not found] <1682867.tATABVWsV9@np-p-burton> 2017-09-07 23:25 ` [RFC PATCH v1 0/9] Support shared percpu interrupts; clean up MIPS hacks Paul Burton 2017-09-07 23:25 ` Paul Burton 2017-09-07 23:25 ` [RFC PATCH v1 1/9] genirq: Allow shared interrupt users to opt into IRQ_NOAUTOEN Paul Burton 2017-09-07 23:25 ` Paul Burton 2017-09-07 23:25 ` [RFC PATCH v1 2/9] genirq: Support shared per_cpu_devid interrupts Paul Burton 2017-09-07 23:25 ` Paul Burton 2017-09-25 21:06 ` Thomas Gleixner 2017-09-26 12:00 ` Thomas Gleixner 2017-10-19 14:08 ` Thomas Gleixner 2017-09-07 23:25 ` [RFC PATCH v1 3/9] genirq: Introduce irq_is_percpu_devid() Paul Burton 2017-09-07 23:25 ` Paul Burton 2017-09-07 23:25 ` [RFC PATCH v1 4/9] MIPS: Remove perf_irq interrupt sharing fallback Paul Burton 2017-09-07 23:25 ` Paul Burton 2017-09-07 23:25 ` Paul Burton [this message] 2017-09-07 23:25 ` [RFC PATCH v1 5/9] MIPS: Remove perf_irq Paul Burton 2017-09-07 23:25 ` [RFC PATCH v1 6/9] MIPS: perf: percpu_devid interrupt support Paul Burton 2017-09-07 23:25 ` Paul Burton 2017-10-19 14:12 ` Thomas Gleixner 2017-09-07 23:25 ` [RFC PATCH v1 7/9] MIPS: cevt-r4k: " Paul Burton 2017-09-07 23:25 ` Paul Burton 2017-09-07 23:25 ` [RFC PATCH v1 8/9] irqchip: mips-cpu: Set timer, FDC & perf interrupts percpu_devid Paul Burton 2017-09-07 23:25 ` Paul Burton 2017-09-07 23:25 ` [RFC PATCH v1 9/9] irqchip: mips-gic: Remove gic_all_vpes_local_irq_controller Paul Burton 2017-09-07 23:25 ` Paul Burton
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20170907232542.20589-6-paul.burton@imgtec.com \ --to=paul.burton@imgtec.com \ --cc=briannorris@chromium.org \ --cc=dianders@chromium.org \ --cc=james.hogan@imgtec.com \ --cc=jason@lakedaemon.net \ --cc=jeffy.chen@rock-chips.com \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-mips@linux-mips.org \ --cc=marc.zyngier@arm.com \ --cc=ralf@linux-mips.org \ --cc=tfiga@chromium.org \ --cc=tglx@linutronix.de \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).