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From: Paul Burton <paul.burton@mips.com>
To: "linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>
Cc: Serge Semin <fancer.lancer@gmail.com>,
	Paul Burton <pburton@wavecomp.com>
Subject: [PATCH 4/4] MIPS: Remove duplicate EBase configuration
Date: Tue, 30 Apr 2019 22:53:31 +0000
Message-ID: <20190430225216.7164-5-paul.burton@mips.com> (raw)
In-Reply-To: <20190430225216.7164-1-paul.burton@mips.com>

Clean up our configuration of the EBase register by making
configure_exception_vector() write to it unconditionally on systems
implementing MIPSr2 or higher, and removing the duplicate code in
per_cpu_trap_init(). The latter would have duplicated work on systems
with vectored interrupts, and didn't set BEV for safety like the
configure_exception_vector() version of the code does.

Signed-off-by: Paul Burton <paul.burton@mips.com>
---
 arch/mips/kernel/traps.c | 20 +++-----------------
 1 file changed, 3 insertions(+), 17 deletions(-)

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 2775190adbe7..c52766a5b85f 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2151,7 +2151,7 @@ static void configure_hwrena(void)
 
 static void configure_exception_vector(void)
 {
-	if (cpu_has_veic || cpu_has_vint) {
+	if (cpu_has_mips_r2_r6) {
 		unsigned long sr = set_c0_status(ST0_BEV);
 		/* If available, use WG to set top bits of EBASE */
 		if (cpu_has_ebase_wg) {
@@ -2163,6 +2163,8 @@ static void configure_exception_vector(void)
 		}
 		write_c0_ebase(ebase);
 		write_c0_status(sr);
+	}
+	if (cpu_has_veic || cpu_has_vint) {
 		/* Setting vector spacing enables EI/VI mode  */
 		change_c0_intctl(0x3e0, VECTORSPACING);
 	}
@@ -2193,22 +2195,6 @@ void per_cpu_trap_init(bool is_boot_cpu)
 	 *  o read IntCtl.IPFDC to determine the fast debug channel interrupt
 	 */
 	if (cpu_has_mips_r2_r6) {
-		/*
-		 * We shouldn't trust a secondary core has a sane EBASE register
-		 * so use the one calculated by the boot CPU.
-		 */
-		if (!is_boot_cpu) {
-			/* If available, use WG to set top bits of EBASE */
-			if (cpu_has_ebase_wg) {
-#ifdef CONFIG_64BIT
-				write_c0_ebase_64(ebase | MIPS_EBASE_WG);
-#else
-				write_c0_ebase(ebase | MIPS_EBASE_WG);
-#endif
-			}
-			write_c0_ebase(ebase);
-		}
-
 		cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
 		cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
 		cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
-- 
2.21.0


  parent reply index

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-30 22:53 [PATCH 0/4] MIPS: Exception vector improvements Paul Burton
2019-04-30 22:53 ` [PATCH 2/4] MIPS: Always allocate exception vector for MIPSr2+ Paul Burton
2019-04-30 22:53 ` [PATCH 1/4] MIPS: Use memblock_phys_alloc() for exception vector Paul Burton
2019-05-01 14:32   ` Philippe Mathieu-Daudé
2019-04-30 22:53 ` Paul Burton [this message]
2019-04-30 22:53 ` [PATCH 3/4] MIPS: Sync icache for whole " Paul Burton
2019-05-01 15:09   ` Philippe Mathieu-Daudé
2019-05-02 13:59 ` [PATCH 0/4] MIPS: Exception vector improvements Serge Semin
2019-05-02 18:35 ` Paul Burton

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