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From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: linux-mips@vger.kernel.org
Cc: tsbogend@alpha.franken.de, maz@kernel.org, chenhc@lemote.com,
	Jiaxun Yang <jiaxun.yang@flygoat.com>
Subject: [RFC PATCH 6/6] MIPS: ip22: Use mips_cpu_map_virq helper
Date: Thu, 26 Mar 2020 14:20:39 +0800
Message-ID: <20200326062039.387756-1-jiaxun.yang@flygoat.com> (raw)
In-Reply-To: <20200326061704.387483-1-jiaxun.yang@flygoat.com>

Remove the use of MIPS_CPU_IRQ_BASE and step forward
to purely irq domain based platform.

I'm not brave enough to touch legacy IRQ layout so just
keep it as is.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/include/asm/sgi/ip22.h | 30 +++++++++++++++---------------
 arch/mips/sgi-ip22/ip22-int.c    | 14 +++++++++-----
 2 files changed, 24 insertions(+), 20 deletions(-)

diff --git a/arch/mips/include/asm/sgi/ip22.h b/arch/mips/include/asm/sgi/ip22.h
index 87ec9eaa04e3..42dadb1d08b8 100644
--- a/arch/mips/include/asm/sgi/ip22.h
+++ b/arch/mips/include/asm/sgi/ip22.h
@@ -24,27 +24,27 @@
 #include <irq.h>
 #include <asm/sgi/ioc.h>
 
+/* 8 MIPS CPU IRQ Lines */
+#define SGI_SOFT_0_IRQ	0
+#define SGI_SOFT_1_IRQ	1
+#define SGI_LOCAL_0_IRQ 2
+#define SGI_LOCAL_1_IRQ 3
+#define SGI_8254_0_IRQ	4
+#define SGI_8254_1_IRQ	5
+#define SGI_BUSERR_IRQ	6
+#define SGI_TIMER_IRQ	7
+
 #define SGINT_EISA	0	/* 16 EISA irq levels (Indigo2) */
-#define SGINT_CPU	MIPS_CPU_IRQ_BASE	/* MIPS CPU define 8 interrupt sources */
-#define SGINT_LOCAL0	(SGINT_CPU+8)	/* 8 local0 irq levels */
-#define SGINT_LOCAL1	(SGINT_CPU+16)	/* 8 local1 irq levels */
-#define SGINT_LOCAL2	(SGINT_CPU+24)	/* 8 local2 vectored irq levels */
-#define SGINT_LOCAL3	(SGINT_CPU+32)	/* 8 local3 vectored irq levels */
-#define SGINT_END	(SGINT_CPU+40)	/* End of 'spaces' */
+#define SGINT_LOCAL0	(SGINT_EISA+24)	/* 8 local0 irq levels */
+#define SGINT_LOCAL1	(SGINT_LOCAL0+8)	/* 8 local1 irq levels */
+#define SGINT_LOCAL2	(SGINT_LOCAL1+8)	/* 8 local2 vectored irq levels */
+#define SGINT_LOCAL3	(SGINT_LOCAL0+8)	/* 8 local3 vectored irq levels */
+#define SGINT_END	(SGINT_LOCAL0+8)	/* End of 'spaces' */
 
 /*
  * Individual interrupt definitions for the Indy and Indigo2
  */
 
-#define SGI_SOFT_0_IRQ	SGINT_CPU + 0
-#define SGI_SOFT_1_IRQ	SGINT_CPU + 1
-#define SGI_LOCAL_0_IRQ SGINT_CPU + 2
-#define SGI_LOCAL_1_IRQ SGINT_CPU + 3
-#define SGI_8254_0_IRQ	SGINT_CPU + 4
-#define SGI_8254_1_IRQ	SGINT_CPU + 5
-#define SGI_BUSERR_IRQ	SGINT_CPU + 6
-#define SGI_TIMER_IRQ	SGINT_CPU + 7
-
 #define SGI_FIFO_IRQ	SGINT_LOCAL0 + 0	/* FIFO full */
 #define SGI_GIO_0_IRQ	SGI_FIFO_IRQ		/* GIO-0 */
 #define SGI_WD93_0_IRQ	SGINT_LOCAL0 + 1	/* 1st onboard WD93 */
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index 96798a4ab2de..b1fbd7c5df9d 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -151,7 +151,7 @@ extern void ip22_be_interrupt(int irq);
 
 static void __irq_entry indy_buserror_irq(void)
 {
-	int irq = SGI_BUSERR_IRQ;
+	int irq = mips_cpu_map_virq(SGI_BUSERR_IRQ);
 
 	irq_enter();
 	kstat_incr_irq_this_cpu(irq);
@@ -203,7 +203,8 @@ asmlinkage void plat_irq_dispatch(void)
 	 * First we check for r4k counter/timer IRQ.
 	 */
 	if (pending & CAUSEF_IP7)
-		do_IRQ(SGI_TIMER_IRQ);
+		do_IRQ(irq_linear_revmap(mips_cpu_irq_domain,
+					SGI_TIMER_IRQ));
 	else if (pending & CAUSEF_IP2)
 		indy_local0_irqdispatch();
 	else if (pending & CAUSEF_IP3)
@@ -293,13 +294,16 @@ void __init arch_init_irq(void)
 	}
 
 	/* vector handler. this register the IRQ as non-sharable */
-	if (request_irq(SGI_LOCAL_0_IRQ, no_action, IRQF_NO_THREAD,
+	if (request_irq(mips_cpu_map_virq(SGI_LOCAL_0_IRQ),
+			no_action, IRQF_NO_THREAD,
 			"local0 cascade", NULL))
 		pr_err("Failed to register local0 cascade interrupt\n");
-	if (request_irq(SGI_LOCAL_1_IRQ, no_action, IRQF_NO_THREAD,
+	if (request_irq(mips_cpu_map_virq(SGI_LOCAL_1_IRQ),
+			no_action, IRQF_NO_THREAD,
 			"local1 cascade", NULL))
 		pr_err("Failed to register local1 cascade interrupt\n");
-	if (request_irq(SGI_BUSERR_IRQ, no_action, IRQF_NO_THREAD,
+	if (request_irq(mips_cpu_map_virq(SGI_BUSERR_IRQ),
+			no_action, IRQF_NO_THREAD,
 			"Bus Error", NULL))
 		pr_err("Failed to register Bus Error interrupt\n");
 
-- 
2.26.0.rc2



  parent reply index

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-26  6:16 [RFC PATCH 0/6] MIPS: Handle CPU IRQ in domain's way Jiaxun Yang
2020-03-26  6:16 ` [RFC PATCH 1/6] MIPS: irq_cpu: Add a helper to map virq for CPU IRQ Jiaxun Yang
2020-03-26  6:16 ` [PATCH 1/2] MIPS: Kill MIPS_GIC_IRQ_BASE Jiaxun Yang
2020-03-26  6:16 ` [RFC PATCH 2/6] irqchip: mips-cpu: Allocate fwnode for non-DT platforms Jiaxun Yang
2020-03-26  6:17 ` [PATCH 2/2] MIPS: Kill RM7K & RM9K IRQ Code Jiaxun Yang
2020-03-26  6:17 ` [RFC PATCH 3/6] irqchip: mips-cpu: Convert to simple domain Jiaxun Yang
2020-03-26  6:17 ` [RFC PATCH 4/6] MIPS: kernel: Use mips_cpu_map_virq helper Jiaxun Yang
2020-03-26  6:17 ` [RFC PATCH 5/6] MIPS: loongson64: " Jiaxun Yang
2020-03-26  6:20 ` Jiaxun Yang [this message]
2020-03-26 15:38 ` [RFC PATCH 0/6] MIPS: Handle CPU IRQ in domain's way Thomas Bogendoerfer
2020-03-26 15:46   ` Marc Zyngier

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