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From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: linux-mips@vger.kernel.org
Cc: "Jiaxun Yang" <jiaxun.yang@flygoat.com>,
	"Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
	"Huacai Chen" <chenhc@lemote.com>,
	"Aleksandar Markovic" <aleksandar.qemu.devel@gmail.com>,
	"Paul Burton" <paulburton@kernel.org>,
	"Serge Semin" <Sergey.Semin@baikalelectronics.ru>,
	"WANG Xuerui" <git@xen0n.name>,
	"周琰杰 (Zhou Yanjie)" <zhouyanjie@wanyeetech.com>,
	"Liangliang Huang" <huanglllzu@gmail.com>,
	"afzal mohammed" <afzal.mohd.ma@gmail.com>,
	"Peter Xu" <peterx@redhat.com>,
	"Peter Zijlstra (Intel)" <peterz@infradead.org>,
	"Sergey Korolev" <s.korolev@ndmsystems.com>,
	"Alexey Malahov" <Alexey.Malahov@baikalelectronics.ru>,
	"Anup Patel" <anup.patel@wdc.com>,
	"Marc Zyngier" <maz@kernel.org>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	"Michael Kelley" <mikelley@microsoft.com>,
	"Steven Price" <steven.price@arm.com>,
	"Atish Patra" <atish.patra@wdc.com>,
	"Ming Lei" <ming.lei@redhat.com>,
	"Daniel Jordan" <daniel.m.jordan@oracle.com>,
	"Mike Leach" <mike.leach@linaro.org>,
	linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Subject: [PATCH 4/7] MIPS: Loongson64: Remove custom count sync procudure
Date: Mon, 17 Aug 2020 11:46:43 +0800	[thread overview]
Message-ID: <20200817034701.3515721-5-jiaxun.yang@flygoat.com> (raw)
In-Reply-To: <20200817034701.3515721-1-jiaxun.yang@flygoat.com>

Now we have hotplug aware reliable sync-r4k, we can simply use
that instead of our IPI based implementation.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/include/asm/smp.h |  1 -
 arch/mips/loongson64/smp.c  | 32 ++------------------------------
 2 files changed, 2 insertions(+), 31 deletions(-)

diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
index 5d9ff61004ca..2300cc0bba34 100644
--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
@@ -52,7 +52,6 @@ extern int __cpu_logical_map[NR_CPUS];
 #define SMP_CALL_FUNCTION	0x2
 /* Octeon - Tell another core to flush its icache */
 #define SMP_ICACHE_FLUSH	0x4
-#define SMP_ASK_C0COUNT		0x8
 
 /* Mask of CPUs which are currently definitely operating coherently */
 extern cpumask_t cpu_coherent_mask;
diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
index e744e1bee49e..d6a3a7c3d1b2 100644
--- a/arch/mips/loongson64/smp.c
+++ b/arch/mips/loongson64/smp.c
@@ -32,7 +32,6 @@ static void *ipi_clear0_regs[16];
 static void *ipi_status0_regs[16];
 static void *ipi_en0_regs[16];
 static void *ipi_mailbox_buf[16];
-static uint32_t core0_c0count[NR_CPUS];
 
 /* read a 32bit value from ipi register */
 #define loongson3_ipi_read32(addr) readl(addr)
@@ -307,8 +306,8 @@ loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action)
 
 static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id)
 {
-	int i, cpu = smp_processor_id();
-	unsigned int action, c0count;
+	int cpu = smp_processor_id();
+	unsigned int action;
 
 	action = ipi_read_clear(cpu);
 
@@ -321,15 +320,6 @@ static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id)
 		irq_exit();
 	}
 
-	if (action & SMP_ASK_C0COUNT) {
-		BUG_ON(cpu != 0);
-		c0count = read_c0_count();
-		c0count = c0count ? c0count : 1;
-		for (i = 1; i < nr_cpu_ids; i++)
-			core0_c0count[i] = c0count;
-		__wbflush(); /* Let others see the result ASAP */
-	}
-
 	return IRQ_HANDLED;
 }
 
@@ -340,7 +330,6 @@ static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id)
 static void loongson3_init_secondary(void)
 {
 	int i;
-	uint32_t initcount;
 	unsigned int cpu = smp_processor_id();
 	unsigned int imask = STATUSF_IP7 | STATUSF_IP6 |
 			     STATUSF_IP3 | STATUSF_IP2;
@@ -356,23 +345,6 @@ static void loongson3_init_secondary(void)
 		     cpu_logical_map(cpu) % loongson_sysconf.cores_per_package);
 	cpu_data[cpu].package =
 		cpu_logical_map(cpu) / loongson_sysconf.cores_per_package;
-
-	i = 0;
-	core0_c0count[cpu] = 0;
-	loongson3_send_ipi_single(0, SMP_ASK_C0COUNT);
-	while (!core0_c0count[cpu]) {
-		i++;
-		cpu_relax();
-	}
-
-	if (i > MAX_LOOPS)
-		i = MAX_LOOPS;
-	if (cpu_data[cpu].package)
-		initcount = core0_c0count[cpu] + i;
-	else /* Local access is faster for loops */
-		initcount = core0_c0count[cpu] + i/2;
-
-	write_c0_count(initcount);
 }
 
 static void loongson3_smp_finish(void)
-- 
2.28.0.rc1


  parent reply	other threads:[~2020-08-17  3:48 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-17  3:46 [PATCH 0/7] R4000 clock enhancements for Loongson Jiaxun Yang
2020-08-17  3:46 ` [PATCH 1/7] MIPS: sync-r4k: Rework to be many cores firendly Jiaxun Yang
2020-08-17  6:04   ` kernel test robot
2020-08-17  7:55   ` peterz
2020-08-21 15:32   ` kernel test robot
2020-08-17  3:46 ` [PATCH 2/7] MIPS: time: Use CPUHUP to handle r4k timer Jiaxun Yang
2020-08-17  3:46 ` [PATCH 3/7] MIPS: Kconfig: Always select SYNC_R4K if both SMP and r4k timer is enabled Jiaxun Yang
2020-08-17  3:46 ` Jiaxun Yang [this message]
2020-08-17  3:46 ` [PATCH 5/7] MIPS: cevt-r4k: Don't handle IRQ if clockevent is not enabled Jiaxun Yang
2020-08-17  3:46 ` [PATCH 6/7] MIPS: cevt-r4k: Enable intimer for Loongson CPUs with extimer Jiaxun Yang
2020-08-17  3:46 ` [PATCH 7/7] MIPS: KVM: Don't use htimer when INTIMER is disabled Jiaxun Yang

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