From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: linux-mips@vger.kernel.org
Cc: "Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
"Huacai Chen" <chenhc@lemote.com>,
"Aleksandar Markovic" <aleksandar.qemu.devel@gmail.com>,
"Serge Semin" <Sergey.Semin@baikalelectronics.ru>,
"Paul Burton" <paulburton@kernel.org>,
"WANG Xuerui" <git@xen0n.name>,
"Alexey Malahov" <Alexey.Malahov@baikalelectronics.ru>,
"周琰杰 (Zhou Yanjie)" <zhouyanjie@wanyeetech.com>,
"Liangliang Huang" <huanglllzu@gmail.com>,
"afzal mohammed" <afzal.mohd.ma@gmail.com>,
"Peter Zijlstra (Intel)" <peterz@infradead.org>,
"Peter Xu" <peterx@redhat.com>,
"Sergey Korolev" <s.korolev@ndmsystems.com>,
"Marc Zyngier" <maz@kernel.org>,
"Anup Patel" <anup.patel@wdc.com>,
"Herbert Xu" <herbert@gondor.apana.org.au>,
"Steven Price" <steven.price@arm.com>,
"Atish Patra" <atish.patra@wdc.com>,
"Ming Lei" <ming.lei@redhat.com>,
"Daniel Jordan" <daniel.m.jordan@oracle.com>,
"Mike Leach" <mike.leach@linaro.org>,
"Ulf Hansson" <ulf.hansson@linaro.org>,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Subject: [PATCH 5/7] MIPS: cevt-r4k: Don't handle IRQ if clockevent is not enabled
Date: Mon, 17 Aug 2020 11:46:44 +0800 [thread overview]
Message-ID: <20200817034701.3515721-6-jiaxun.yang@flygoat.com> (raw)
In-Reply-To: <20200817034701.3515721-1-jiaxun.yang@flygoat.com>
Some platforms may have shared Cause.TI, bailing out in IRQ handler
when clock event is not enabled can give another clock device a chance.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/kernel/cevt-r4k.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index f0c52d751d0a..d396b1011fee 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -142,6 +142,15 @@ irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
if (handle_perf_irq(r2))
return IRQ_HANDLED;
+ cd = &per_cpu(mips_clockevent_device, cpu);
+ /*
+ * If the clockevent have not enabled, then no need to check the rest.
+ * Some platforms may have shared Cause.TI, bailing out here can
+ * give another clock device a chance.
+ */
+ if (clockevent_state_detached(cd) || clockevent_state_shutdown(cd))
+ return IRQ_NONE;
+
/*
* The same applies to performance counter interrupts. But with the
* above we now know that the reason we got here must be a timer
@@ -150,7 +159,6 @@ irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
if (!r2 || (read_c0_cause() & CAUSEF_TI)) {
/* Clear Count/Compare Interrupt */
write_c0_compare(read_c0_compare());
- cd = &per_cpu(mips_clockevent_device, cpu);
cd->event_handler(cd);
return IRQ_HANDLED;
--
2.28.0.rc1
next prev parent reply other threads:[~2020-08-17 3:49 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-17 3:46 [PATCH 0/7] R4000 clock enhancements for Loongson Jiaxun Yang
2020-08-17 3:46 ` [PATCH 1/7] MIPS: sync-r4k: Rework to be many cores firendly Jiaxun Yang
2020-08-17 6:04 ` kernel test robot
2020-08-17 7:55 ` peterz
2020-08-21 15:32 ` kernel test robot
2020-08-17 3:46 ` [PATCH 2/7] MIPS: time: Use CPUHUP to handle r4k timer Jiaxun Yang
2020-08-17 3:46 ` [PATCH 3/7] MIPS: Kconfig: Always select SYNC_R4K if both SMP and r4k timer is enabled Jiaxun Yang
2020-08-17 3:46 ` [PATCH 4/7] MIPS: Loongson64: Remove custom count sync procudure Jiaxun Yang
2020-08-17 3:46 ` Jiaxun Yang [this message]
2020-08-17 3:46 ` [PATCH 6/7] MIPS: cevt-r4k: Enable intimer for Loongson CPUs with extimer Jiaxun Yang
2020-08-17 3:46 ` [PATCH 7/7] MIPS: KVM: Don't use htimer when INTIMER is disabled Jiaxun Yang
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