From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: linux-mips@vger.kernel.org
Cc: "Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
"Huacai Chen" <chenhc@lemote.com>,
"Aleksandar Markovic" <aleksandar.qemu.devel@gmail.com>,
"Serge Semin" <Sergey.Semin@baikalelectronics.ru>,
"Paul Burton" <paulburton@kernel.org>,
"WANG Xuerui" <git@xen0n.name>,
"周琰杰 (Zhou Yanjie)" <zhouyanjie@wanyeetech.com>,
"Liangliang Huang" <huanglllzu@gmail.com>,
"afzal mohammed" <afzal.mohd.ma@gmail.com>,
"Peter Xu" <peterx@redhat.com>,
"Peter Zijlstra (Intel)" <peterz@infradead.org>,
"Ingo Molnar" <mingo@kernel.org>,
"Sergey Korolev" <s.korolev@ndmsystems.com>,
"Alexey Malahov" <Alexey.Malahov@baikalelectronics.ru>,
"Marc Zyngier" <maz@kernel.org>,
"Anup Patel" <anup.patel@wdc.com>,
"Daniel Jordan" <daniel.m.jordan@oracle.com>,
"Ulf Hansson" <ulf.hansson@linaro.org>,
"Atish Patra" <atish.patra@wdc.com>,
"Steven Price" <steven.price@arm.com>,
"Mike Leach" <mike.leach@linaro.org>,
"Ming Lei" <ming.lei@redhat.com>,
"Michael Kelley" <mikelley@microsoft.com>,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Subject: [PATCH 6/7] MIPS: cevt-r4k: Enable intimer for Loongson CPUs with extimer
Date: Mon, 17 Aug 2020 11:46:45 +0800 [thread overview]
Message-ID: <20200817034701.3515721-7-jiaxun.yang@flygoat.com> (raw)
In-Reply-To: <20200817034701.3515721-1-jiaxun.yang@flygoat.com>
Loongson64C and Loongson64G have extimer feature, which is sharing
Cause.TI with intimer (which is cevt-r4k).
To ensure the cevt-r4k's usability, we need to add a callback for
clock device to ensure intimer is enabled when cevt-r4k is enabled.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/include/asm/cpu-features.h | 4 ++++
arch/mips/include/asm/cpu.h | 1 +
arch/mips/kernel/cevt-r4k.c | 25 +++++++++++++++++++++++++
arch/mips/kernel/cpu-probe.c | 6 +++++-
4 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 78cf7e300f12..aec458eee2a5 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -576,6 +576,10 @@
# define cpu_has_gsexcex __opt(MIPS_CPU_GSEXCEX)
#endif
+#ifndef cpu_has_extimer
+# define cpu_has_extimer __opt(MIPS_CPU_EXTIMER)
+#endif
+
#ifdef CONFIG_SMP
/*
* Some systems share FTLB RAMs between threads within a core (siblings in
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 388a82f28a87..854e1b44254b 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -429,6 +429,7 @@ enum cpu_type_enum {
#define MIPS_CPU_MAC_2008_ONLY BIT_ULL(60) /* CPU Only support MAC2008 Fused multiply-add instruction */
#define MIPS_CPU_FTLBPAREX BIT_ULL(61) /* CPU has FTLB parity exception */
#define MIPS_CPU_GSEXCEX BIT_ULL(62) /* CPU has GSExc exception */
+#define MIPS_CPU_EXTIMER BIT_ULL(63) /* CPU has External Timer (Loongson) */
/*
* CPU ASE encodings
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index d396b1011fee..a6e56e9d4e70 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -15,6 +15,8 @@
#include <asm/time.h>
#include <asm/cevt-r4k.h>
+#include <asm/cpu-features.h>
+#include <asm/mipsregs.h>
static int mips_next_event(unsigned long delta,
struct clock_event_device *evt)
@@ -302,6 +304,24 @@ core_initcall(r4k_register_cpufreq_notifier);
#endif /* !CONFIG_CPU_FREQ */
+#ifdef CONFIG_CPU_LOONGSON64
+static int c0_compare_int_enable(struct clock_event_device *cd)
+{
+ if (cpu_has_extimer)
+ set_c0_config6(LOONGSON_CONF6_INTIMER);
+
+ return 0;
+}
+
+static int c0_compare_int_disable(struct clock_event_device *cd)
+{
+ if (cpu_has_extimer)
+ clear_c0_config6(LOONGSON_CONF6_INTIMER);
+
+ return 0;
+}
+#endif
+
int r4k_clockevent_percpu_init(int cpu)
{
struct clock_event_device *cd;
@@ -330,6 +350,11 @@ int r4k_clockevent_percpu_init(int cpu)
cd->set_next_event = mips_next_event;
cd->event_handler = mips_event_handler;
+#ifdef CONFIG_CPU_LOONGSON64
+ cd->set_state_oneshot = c0_compare_int_enable;
+ cd->set_state_shutdown = c0_compare_int_disable;
+#endif
+
clockevents_config_and_register(cd, mips_hpt_frequency, min_delta, 0x7fffffff);
return 0;
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index e2955f1f6316..f41e8d4f6d84 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -2030,6 +2030,9 @@ static inline void decode_cpucfg(struct cpuinfo_mips *c)
if (cfg2 & LOONGSON_CFG2_LEXT2)
c->ases |= MIPS_ASE_LOONGSON_EXT2;
+ if (cfg2 & LOONGSON_CFG2_LLFTP)
+ c->options |= MIPS_CPU_EXTIMER;
+
if (cfg2 & LOONGSON_CFG2_LSPW) {
c->options |= MIPS_CPU_LDPTE;
c->guest.options |= MIPS_CPU_LDPTE;
@@ -2088,7 +2091,8 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
* Also some early Loongson-3A2000 had wrong TLB type in Config
* register, we correct it here.
*/
- c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
+ c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE |
+ MIPS_CPU_EXTIMER;
c->writecombine = _CACHE_UNCACHED_ACCELERATED;
c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
--
2.28.0.rc1
next prev parent reply other threads:[~2020-08-17 3:49 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-17 3:46 [PATCH 0/7] R4000 clock enhancements for Loongson Jiaxun Yang
2020-08-17 3:46 ` [PATCH 1/7] MIPS: sync-r4k: Rework to be many cores firendly Jiaxun Yang
2020-08-17 6:04 ` kernel test robot
2020-08-17 7:55 ` peterz
2020-08-21 15:32 ` kernel test robot
2020-08-17 3:46 ` [PATCH 2/7] MIPS: time: Use CPUHUP to handle r4k timer Jiaxun Yang
2020-08-17 3:46 ` [PATCH 3/7] MIPS: Kconfig: Always select SYNC_R4K if both SMP and r4k timer is enabled Jiaxun Yang
2020-08-17 3:46 ` [PATCH 4/7] MIPS: Loongson64: Remove custom count sync procudure Jiaxun Yang
2020-08-17 3:46 ` [PATCH 5/7] MIPS: cevt-r4k: Don't handle IRQ if clockevent is not enabled Jiaxun Yang
2020-08-17 3:46 ` Jiaxun Yang [this message]
2020-08-17 3:46 ` [PATCH 7/7] MIPS: KVM: Don't use htimer when INTIMER is disabled Jiaxun Yang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200817034701.3515721-7-jiaxun.yang@flygoat.com \
--to=jiaxun.yang@flygoat.com \
--cc=Alexey.Malahov@baikalelectronics.ru \
--cc=Sergey.Semin@baikalelectronics.ru \
--cc=afzal.mohd.ma@gmail.com \
--cc=aleksandar.qemu.devel@gmail.com \
--cc=anup.patel@wdc.com \
--cc=atish.patra@wdc.com \
--cc=chenhc@lemote.com \
--cc=daniel.m.jordan@oracle.com \
--cc=git@xen0n.name \
--cc=huanglllzu@gmail.com \
--cc=kvm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mips@vger.kernel.org \
--cc=maz@kernel.org \
--cc=mike.leach@linaro.org \
--cc=mikelley@microsoft.com \
--cc=ming.lei@redhat.com \
--cc=mingo@kernel.org \
--cc=paulburton@kernel.org \
--cc=peterx@redhat.com \
--cc=peterz@infradead.org \
--cc=s.korolev@ndmsystems.com \
--cc=steven.price@arm.com \
--cc=tsbogend@alpha.franken.de \
--cc=ulf.hansson@linaro.org \
--cc=zhouyanjie@wanyeetech.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).