From: James Hogan <james.hogan@imgtec.com> To: <linux-mips@linux-mips.org> Cc: "James Hogan" <james.hogan@imgtec.com>, "Ralf Baechle" <ralf@linux-mips.org>, "Paolo Bonzini" <pbonzini@redhat.com>, "Radim Krčmář" <rkrcmar@redhat.com>, kvm@vger.kernel.org Subject: [PATCH 4/30] MIPS: Export some tlbex internals for KVM to use Date: Fri, 6 Jan 2017 01:32:36 +0000 [thread overview] Message-ID: <3007c32a817fa8ab6f1b20069d595d5f853c3545.1483665879.git-series.james.hogan@imgtec.com> (raw) In-Reply-To: <cover.d6d201de414322ed2c1372e164254e6055ef7db9.1483665879.git-series.james.hogan@imgtec.com> Export to TLB exception code generating functions so that KVM can construct a fast TLB refill handler for guest context without reinventing the wheel quite so much. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org --- arch/mips/include/asm/tlbex.h | 26 ++++++++++++++++++++++++++ arch/mips/mm/tlbex.c | 33 ++++++++++++++++----------------- 2 files changed, 42 insertions(+), 17 deletions(-) create mode 100644 arch/mips/include/asm/tlbex.h diff --git a/arch/mips/include/asm/tlbex.h b/arch/mips/include/asm/tlbex.h new file mode 100644 index 000000000000..53050e9dd2c9 --- /dev/null +++ b/arch/mips/include/asm/tlbex.h @@ -0,0 +1,26 @@ +#ifndef __ASM_TLBEX_H +#define __ASM_TLBEX_H + +#include <asm/uasm.h> + +/* + * Write random or indexed TLB entry, and care about the hazards from + * the preceding mtc0 and for the following eret. + */ +enum tlb_write_entry { + tlb_random, + tlb_indexed +}; + +extern int pgd_reg; + +void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, + unsigned int tmp, unsigned int ptr); +void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr); +void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr); +void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep); +void build_tlb_write_entry(u32 **p, struct uasm_label **l, + struct uasm_reloc **r, + enum tlb_write_entry wmode); + +#endif /* __ASM_TLBEX_H */ diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index dc7bb1506103..2465f83c79c3 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -35,6 +35,7 @@ #include <asm/war.h> #include <asm/uasm.h> #include <asm/setup.h> +#include <asm/tlbex.h> static int mips_xpa_disabled; @@ -345,7 +346,8 @@ static int allocate_kscratch(void) } static int scratch_reg; -static int pgd_reg; +int pgd_reg; +EXPORT_SYMBOL_GPL(pgd_reg); enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch}; static struct work_registers build_get_work_registers(u32 **p) @@ -497,15 +499,9 @@ static void __maybe_unused build_tlb_probe_entry(u32 **p) } } -/* - * Write random or indexed TLB entry, and care about the hazards from - * the preceding mtc0 and for the following eret. - */ -enum tlb_write_entry { tlb_random, tlb_indexed }; - -static void build_tlb_write_entry(u32 **p, struct uasm_label **l, - struct uasm_reloc **r, - enum tlb_write_entry wmode) +void build_tlb_write_entry(u32 **p, struct uasm_label **l, + struct uasm_reloc **r, + enum tlb_write_entry wmode) { void(*tlbw)(u32 **) = NULL; @@ -628,6 +624,7 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l, break; } } +EXPORT_SYMBOL_GPL(build_tlb_write_entry); static __maybe_unused void build_convert_pte_to_entrylo(u32 **p, unsigned int reg) @@ -782,9 +779,8 @@ static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r, * TMP and PTR are scratch. * TMP will be clobbered, PTR will hold the pmd entry. */ -static void -build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, - unsigned int tmp, unsigned int ptr) +void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, + unsigned int tmp, unsigned int ptr) { #ifndef CONFIG_MIPS_PGD_C0_CONTEXT long pgdc = (long)pgd_current; @@ -860,6 +856,7 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ #endif } +EXPORT_SYMBOL_GPL(build_get_pmde64); /* * BVADDR is the faulting address, PTR is scratch. @@ -935,8 +932,7 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, * TMP and PTR are scratch. * TMP will be clobbered, PTR will hold the pgd entry. */ -static void __maybe_unused -build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) +void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) { if (pgd_reg != -1) { /* pgd is in pgd_reg */ @@ -961,6 +957,7 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ } +EXPORT_SYMBOL_GPL(build_get_pgde32); #endif /* !CONFIG_64BIT */ @@ -990,7 +987,7 @@ static void build_adjust_context(u32 **p, unsigned int ctx) uasm_i_andi(p, ctx, ctx, mask); } -static void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) +void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) { /* * Bug workaround for the Nevada. It seems as if under certain @@ -1014,8 +1011,9 @@ static void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) build_adjust_context(p, tmp); UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ } +EXPORT_SYMBOL_GPL(build_get_ptep); -static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) +void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) { int pte_off_even = 0; int pte_off_odd = sizeof(pte_t); @@ -1064,6 +1062,7 @@ static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) UASM_i_MTC0(p, 0, C0_ENTRYLO1); UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ } +EXPORT_SYMBOL_GPL(build_update_entries); struct mips_huge_tlb_info { int huge_pte; -- git-series 0.8.10
WARNING: multiple messages have this Message-ID (diff)
From: James Hogan <james.hogan@imgtec.com> To: linux-mips@linux-mips.org Cc: "James Hogan" <james.hogan@imgtec.com>, "Ralf Baechle" <ralf@linux-mips.org>, "Paolo Bonzini" <pbonzini@redhat.com>, "Radim Krčmář" <rkrcmar@redhat.com>, kvm@vger.kernel.org Subject: [PATCH 4/30] MIPS: Export some tlbex internals for KVM to use Date: Fri, 6 Jan 2017 01:32:36 +0000 [thread overview] Message-ID: <3007c32a817fa8ab6f1b20069d595d5f853c3545.1483665879.git-series.james.hogan@imgtec.com> (raw) Message-ID: <20170106013236.mMEWtZgswymfAItG3qnhffSruMa-49J7MxBrvAFanI0@z> (raw) In-Reply-To: <cover.d6d201de414322ed2c1372e164254e6055ef7db9.1483665879.git-series.james.hogan@imgtec.com> Export to TLB exception code generating functions so that KVM can construct a fast TLB refill handler for guest context without reinventing the wheel quite so much. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org --- arch/mips/include/asm/tlbex.h | 26 ++++++++++++++++++++++++++ arch/mips/mm/tlbex.c | 33 ++++++++++++++++----------------- 2 files changed, 42 insertions(+), 17 deletions(-) create mode 100644 arch/mips/include/asm/tlbex.h diff --git a/arch/mips/include/asm/tlbex.h b/arch/mips/include/asm/tlbex.h new file mode 100644 index 000000000000..53050e9dd2c9 --- /dev/null +++ b/arch/mips/include/asm/tlbex.h @@ -0,0 +1,26 @@ +#ifndef __ASM_TLBEX_H +#define __ASM_TLBEX_H + +#include <asm/uasm.h> + +/* + * Write random or indexed TLB entry, and care about the hazards from + * the preceding mtc0 and for the following eret. + */ +enum tlb_write_entry { + tlb_random, + tlb_indexed +}; + +extern int pgd_reg; + +void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, + unsigned int tmp, unsigned int ptr); +void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr); +void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr); +void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep); +void build_tlb_write_entry(u32 **p, struct uasm_label **l, + struct uasm_reloc **r, + enum tlb_write_entry wmode); + +#endif /* __ASM_TLBEX_H */ diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index dc7bb1506103..2465f83c79c3 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -35,6 +35,7 @@ #include <asm/war.h> #include <asm/uasm.h> #include <asm/setup.h> +#include <asm/tlbex.h> static int mips_xpa_disabled; @@ -345,7 +346,8 @@ static int allocate_kscratch(void) } static int scratch_reg; -static int pgd_reg; +int pgd_reg; +EXPORT_SYMBOL_GPL(pgd_reg); enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch}; static struct work_registers build_get_work_registers(u32 **p) @@ -497,15 +499,9 @@ static void __maybe_unused build_tlb_probe_entry(u32 **p) } } -/* - * Write random or indexed TLB entry, and care about the hazards from - * the preceding mtc0 and for the following eret. - */ -enum tlb_write_entry { tlb_random, tlb_indexed }; - -static void build_tlb_write_entry(u32 **p, struct uasm_label **l, - struct uasm_reloc **r, - enum tlb_write_entry wmode) +void build_tlb_write_entry(u32 **p, struct uasm_label **l, + struct uasm_reloc **r, + enum tlb_write_entry wmode) { void(*tlbw)(u32 **) = NULL; @@ -628,6 +624,7 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l, break; } } +EXPORT_SYMBOL_GPL(build_tlb_write_entry); static __maybe_unused void build_convert_pte_to_entrylo(u32 **p, unsigned int reg) @@ -782,9 +779,8 @@ static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r, * TMP and PTR are scratch. * TMP will be clobbered, PTR will hold the pmd entry. */ -static void -build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, - unsigned int tmp, unsigned int ptr) +void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, + unsigned int tmp, unsigned int ptr) { #ifndef CONFIG_MIPS_PGD_C0_CONTEXT long pgdc = (long)pgd_current; @@ -860,6 +856,7 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ #endif } +EXPORT_SYMBOL_GPL(build_get_pmde64); /* * BVADDR is the faulting address, PTR is scratch. @@ -935,8 +932,7 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, * TMP and PTR are scratch. * TMP will be clobbered, PTR will hold the pgd entry. */ -static void __maybe_unused -build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) +void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) { if (pgd_reg != -1) { /* pgd is in pgd_reg */ @@ -961,6 +957,7 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ } +EXPORT_SYMBOL_GPL(build_get_pgde32); #endif /* !CONFIG_64BIT */ @@ -990,7 +987,7 @@ static void build_adjust_context(u32 **p, unsigned int ctx) uasm_i_andi(p, ctx, ctx, mask); } -static void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) +void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) { /* * Bug workaround for the Nevada. It seems as if under certain @@ -1014,8 +1011,9 @@ static void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) build_adjust_context(p, tmp); UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ } +EXPORT_SYMBOL_GPL(build_get_ptep); -static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) +void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) { int pte_off_even = 0; int pte_off_odd = sizeof(pte_t); @@ -1064,6 +1062,7 @@ static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) UASM_i_MTC0(p, 0, C0_ENTRYLO1); UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ } +EXPORT_SYMBOL_GPL(build_update_entries); struct mips_huge_tlb_info { int huge_pte; -- git-series 0.8.10
next prev parent reply other threads:[~2017-01-06 1:36 UTC|newest] Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-01-06 1:32 [PATCH 0/30] KVM: MIPS: Implement GVA page tables James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-06 1:32 ` [PATCH 1/30] mm: Export init_mm for MIPS KVM use of pgd_alloc() James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-17 16:23 ` Ralf Baechle 2017-01-17 16:27 ` Ralf Baechle 2017-01-06 1:32 ` [PATCH 2/30] MIPS: Export pgd/pmd symbols for KVM James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-17 16:24 ` Ralf Baechle 2017-01-06 1:32 ` [PATCH 3/30] MIPS: uasm: Add include guards in asm/uasm.h James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-17 16:25 ` Ralf Baechle 2017-01-06 1:32 ` James Hogan [this message] 2017-01-06 1:32 ` [PATCH 4/30] MIPS: Export some tlbex internals for KVM to use James Hogan 2017-01-17 16:26 ` Ralf Baechle 2017-01-06 1:32 ` [PATCH 5/30] KVM: MIPS: Drop partial KVM_NMI implementation James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-06 1:32 ` [PATCH 6/30] KVM: MIPS/MMU: Simplify ASID restoration James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-06 1:32 ` [PATCH 7/30] KVM: MIPS: Convert get/set_regs -> vcpu_load/put James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-06 1:32 ` [PATCH 8/30] KVM: MIPS/MMU: Move preempt/ASID handling to implementation James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-06 1:32 ` [PATCH 9/30] KVM: MIPS: Remove duplicated ASIDs from vcpu James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-06 1:32 ` [PATCH 10/30] KVM: MIPS: Add vcpu_run() & vcpu_reenter() callbacks James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-06 1:32 ` [PATCH 11/30] KVM: MIPS/T&E: Restore host asid on return to host James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-06 1:32 ` [PATCH 12/30] KVM: MIPS/T&E: active_mm = init_mm in guest context James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-06 1:32 ` [PATCH 13/30] KVM: MIPS: Wire up vcpu uninit James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-06 1:32 ` [PATCH 14/30] KVM: MIPS/T&E: Allocate GVA -> HPA page tables James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-06 1:32 ` [PATCH 15/30] KVM: MIPS/T&E: Activate GVA page tables in guest context James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-06 1:32 ` [PATCH 16/30] KVM: MIPS: Support NetLogic KScratch registers James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-06 1:32 ` [PATCH 17/30] KVM: MIPS: Add fast path TLB refill handler James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-06 1:32 ` [PATCH 18/30] KVM: MIPS/TLB: Fix off-by-one in TLB invalidate James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-06 1:32 ` [PATCH 19/30] KVM: MIPS/TLB: Generalise host TLB invalidate to kernel ASID James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-06 1:32 ` [PATCH 20/30] KVM: MIPS/MMU: Invalidate GVA PTs on ASID changes James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-06 1:32 ` [PATCH 21/30] KVM: MIPS/MMU: Invalidate stale GVA PTEs on TLBW James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-06 1:32 ` [PATCH 22/30] KVM: MIPS/MMU: Convert KSeg0 faults to page tables James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-06 1:32 ` [PATCH 23/30] KVM: MIPS/MMU: Convert TLB mapped " James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-06 1:32 ` [PATCH 24/30] KVM: MIPS/MMU: Convert commpage fault handling " James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-06 1:32 ` [PATCH 25/30] KVM: MIPS: Drop vm_init() callback James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-06 1:32 ` [PATCH 26/30] KVM: MIPS: Use uaccess to read/modify guest instructions James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-06 1:32 ` [PATCH 27/30] KVM: MIPS/Emulate: Fix CACHE emulation for EVA hosts James Hogan 2017-01-06 1:32 ` James Hogan 2017-01-06 1:33 ` [PATCH 28/30] KVM: MIPS/TLB: Drop kvm_local_flush_tlb_all() James Hogan 2017-01-06 1:33 ` James Hogan 2017-01-06 1:33 ` [PATCH 29/30] KVM: MIPS/Emulate: Drop redundant TLB flushes on exceptions James Hogan 2017-01-06 1:33 ` James Hogan 2017-01-06 1:33 ` [PATCH 30/30] KVM: MIPS/MMU: Drop kvm_get_new_mmu_context() James Hogan 2017-01-06 1:33 ` James Hogan
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