* [PATCH 1/3] MIPS: Select R3k-style TLB in Kconfig
@ 2019-08-31 15:40 Paul Burton
2019-08-31 15:40 ` [PATCH 2/3] MIPS: tlbex: Simplify r3k check Paul Burton
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Paul Burton @ 2019-08-31 15:40 UTC (permalink / raw)
To: linux-mips; +Cc: Paul Burton
Currently areas where we need to determine whether the TLB is R3k-style
need to check for either of CONFIG_CPU_R3000 || CONFIG_CPU_TX39XX.
Introduce a new CONFIG_CPU_R3K_TLB & select it from both of the above,
allowing us to simplify checks for R3k-style TLBs by only checking for
this new Kconfig option.
Signed-off-by: Paul Burton <paul.burton@mips.com>
---
arch/mips/Kconfig | 7 ++++++-
arch/mips/include/asm/pgtable-32.h | 4 ++--
arch/mips/include/asm/pgtable-bits.h | 6 +++---
arch/mips/include/asm/pgtable.h | 4 ++--
arch/mips/mm/Makefile | 5 +++--
5 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 31c7044e34e6..3f18aa018a0c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1575,6 +1575,7 @@ config CPU_R3000
depends on SYS_HAS_CPU_R3000
select CPU_HAS_WB
select CPU_HAS_LOAD_STORE_LR
+ select CPU_R3K_TLB
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
help
@@ -1590,6 +1591,7 @@ config CPU_TX39XX
depends on SYS_HAS_CPU_TX39XX
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_HAS_LOAD_STORE_LR
+ select CPU_R3K_TLB
config CPU_VR41XX
bool "R41xx"
@@ -2280,6 +2282,9 @@ config CPU_R2300_FPU
depends on MIPS_FP_SUPPORT
default y if CPU_R3000 || CPU_TX39XX
+config CPU_R3K_TLB
+ bool
+
config CPU_R4K_FPU
bool
depends on MIPS_FP_SUPPORT
@@ -2287,7 +2292,7 @@ config CPU_R4K_FPU
config CPU_R4K_CACHE_TLB
bool
- default y if !(CPU_R3000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
+ default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
config MIPS_MT_SMP
bool "MIPS MT SMP support (1 TC on each available VPE)"
diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h
index e600570789f4..ba967148b016 100644
--- a/arch/mips/include/asm/pgtable-32.h
+++ b/arch/mips/include/asm/pgtable-32.h
@@ -221,7 +221,7 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
#define pte_unmap(pte) ((void)(pte))
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#if defined(CONFIG_CPU_R3K_TLB)
/* Swap entries must have VALID bit cleared. */
#define __swp_type(x) (((x).val >> 10) & 0x1f)
@@ -266,6 +266,6 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
-#endif /* defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) */
+#endif /* defined(CONFIG_CPU_R3K_TLB) */
#endif /* _ASM_PGTABLE_32_H */
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index c2c1060b43ef..5f1ced8cba07 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -82,7 +82,7 @@ enum pgtable_bits {
_PAGE_SPECIAL_SHIFT,
};
-#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#elif defined(CONFIG_CPU_R3K_TLB)
/* Page table bits used for r3k systems */
enum pgtable_bits {
@@ -151,7 +151,7 @@ enum pgtable_bits {
#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#if defined(CONFIG_CPU_R3K_TLB)
# define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT)
# define _CACHE_MASK _CACHE_UNCACHED
# define _PFN_SHIFT PAGE_SHIFT
@@ -209,7 +209,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
/*
* Cache attributes
*/
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#if defined(CONFIG_CPU_R3K_TLB)
#define _CACHE_CACHABLE_NONCOHERENT 0
#define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index d60f47a9088c..4dca733d5076 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -199,7 +199,7 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt
static inline void set_pte(pte_t *ptep, pte_t pteval)
{
*ptep = pteval;
-#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX)
+#if !defined(CONFIG_CPU_R3K_TLB)
if (pte_val(pteval) & _PAGE_GLOBAL) {
pte_t *buddy = ptep_buddy(ptep);
/*
@@ -218,7 +218,7 @@ static inline void set_pte(pte_t *ptep, pte_t pteval)
static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
{
htw_stop();
-#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX)
+#if !defined(CONFIG_CPU_R3K_TLB)
/* Preserve global status for the pair */
if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL)
set_pte_at(mm, addr, ptep, __pte(_PAGE_GLOBAL));
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index 949d43eefda1..46f483e952c8 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -28,10 +28,11 @@ obj-$(CONFIG_HIGHMEM) += highmem.o
obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
obj-$(CONFIG_DMA_NONCOHERENT) += dma-noncoherent.o
+obj-$(CONFIG_CPU_R3K_TLB) += tlb-r3k.o
obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o
-obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o
+obj-$(CONFIG_CPU_R3000) += c-r3k.o
obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o
-obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o
+obj-$(CONFIG_CPU_TX39XX) += c-tx39.o
obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o
obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
--
2.22.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/3] MIPS: tlbex: Simplify r3k check
2019-08-31 15:40 [PATCH 1/3] MIPS: Select R3k-style TLB in Kconfig Paul Burton
@ 2019-08-31 15:40 ` Paul Burton
2019-08-31 15:40 ` [PATCH 3/3] MIPS: tlbex: Remove cpu_has_local_ebase Paul Burton
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Paul Burton @ 2019-08-31 15:40 UTC (permalink / raw)
To: linux-mips; +Cc: Paul Burton
We already know whether a CPU has r3k style exceptions, including TLB
exceptions, by checking cpu_has_3kex. Remove the list of CPU types in
build_tlb_refill_handler() & check cpu_has_3kex instead.
Signed-off-by: Paul Burton <paul.burton@mips.com>
---
arch/mips/mm/tlbex.c | 52 +++++++++++++++++++-------------------------
1 file changed, 22 insertions(+), 30 deletions(-)
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 071d48593464..6e3ca9cc5249 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -2607,14 +2607,7 @@ void build_tlb_refill_handler(void)
check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
#endif
- switch (current_cpu_type()) {
- case CPU_R2000:
- case CPU_R3000:
- case CPU_R3000A:
- case CPU_R3081E:
- case CPU_TX3912:
- case CPU_TX3922:
- case CPU_TX3927:
+ if (cpu_has_3kex) {
#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
if (cpu_has_local_ebase)
build_r3000_tlb_refill_handler();
@@ -2631,30 +2624,29 @@ void build_tlb_refill_handler(void)
#else
panic("No R3000 TLB refill handler");
#endif
- break;
+ return;
+ }
- default:
- if (cpu_has_ldpte)
- setup_pw();
+ if (cpu_has_ldpte)
+ setup_pw();
- if (!run_once) {
- scratch_reg = allocate_kscratch();
- build_setup_pgd();
- build_r4000_tlb_load_handler();
- build_r4000_tlb_store_handler();
- build_r4000_tlb_modify_handler();
- if (cpu_has_ldpte)
- build_loongson3_tlb_refill_handler();
- else if (!cpu_has_local_ebase)
- build_r4000_tlb_refill_handler();
- flush_tlb_handlers();
- run_once++;
- }
- if (cpu_has_local_ebase)
+ if (!run_once) {
+ scratch_reg = allocate_kscratch();
+ build_setup_pgd();
+ build_r4000_tlb_load_handler();
+ build_r4000_tlb_store_handler();
+ build_r4000_tlb_modify_handler();
+ if (cpu_has_ldpte)
+ build_loongson3_tlb_refill_handler();
+ else if (!cpu_has_local_ebase)
build_r4000_tlb_refill_handler();
- if (cpu_has_xpa)
- config_xpa_params();
- if (cpu_has_htw)
- config_htw_params();
+ flush_tlb_handlers();
+ run_once++;
}
+ if (cpu_has_local_ebase)
+ build_r4000_tlb_refill_handler();
+ if (cpu_has_xpa)
+ config_xpa_params();
+ if (cpu_has_htw)
+ config_htw_params();
}
--
2.22.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/3] MIPS: tlbex: Remove cpu_has_local_ebase
2019-08-31 15:40 [PATCH 1/3] MIPS: Select R3k-style TLB in Kconfig Paul Burton
2019-08-31 15:40 ` [PATCH 2/3] MIPS: tlbex: Simplify r3k check Paul Burton
@ 2019-08-31 15:40 ` Paul Burton
2019-09-01 23:19 ` Philippe Mathieu-Daudé
2019-09-30 4:29 ` Maciej W. Rozycki
2019-09-01 22:54 ` [PATCH 1/3] MIPS: Select R3k-style TLB in Kconfig Philippe Mathieu-Daudé
2019-09-03 14:45 ` Paul Burton
3 siblings, 2 replies; 7+ messages in thread
From: Paul Burton @ 2019-08-31 15:40 UTC (permalink / raw)
To: linux-mips; +Cc: Paul Burton
The cpu_has_local_ebase macro is, confusingly, not used to indicate
whether the EBase register is local to a CPU or not. Instead it
indicates whether we want to generate the TLB refill exception vector
each time a CPU is brought online. Doing this makes little sense on any
system, since we always use the same value for EBase & thus we cannot
have different TLB refill exception handlers per CPU.
Regenerating the code is not only pointless but also can be actively
harmful, as commit 8759934e2b6b ("MIPS: Build uasm-generated code only
once to avoid CPU Hotplug problem") described. That commit introduced
cpu_has_local_ebase to disable the handler regeneration for Loongson
machines, but this is by no means a Loongson-specific problem.
Remove cpu_has_local_ebase & simply generate the TLB refill handler once
during boot, just like the rest of the TLB exception handlers.
Signed-off-by: Paul Burton <paul.burton@mips.com>
---
arch/mips/include/asm/cpu-features.h | 3 ---
arch/mips/include/asm/mach-dec/cpu-feature-overrides.h | 1 -
.../include/asm/mach-loongson64/cpu-feature-overrides.h | 1 -
arch/mips/mm/tlbex.c | 9 ++-------
4 files changed, 2 insertions(+), 12 deletions(-)
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 4e2bea8875f5..983a6a7f43a1 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -243,9 +243,6 @@
#ifndef cpu_has_pindexed_dcache
#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
#endif
-#ifndef cpu_has_local_ebase
-#define cpu_has_local_ebase 1
-#endif
/*
* I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
diff --git a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
index 1c11310bc8ad..00beb69bfab9 100644
--- a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
@@ -32,7 +32,6 @@
#define cpu_has_vtag_icache 0
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_pindexed_dcache 0
-#define cpu_has_local_ebase 0
#define cpu_icache_snoops_remote_store 1
#define cpu_has_mips_4 0
#define cpu_has_mips_5 0
diff --git a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
index 581915ce231c..4aca25f2ff06 100644
--- a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
@@ -43,7 +43,6 @@
#define cpu_has_vint 0
#define cpu_has_vtag_icache 0
#define cpu_has_watch 1
-#define cpu_has_local_ebase 0
#ifdef CONFIG_CPU_LOONGSON3
#define cpu_has_wsbh 1
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 6e3ca9cc5249..e01cb33bfa1a 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -2609,12 +2609,9 @@ void build_tlb_refill_handler(void)
if (cpu_has_3kex) {
#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
- if (cpu_has_local_ebase)
- build_r3000_tlb_refill_handler();
if (!run_once) {
- if (!cpu_has_local_ebase)
- build_r3000_tlb_refill_handler();
build_setup_pgd();
+ build_r3000_tlb_refill_handler();
build_r3000_tlb_load_handler();
build_r3000_tlb_store_handler();
build_r3000_tlb_modify_handler();
@@ -2638,13 +2635,11 @@ void build_tlb_refill_handler(void)
build_r4000_tlb_modify_handler();
if (cpu_has_ldpte)
build_loongson3_tlb_refill_handler();
- else if (!cpu_has_local_ebase)
+ else
build_r4000_tlb_refill_handler();
flush_tlb_handlers();
run_once++;
}
- if (cpu_has_local_ebase)
- build_r4000_tlb_refill_handler();
if (cpu_has_xpa)
config_xpa_params();
if (cpu_has_htw)
--
2.22.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/3] MIPS: Select R3k-style TLB in Kconfig
2019-08-31 15:40 [PATCH 1/3] MIPS: Select R3k-style TLB in Kconfig Paul Burton
2019-08-31 15:40 ` [PATCH 2/3] MIPS: tlbex: Simplify r3k check Paul Burton
2019-08-31 15:40 ` [PATCH 3/3] MIPS: tlbex: Remove cpu_has_local_ebase Paul Burton
@ 2019-09-01 22:54 ` Philippe Mathieu-Daudé
2019-09-03 14:45 ` Paul Burton
3 siblings, 0 replies; 7+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-09-01 22:54 UTC (permalink / raw)
To: Paul Burton, linux-mips; +Cc: Paul Burton
On 8/31/19 5:40 PM, Paul Burton wrote:
> Currently areas where we need to determine whether the TLB is R3k-style
> need to check for either of CONFIG_CPU_R3000 || CONFIG_CPU_TX39XX.
>
> Introduce a new CONFIG_CPU_R3K_TLB & select it from both of the above,
> allowing us to simplify checks for R3k-style TLBs by only checking for
> this new Kconfig option.
>
> Signed-off-by: Paul Burton <paul.burton@mips.com>
> ---
>
> arch/mips/Kconfig | 7 ++++++-
> arch/mips/include/asm/pgtable-32.h | 4 ++--
> arch/mips/include/asm/pgtable-bits.h | 6 +++---
> arch/mips/include/asm/pgtable.h | 4 ++--
> arch/mips/mm/Makefile | 5 +++--
> 5 files changed, 16 insertions(+), 10 deletions(-)
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 31c7044e34e6..3f18aa018a0c 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -1575,6 +1575,7 @@ config CPU_R3000
> depends on SYS_HAS_CPU_R3000
> select CPU_HAS_WB
> select CPU_HAS_LOAD_STORE_LR
> + select CPU_R3K_TLB
> select CPU_SUPPORTS_32BIT_KERNEL
> select CPU_SUPPORTS_HIGHMEM
> help
> @@ -1590,6 +1591,7 @@ config CPU_TX39XX
> depends on SYS_HAS_CPU_TX39XX
> select CPU_SUPPORTS_32BIT_KERNEL
> select CPU_HAS_LOAD_STORE_LR
> + select CPU_R3K_TLB
>
> config CPU_VR41XX
> bool "R41xx"
> @@ -2280,6 +2282,9 @@ config CPU_R2300_FPU
> depends on MIPS_FP_SUPPORT
> default y if CPU_R3000 || CPU_TX39XX
>
> +config CPU_R3K_TLB
> + bool
> +
> config CPU_R4K_FPU
> bool
> depends on MIPS_FP_SUPPORT
> @@ -2287,7 +2292,7 @@ config CPU_R4K_FPU
>
> config CPU_R4K_CACHE_TLB
> bool
> - default y if !(CPU_R3000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
> + default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
>
> config MIPS_MT_SMP
> bool "MIPS MT SMP support (1 TC on each available VPE)"
> diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h
> index e600570789f4..ba967148b016 100644
> --- a/arch/mips/include/asm/pgtable-32.h
> +++ b/arch/mips/include/asm/pgtable-32.h
> @@ -221,7 +221,7 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
> ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
> #define pte_unmap(pte) ((void)(pte))
>
> -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
> +#if defined(CONFIG_CPU_R3K_TLB)
>
> /* Swap entries must have VALID bit cleared. */
> #define __swp_type(x) (((x).val >> 10) & 0x1f)
> @@ -266,6 +266,6 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
>
> #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
>
> -#endif /* defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) */
> +#endif /* defined(CONFIG_CPU_R3K_TLB) */
>
> #endif /* _ASM_PGTABLE_32_H */
> diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
> index c2c1060b43ef..5f1ced8cba07 100644
> --- a/arch/mips/include/asm/pgtable-bits.h
> +++ b/arch/mips/include/asm/pgtable-bits.h
> @@ -82,7 +82,7 @@ enum pgtable_bits {
> _PAGE_SPECIAL_SHIFT,
> };
>
> -#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
> +#elif defined(CONFIG_CPU_R3K_TLB)
>
> /* Page table bits used for r3k systems */
> enum pgtable_bits {
> @@ -151,7 +151,7 @@ enum pgtable_bits {
> #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
> #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
> #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
> -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
> +#if defined(CONFIG_CPU_R3K_TLB)
> # define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT)
> # define _CACHE_MASK _CACHE_UNCACHED
> # define _PFN_SHIFT PAGE_SHIFT
> @@ -209,7 +209,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
> /*
> * Cache attributes
> */
> -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
> +#if defined(CONFIG_CPU_R3K_TLB)
>
> #define _CACHE_CACHABLE_NONCOHERENT 0
> #define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED
> diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
> index d60f47a9088c..4dca733d5076 100644
> --- a/arch/mips/include/asm/pgtable.h
> +++ b/arch/mips/include/asm/pgtable.h
> @@ -199,7 +199,7 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt
> static inline void set_pte(pte_t *ptep, pte_t pteval)
> {
> *ptep = pteval;
> -#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX)
> +#if !defined(CONFIG_CPU_R3K_TLB)
> if (pte_val(pteval) & _PAGE_GLOBAL) {
> pte_t *buddy = ptep_buddy(ptep);
> /*
> @@ -218,7 +218,7 @@ static inline void set_pte(pte_t *ptep, pte_t pteval)
> static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
> {
> htw_stop();
> -#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX)
> +#if !defined(CONFIG_CPU_R3K_TLB)
> /* Preserve global status for the pair */
> if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL)
> set_pte_at(mm, addr, ptep, __pte(_PAGE_GLOBAL));
> diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
> index 949d43eefda1..46f483e952c8 100644
> --- a/arch/mips/mm/Makefile
> +++ b/arch/mips/mm/Makefile
> @@ -28,10 +28,11 @@ obj-$(CONFIG_HIGHMEM) += highmem.o
> obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
> obj-$(CONFIG_DMA_NONCOHERENT) += dma-noncoherent.o
>
> +obj-$(CONFIG_CPU_R3K_TLB) += tlb-r3k.o
> obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o
> -obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o
> +obj-$(CONFIG_CPU_R3000) += c-r3k.o
> obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o
> -obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o
> +obj-$(CONFIG_CPU_TX39XX) += c-tx39.o
> obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o
>
> obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 3/3] MIPS: tlbex: Remove cpu_has_local_ebase
2019-08-31 15:40 ` [PATCH 3/3] MIPS: tlbex: Remove cpu_has_local_ebase Paul Burton
@ 2019-09-01 23:19 ` Philippe Mathieu-Daudé
2019-09-30 4:29 ` Maciej W. Rozycki
1 sibling, 0 replies; 7+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-09-01 23:19 UTC (permalink / raw)
To: Paul Burton, linux-mips; +Cc: Paul Burton
On 8/31/19 5:40 PM, Paul Burton wrote:
> The cpu_has_local_ebase macro is, confusingly, not used to indicate
> whether the EBase register is local to a CPU or not. Instead it
> indicates whether we want to generate the TLB refill exception vector
> each time a CPU is brought online. Doing this makes little sense on any
> system, since we always use the same value for EBase & thus we cannot
> have different TLB refill exception handlers per CPU.
>
> Regenerating the code is not only pointless but also can be actively
> harmful, as commit 8759934e2b6b ("MIPS: Build uasm-generated code only
> once to avoid CPU Hotplug problem") described. That commit introduced
> cpu_has_local_ebase to disable the handler regeneration for Loongson
> machines, but this is by no means a Loongson-specific problem.
>
> Remove cpu_has_local_ebase & simply generate the TLB refill handler once
> during boot, just like the rest of the TLB exception handlers.
>
> Signed-off-by: Paul Burton <paul.burton@mips.com>
> ---
>
> arch/mips/include/asm/cpu-features.h | 3 ---
> arch/mips/include/asm/mach-dec/cpu-feature-overrides.h | 1 -
> .../include/asm/mach-loongson64/cpu-feature-overrides.h | 1 -
> arch/mips/mm/tlbex.c | 9 ++-------
> 4 files changed, 2 insertions(+), 12 deletions(-)
>
> diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
> index 4e2bea8875f5..983a6a7f43a1 100644
> --- a/arch/mips/include/asm/cpu-features.h
> +++ b/arch/mips/include/asm/cpu-features.h
> @@ -243,9 +243,6 @@
> #ifndef cpu_has_pindexed_dcache
> #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
> #endif
> -#ifndef cpu_has_local_ebase
> -#define cpu_has_local_ebase 1
> -#endif
>
> /*
> * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
> diff --git a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
> index 1c11310bc8ad..00beb69bfab9 100644
> --- a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
> +++ b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
> @@ -32,7 +32,6 @@
> #define cpu_has_vtag_icache 0
> #define cpu_has_ic_fills_f_dc 0
> #define cpu_has_pindexed_dcache 0
> -#define cpu_has_local_ebase 0
> #define cpu_icache_snoops_remote_store 1
> #define cpu_has_mips_4 0
> #define cpu_has_mips_5 0
> diff --git a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
> index 581915ce231c..4aca25f2ff06 100644
> --- a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
> +++ b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
> @@ -43,7 +43,6 @@
> #define cpu_has_vint 0
> #define cpu_has_vtag_icache 0
> #define cpu_has_watch 1
> -#define cpu_has_local_ebase 0
>
> #ifdef CONFIG_CPU_LOONGSON3
> #define cpu_has_wsbh 1
> diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
> index 6e3ca9cc5249..e01cb33bfa1a 100644
> --- a/arch/mips/mm/tlbex.c
> +++ b/arch/mips/mm/tlbex.c
> @@ -2609,12 +2609,9 @@ void build_tlb_refill_handler(void)
>
> if (cpu_has_3kex) {
> #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
> - if (cpu_has_local_ebase)
> - build_r3000_tlb_refill_handler();
> if (!run_once) {
> - if (!cpu_has_local_ebase)
> - build_r3000_tlb_refill_handler();
> build_setup_pgd();
> + build_r3000_tlb_refill_handler();
> build_r3000_tlb_load_handler();
> build_r3000_tlb_store_handler();
> build_r3000_tlb_modify_handler();
> @@ -2638,13 +2635,11 @@ void build_tlb_refill_handler(void)
> build_r4000_tlb_modify_handler();
> if (cpu_has_ldpte)
> build_loongson3_tlb_refill_handler();
> - else if (!cpu_has_local_ebase)
> + else
> build_r4000_tlb_refill_handler();
> flush_tlb_handlers();
> run_once++;
> }
> - if (cpu_has_local_ebase)
> - build_r4000_tlb_refill_handler();
> if (cpu_has_xpa)
> config_xpa_params();
> if (cpu_has_htw)
>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/3] MIPS: Select R3k-style TLB in Kconfig
2019-08-31 15:40 [PATCH 1/3] MIPS: Select R3k-style TLB in Kconfig Paul Burton
` (2 preceding siblings ...)
2019-09-01 22:54 ` [PATCH 1/3] MIPS: Select R3k-style TLB in Kconfig Philippe Mathieu-Daudé
@ 2019-09-03 14:45 ` Paul Burton
3 siblings, 0 replies; 7+ messages in thread
From: Paul Burton @ 2019-09-03 14:45 UTC (permalink / raw)
To: Paul Burton; +Cc: linux-mips, Paul Burton, linux-mips
Hello,
Paul Burton wrote:
> Currently areas where we need to determine whether the TLB is R3k-style
> need to check for either of CONFIG_CPU_R3000 || CONFIG_CPU_TX39XX.
>
> Introduce a new CONFIG_CPU_R3K_TLB & select it from both of the above,
> allowing us to simplify checks for R3k-style TLBs by only checking for
> this new Kconfig option.
Series applied to mips-next.
> MIPS: Select R3k-style TLB in Kconfig
> commit 547468293475
> https://git.kernel.org/mips/c/547468293475
>
> Signed-off-by: Paul Burton <paul.burton@mips.com>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> MIPS: tlbex: Simplify r3k check
> commit 54e8d9f07d8a
> https://git.kernel.org/mips/c/54e8d9f07d8a
>
> Signed-off-by: Paul Burton <paul.burton@mips.com>
>
> MIPS: tlbex: Remove cpu_has_local_ebase
> commit 775b089aeffa
> https://git.kernel.org/mips/c/775b089aeffa
>
> Signed-off-by: Paul Burton <paul.burton@mips.com>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Thanks,
Paul
[ This message was auto-generated; if you believe anything is incorrect
then please email paul.burton@mips.com to report it. ]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 3/3] MIPS: tlbex: Remove cpu_has_local_ebase
2019-08-31 15:40 ` [PATCH 3/3] MIPS: tlbex: Remove cpu_has_local_ebase Paul Burton
2019-09-01 23:19 ` Philippe Mathieu-Daudé
@ 2019-09-30 4:29 ` Maciej W. Rozycki
1 sibling, 0 replies; 7+ messages in thread
From: Maciej W. Rozycki @ 2019-09-30 4:29 UTC (permalink / raw)
To: Paul Burton; +Cc: linux-mips, Paul Burton
On Sat, 31 Aug 2019, Paul Burton wrote:
> Remove cpu_has_local_ebase & simply generate the TLB refill handler once
> during boot, just like the rest of the TLB exception handlers.
You may want to update this comment:
/*
* The refill handler is generated per-CPU, multi-node systems
* may have local storage for it. The other handlers are only
* needed once.
*/
accordingly then (assuming you've checked it no longer applies before
making this change).
Maciej
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-09-30 4:29 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-31 15:40 [PATCH 1/3] MIPS: Select R3k-style TLB in Kconfig Paul Burton
2019-08-31 15:40 ` [PATCH 2/3] MIPS: tlbex: Simplify r3k check Paul Burton
2019-08-31 15:40 ` [PATCH 3/3] MIPS: tlbex: Remove cpu_has_local_ebase Paul Burton
2019-09-01 23:19 ` Philippe Mathieu-Daudé
2019-09-30 4:29 ` Maciej W. Rozycki
2019-09-01 22:54 ` [PATCH 1/3] MIPS: Select R3k-style TLB in Kconfig Philippe Mathieu-Daudé
2019-09-03 14:45 ` Paul Burton
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).