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From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: 陈华才 <chenhc@lemote.com>, "Paul Burton" <paul.burton@mips.com>,
	"linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>
Cc: Paul Burton <pburton@wavecomp.com>
Subject: Re: [PATCH] MIPS: Drop Loongson _CACHE_* definitions
Date: Mon, 2 Sep 2019 08:47:01 +0800
Message-ID: <a16c6cef-02fd-ec15-1618-144e77b370f0@flygoat.com> (raw)
In-Reply-To: <tencent_136CE6EE297BEA5D2910DF5B@qq.com>


在 2019/9/1 10:41, 陈华才 写道:
> Hi, Paul,
>
> I found that _CACHE_CACHABLE_COHERENT is removed since 3.18, so this patch need to CC stable?

Hi Huacai

According to stable policy, stable tree won't accept this kind of 
trivial fixes.

Thanks.

--

Jiaxun Yang

> Huacai
>   
> ------------------ Original ------------------
> From:  "Paul Burton"<paul.burton@mips.com>;
> Date:  Sat, Aug 31, 2019 11:41 PM
> To:  "linux-mips@vger.kernel.org"<linux-mips@vger.kernel.org>;
> Cc:  "Paul Burton"<pburton@wavecomp.com>; "Huacai Chen"<chenhc@lemote.com>;
> Subject:  [PATCH] MIPS: Drop Loongson _CACHE_* definitions
>   
> _CACHE_CACHABLE_NONCOHERENT is defined as 3<<_CACHE_SHIFT by default, so
> there's no need to define it as such specifically for Loongson.
>
> _CACHE_CACHABLE_COHERENT is not used anywhere in the kernel, so there's
> no need to define it at all.
>
> Finally the comment found alongside these definitions seems incorrect -
> it suggests that we're defining _CACHE_CACHABLE_NONCOHERENT such that it
> actually provides coherence, but the opposite seems to be true & instead
> the unused _CACHE_CACHABLE_COHERENT is defined as the typically
> incoherent value.
>
> Delete the whole thing, which will have no effect on the compiled code
> anyway.
>
> Signed-off-by: Paul Burton <paul.burton@mips.com>
> Cc: Huacai Chen <chenhc@lemote.com>
> ---
>
>   arch/mips/include/asm/pgtable-bits.h | 7 -------
>   1 file changed, 7 deletions(-)
>
> diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
> index 5f1ced8cba07..409ae01ed7be 100644
> --- a/arch/mips/include/asm/pgtable-bits.h
> +++ b/arch/mips/include/asm/pgtable-bits.h
> @@ -221,13 +221,6 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
>   
>   #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
>   
> -#elif defined(CONFIG_CPU_LOONGSON3)
> -
> -/* Using COHERENT flag for NONCOHERENT doesn't hurt. */
> -
> -#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)  /* LOONGSON       */
> -#define _CACHE_CACHABLE_COHERENT    (3<<_CACHE_SHIFT)  /* LOONGSON-3     */
> -
>   #elif defined(CONFIG_MACH_INGENIC)
>   
>   /* Ingenic uses the WA bit to achieve write-combine memory writes */

  reply index

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-31 15:41 Paul Burton
2019-09-01  2:41 ` 陈华才
2019-09-02  0:47   ` Jiaxun Yang [this message]
2019-09-01 22:53 ` [PATCH] " Philippe Mathieu-Daudé
2019-09-02  0:51 ` Jiaxun Yang
2019-09-03 20:47 ` Paul Burton

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