From: "Maciej W. Rozycki" <macro@imgtec.com>
To: James Hogan <james.hogan@imgtec.com>
Cc: Marcin Nowakowski <marcin.nowakowski@imgtec.com>,
Ralf Baechle <ralf@linux-mips.org>, <linux-mips@linux-mips.org>
Subject: Re: [PATCH v2 1/2] MIPS: ptrace: disallow setting watchpoints in kernel address space
Date: Wed, 25 Jan 2017 14:39:36 +0000 [thread overview]
Message-ID: <alpine.DEB.2.00.1701251427190.13564@tp.orcam.me.uk> (raw)
In-Reply-To: <alpine.DEB.2.00.1701242229480.13564@tp.orcam.me.uk>
On Tue, 24 Jan 2017, Maciej W. Rozycki wrote:
> However if we can prove that we won't need the IP[1:0] bits in scenarios
> that involve a TLB refill, then we could just quickly do a short sequence,
> say:
>
> lui $k0, 1 << 23
Umm, thinko here, this obviously has to be:
li $k0, 1 << 23
or alternatively:
lui $k0, 1 << (23 - 16)
(GAS will emit a single LUI instruction in either case).
> mtc0 $13, $k0
> eret
>
> Otherwise we'll have to do a full RMW sequence; fortunately a single INS
> from $0 will do here again to clear CP0.Cause.WP and keep the remaining
> bits. Maybe we could do just the same in the regular exception epilogue
> to avoid the dependency on a hazard (and consequently an issue with QEMU).
Of course a similar hazard is still there, so the same precautions apply.
Also I think we do need to clear CP0.Cause.WP in all cases before ERET,
including the various exception fast paths, such as in the TLBL/TLBS/TLBM
handlers, which also means we don't have to fiddle with CP0.EntryHi.ASID
in handler execution paths that run at EXL entirely to completion.
Maciej
WARNING: multiple messages have this Message-ID (diff)
From: "Maciej W. Rozycki" <macro@imgtec.com>
To: James Hogan <james.hogan@imgtec.com>
Cc: Marcin Nowakowski <marcin.nowakowski@imgtec.com>,
Ralf Baechle <ralf@linux-mips.org>,
linux-mips@linux-mips.org
Subject: Re: [PATCH v2 1/2] MIPS: ptrace: disallow setting watchpoints in kernel address space
Date: Wed, 25 Jan 2017 14:39:36 +0000 [thread overview]
Message-ID: <alpine.DEB.2.00.1701251427190.13564@tp.orcam.me.uk> (raw)
Message-ID: <20170125143936.34Kb6doWjoxXON8MgMWI6241EO2I27_1ZIGYa1C8Pfs@z> (raw)
In-Reply-To: <alpine.DEB.2.00.1701242229480.13564@tp.orcam.me.uk>
On Tue, 24 Jan 2017, Maciej W. Rozycki wrote:
> However if we can prove that we won't need the IP[1:0] bits in scenarios
> that involve a TLB refill, then we could just quickly do a short sequence,
> say:
>
> lui $k0, 1 << 23
Umm, thinko here, this obviously has to be:
li $k0, 1 << 23
or alternatively:
lui $k0, 1 << (23 - 16)
(GAS will emit a single LUI instruction in either case).
> mtc0 $13, $k0
> eret
>
> Otherwise we'll have to do a full RMW sequence; fortunately a single INS
> from $0 will do here again to clear CP0.Cause.WP and keep the remaining
> bits. Maybe we could do just the same in the regular exception epilogue
> to avoid the dependency on a hazard (and consequently an issue with QEMU).
Of course a similar hazard is still there, so the same precautions apply.
Also I think we do need to clear CP0.Cause.WP in all cases before ERET,
including the various exception fast paths, such as in the TLBL/TLBS/TLBM
handlers, which also means we don't have to fiddle with CP0.EntryHi.ASID
in handler execution paths that run at EXL entirely to completion.
Maciej
next prev parent reply other threads:[~2017-01-25 14:39 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-23 9:18 [PATCH v2 1/2] MIPS: ptrace: disallow setting watchpoints in kernel address space Marcin Nowakowski
2017-01-23 9:18 ` Marcin Nowakowski
2017-01-23 9:18 ` [PATCH v2 2/2] MIPS: ptrace: disable watchpoints if hit in kernel mode Marcin Nowakowski
2017-01-23 9:18 ` Marcin Nowakowski
2017-01-24 17:09 ` [PATCH v2 1/2] MIPS: ptrace: disallow setting watchpoints in kernel address space Maciej W. Rozycki
2017-01-24 17:09 ` Maciej W. Rozycki
2017-01-24 18:54 ` James Hogan
2017-01-24 18:54 ` James Hogan
2017-01-24 20:52 ` Maciej W. Rozycki
2017-01-24 20:52 ` Maciej W. Rozycki
2017-01-24 22:05 ` James Hogan
2017-01-24 22:05 ` James Hogan
2017-01-24 23:07 ` Maciej W. Rozycki
2017-01-24 23:07 ` Maciej W. Rozycki
2017-01-25 14:39 ` Maciej W. Rozycki [this message]
2017-01-25 14:39 ` Maciej W. Rozycki
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