* Re: [RFC PATCH 0/2] MIPS: Loongson: ExtCC clocksource support
@ 2019-02-25 5:28 Jiaxun Yang
2019-02-25 6:05 ` Wang Xuerui
0 siblings, 1 reply; 3+ messages in thread
From: Jiaxun Yang @ 2019-02-25 5:28 UTC (permalink / raw)
To: kernel
Cc: linux-mips, Paul Burton, linux-mips, James Hogan, Ralf Baechle,
Wang Xuerui, Huacai Chen
2019年2月24日 下午5:36于 kernel@xen0n.name写道:
>
> From: Wang Xuerui <wangxuerui@qiniu.com>
>
> Hi,
>
> This is my WIP patchset to add support for using the on-chip ExtCC
> (external counter) register as clocksource, to boost the real-time
> performance on Loongson platform. I'm posting this to solicit comments
> and get some of the unresolved questions answered.
Hi Xuerui
Thanks a lot for your works, however, the ExtCC can be influenced by the frequency of CPU core, and we have cpufreq working on Loongson-3 processors, so you should mark it conflict with cpufreq driver.
And as far as I know, ExtCC is even not synchronous between different cores.
I'd prefer to use gs3_HPT(0x3ff00408) register to implement this feather. Also it can be accessed from all the nodes, and the clock comes from "node clock" which will not effected by core frequency.
>
> * I don't have access to multi-socket ccNUMA Loongson boards. The code
> most certainly doesn't work on such hardware, so either someone with
> expertise would teach me how to do this, or get this done on their
> own.
> * I'm not sure of the pipeline behavior of the rdhwr instruction used.
> The current implementation has a sync (roughly the x86 way), and I'm
> not sure if it can be safely omitted, or even moved into the delay
> slot on return.
> * Clock skew can be a concern, but it seems there's no generic mechanism
> for clocksource calibration. The x86 code has one supporting PIT/HPET-
> based calibration, but that code never got extracted to common
> framework.
> * The VDSO performance seems very bad comparing to x86, even after
> adjusting for the cycle frequency difference. But I haven't thoroughly
> profiled this and perhaps won't have enough spare time for doing so
> (kernel work isn't part of my day job). So maybe someone could
> provide some hints in this area?
>
> Can only come up with so many points for now; I'll add if more ideas
> turn up.
>
> P.S. I have to change to my personal address for outgoing mails; my
> work address is hosted on QQ Enterprise Mail, which most certainly is
> blocked altogether by linux-mips.org.
>
> Wang Xuerui (2):
> MIPS: Loongson: add extcc clocksource
> MIPS: VDSO: support extcc-based timekeeping
>
> arch/mips/include/asm/clocksource.h | 1 +
> arch/mips/include/asm/mach-loongson64/extcc.h | 26 +++++++++
> arch/mips/loongson64/Kconfig | 13 +++++
> arch/mips/loongson64/common/Makefile | 5 ++
> arch/mips/loongson64/common/extcc.c | 54 +++++++++++++++++++
> arch/mips/loongson64/common/time.c | 7 +++
> arch/mips/vdso/gettimeofday.c | 8 +++
> 7 files changed, 114 insertions(+)
> create mode 100644 arch/mips/include/asm/mach-loongson64/extcc.h
> create mode 100644 arch/mips/loongson64/common/extcc.c
>
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [RFC PATCH 0/2] MIPS: Loongson: ExtCC clocksource support
2019-02-25 5:28 [RFC PATCH 0/2] MIPS: Loongson: ExtCC clocksource support Jiaxun Yang
@ 2019-02-25 6:05 ` Wang Xuerui
0 siblings, 0 replies; 3+ messages in thread
From: Wang Xuerui @ 2019-02-25 6:05 UTC (permalink / raw)
To: Jiaxun Yang
Cc: linux-mips, Paul Burton, linux-mips, James Hogan, Ralf Baechle,
Wang Xuerui, Huacai Chen
On 2019/2/25 13:28, Jiaxun Yang wrote:
>
> 2019年2月24日 下午5:36于 kernel@xen0n.name写道:
>> From: Wang Xuerui <wangxuerui@qiniu.com>
>>
>> Hi,
>>
>> This is my WIP patchset to add support for using the on-chip ExtCC
>> (external counter) register as clocksource, to boost the real-time
>> performance on Loongson platform. I'm posting this to solicit comments
>> and get some of the unresolved questions answered.
> Hi Xuerui
>
> Thanks a lot for your works, however, the ExtCC can be influenced by the frequency of CPU core, and we have cpufreq working on Loongson-3 processors, so you should mark it conflict with cpufreq driver.
>
> And as far as I know, ExtCC is even not synchronous between different cores.
>
> I'd prefer to use gs3_HPT(0x3ff00408) register to implement this feather. Also it can be accessed from all the nodes, and the clock comes from "node clock" which will not effected by core frequency.
This is interesting, but according to Section 2.4.3 of the 3A3000 User
Manual (Vol. 2), the ExtCC register is explicitly stated to be
core-frequency-independent.
Maybe you confused ExtCC with Count (rdhwr with rd=2), of which update
freq does vary with core freq?
^ permalink raw reply [flat|nested] 3+ messages in thread
* [RFC PATCH 0/2] MIPS: Loongson: ExtCC clocksource support
@ 2019-02-24 9:36 kernel
0 siblings, 0 replies; 3+ messages in thread
From: kernel @ 2019-02-24 9:36 UTC (permalink / raw)
To: linux-mips
Cc: Wang Xuerui, Huacai Chen, Jiaxun Yang, James Hogan, Paul Burton,
Ralf Baechle, linux-mips
From: Wang Xuerui <wangxuerui@qiniu.com>
Hi,
This is my WIP patchset to add support for using the on-chip ExtCC
(external counter) register as clocksource, to boost the real-time
performance on Loongson platform. I'm posting this to solicit comments
and get some of the unresolved questions answered.
* I don't have access to multi-socket ccNUMA Loongson boards. The code
most certainly doesn't work on such hardware, so either someone with
expertise would teach me how to do this, or get this done on their
own.
* I'm not sure of the pipeline behavior of the rdhwr instruction used.
The current implementation has a sync (roughly the x86 way), and I'm
not sure if it can be safely omitted, or even moved into the delay
slot on return.
* Clock skew can be a concern, but it seems there's no generic mechanism
for clocksource calibration. The x86 code has one supporting PIT/HPET-
based calibration, but that code never got extracted to common
framework.
* The VDSO performance seems very bad comparing to x86, even after
adjusting for the cycle frequency difference. But I haven't thoroughly
profiled this and perhaps won't have enough spare time for doing so
(kernel work isn't part of my day job). So maybe someone could
provide some hints in this area?
Can only come up with so many points for now; I'll add if more ideas
turn up.
P.S. I have to change to my personal address for outgoing mails; my
work address is hosted on QQ Enterprise Mail, which most certainly is
blocked altogether by linux-mips.org.
Wang Xuerui (2):
MIPS: Loongson: add extcc clocksource
MIPS: VDSO: support extcc-based timekeeping
arch/mips/include/asm/clocksource.h | 1 +
arch/mips/include/asm/mach-loongson64/extcc.h | 26 +++++++++
arch/mips/loongson64/Kconfig | 13 +++++
arch/mips/loongson64/common/Makefile | 5 ++
arch/mips/loongson64/common/extcc.c | 54 +++++++++++++++++++
arch/mips/loongson64/common/time.c | 7 +++
arch/mips/vdso/gettimeofday.c | 8 +++
7 files changed, 114 insertions(+)
create mode 100644 arch/mips/include/asm/mach-loongson64/extcc.h
create mode 100644 arch/mips/loongson64/common/extcc.c
--
2.20.1
^ permalink raw reply [flat|nested] 3+ messages in thread
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