From: Zhenyu Ye <yezhenyu2@huawei.com>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: <peterz@infradead.org>, <mark.rutland@arm.com>, <will@kernel.org>,
<aneesh.kumar@linux.ibm.com>, <akpm@linux-foundation.org>,
<npiggin@gmail.com>, <arnd@arndb.de>, <rostedt@goodmis.org>,
<maz@kernel.org>, <suzuki.poulose@arm.com>, <tglx@linutronix.de>,
<yuzhao@google.com>, <Dave.Martin@arm.com>,
<steven.price@arm.com>, <broonie@kernel.org>,
<guohanjun@huawei.com>, <linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-arch@vger.kernel.org>,
<linux-mm@kvack.org>, <arm@kernel.org>, <xiexiangyou@huawei.com>,
<prime.zeng@hisilicon.com>, <zhangshaokun@hisilicon.com>,
<kuhn.chenqun@huawei.com>
Subject: Re: [PATCH v2 2/6] arm64: Add level-hinted TLB invalidation helper
Date: Mon, 25 May 2020 14:54:51 +0800 [thread overview]
Message-ID: <3852291c-37cf-39b6-564d-8b4f50f9d86e@huawei.com> (raw)
In-Reply-To: <20200522155017.GG26492@gaia>
On 2020/5/22 23:50, Catalin Marinas wrote:
> On Thu, Apr 23, 2020 at 09:56:52PM +0800, Zhenyu Ye wrote:
>> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
>> index bc3949064725..5f9f189bc6d2 100644
>> --- a/arch/arm64/include/asm/tlbflush.h
>> +++ b/arch/arm64/include/asm/tlbflush.h
>> @@ -10,6 +10,7 @@
>>
>> #ifndef __ASSEMBLY__
>>
>> +#include <linux/bitfield.h>
>> #include <linux/mm_types.h>
>> #include <linux/sched.h>
>> #include <asm/cputype.h>
>> @@ -59,6 +60,35 @@
>> __ta; \
>> })
>>
>> +#define TLBI_TTL_MASK GENMASK_ULL(47, 44)
>> +
>> +#define __tlbi_level(op, addr, level) \
>> + do { \
>
> Nitpick: move "do {" on the same line as __tlbi_level() to reduce the
> indentation levels of the whole block.
>
> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
>
OK.
next prev parent reply other threads:[~2020-05-25 6:55 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-23 13:56 [PATCH v2 0/6] arm64: tlb: add support for TTL feature Zhenyu Ye
2020-04-23 13:56 ` [PATCH v2 1/6] arm64: Detect the ARMv8.4 " Zhenyu Ye
2020-05-22 15:50 ` Catalin Marinas
2020-04-23 13:56 ` [PATCH v2 2/6] arm64: Add level-hinted TLB invalidation helper Zhenyu Ye
2020-05-22 15:50 ` Catalin Marinas
2020-05-25 6:54 ` Zhenyu Ye [this message]
2020-04-23 13:56 ` [PATCH v2 3/6] arm64: Add tlbi_user_level " Zhenyu Ye
2020-05-22 15:49 ` Catalin Marinas
2020-05-25 6:57 ` Zhenyu Ye
2020-04-23 13:56 ` [PATCH v2 4/6] tlb: mmu_gather: add tlb_flush_*_range APIs Zhenyu Ye
2020-05-22 15:50 ` Catalin Marinas
2020-04-23 13:56 ` [PATCH v2 5/6] mm: tlb: Provide flush_*_tlb_range wrappers Zhenyu Ye
2020-05-22 15:42 ` Catalin Marinas
2020-05-25 7:19 ` Zhenyu Ye
2020-05-26 14:52 ` Catalin Marinas
2020-05-30 10:24 ` Zhenyu Ye
2020-06-01 11:56 ` Catalin Marinas
2020-06-01 13:36 ` Zhenyu Ye
2020-04-23 13:56 ` [PATCH v2 6/6] arm64: tlb: Set the TTL field in flush_tlb_range Zhenyu Ye
2020-05-26 14:56 ` Catalin Marinas
2020-05-11 12:41 ` [PATCH v2 0/6] arm64: tlb: add support for TTL feature Zhenyu Ye
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