* [PATCH v3 0/3] TLB flush counters
@ 2019-04-29 21:27 Atish Patra
2019-04-29 21:27 ` [PATCH v3 1/3] x86: Move DEBUG_TLBFLUSH option Atish Patra
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Atish Patra @ 2019-04-29 21:27 UTC (permalink / raw)
To: linux-kernel
Cc: Atish Patra, Albert Ou, Andrew Morton, Anup Patel,
Borislav Petkov, Changbin Du, Gary Guo, H. Peter Anvin,
Ingo Molnar, Kees Cook, linux-mm, linux-riscv,
Luc Van Oostenryck, Palmer Dabbelt, Thomas Gleixner,
Vlastimil Babka, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
Christoph Hellwig
The RISC-V patch (2/3) is based on Gary's TLB flush patch series
https://patchwork.kernel.org/project/linux-riscv/list/?series=97315
The x86 kconfig fix patch(1/3) can be applied separately.
Chnages from v2->v3:
1. Fixed typos and commit text formatting.
Changes from v1->v2:
1. Move the arch specific config option to a common one as it touches
generic code.
2. Introduced another config that architectures can select to enable
tlbflush option.
Atish Patra (3):
x86: Move DEBUG_TLBFLUSH option.
RISC-V: Enable TLBFLUSH counters for debug kernel.
RISC-V: Update tlb flush counters
arch/riscv/Kconfig | 1 +
arch/riscv/include/asm/tlbflush.h | 5 +++++
arch/riscv/mm/tlbflush.c | 12 ++++++++++++
arch/x86/Kconfig | 1 +
arch/x86/Kconfig.debug | 19 -------------------
mm/Kconfig.debug | 13 +++++++++++++
6 files changed, 32 insertions(+), 19 deletions(-)
--
2.21.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v3 1/3] x86: Move DEBUG_TLBFLUSH option.
2019-04-29 21:27 [PATCH v3 0/3] TLB flush counters Atish Patra
@ 2019-04-29 21:27 ` Atish Patra
2019-06-28 5:47 ` Paul Walmsley
2019-04-29 21:27 ` [PATCH v3 2/3] RISC-V: Enable TLBFLUSH counters for debug kernel Atish Patra
2019-04-29 21:27 ` [PATCH v3 3/3] RISC-V: Update tlb flush counters Atish Patra
2 siblings, 1 reply; 7+ messages in thread
From: Atish Patra @ 2019-04-29 21:27 UTC (permalink / raw)
To: linux-kernel
Cc: Atish Patra, Albert Ou, Andrew Morton, Anup Patel,
Borislav Petkov, Changbin Du, Gary Guo, H. Peter Anvin,
Ingo Molnar, Kees Cook, linux-mm, linux-riscv,
Luc Van Oostenryck, Palmer Dabbelt, Thomas Gleixner,
Vlastimil Babka, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
Christoph Hellwig
CONFIG_DEBUG_TLBFLUSH was added in
'commit 3df3212f9722 ("x86/tlb: add tlb_flushall_shift knob into debugfs")'
to support tlb_flushall_shift knob. The knob was removed in
'commit e9f4e0a9fe27 ("x86/mm: Rip out complicated, out-of-date, buggy
TLB flushing")'.
However, the debug option was never removed from Kconfig. It was reused
in commit
'9824cf9753ec ("mm: vmstats: tlb flush counters")'
but the commit text was never updated accordingly.
Update the Kconfig option description as per its current usage.
Take this opportunity to make this kconfig option a common option as it
touches the common vmstat code. Introduce another arch specific config
HAVE_ARCH_DEBUG_TLBFLUSH that can be selected to enable this config.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
arch/x86/Kconfig | 1 +
arch/x86/Kconfig.debug | 19 -------------------
mm/Kconfig.debug | 13 +++++++++++++
3 files changed, 14 insertions(+), 19 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 62fc3fda1a05..4c59f59e9491 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -132,6 +132,7 @@ config X86
select HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD if X86_64
select HAVE_ARCH_VMAP_STACK if X86_64
select HAVE_ARCH_WITHIN_STACK_FRAMES
+ select HAVE_ARCH_DEBUG_TLBFLUSH if DEBUG_KERNEL
select HAVE_CMPXCHG_DOUBLE
select HAVE_CMPXCHG_LOCAL
select HAVE_CONTEXT_TRACKING if X86_64
diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug
index 15d0fbe27872..0c8f9931e901 100644
--- a/arch/x86/Kconfig.debug
+++ b/arch/x86/Kconfig.debug
@@ -124,25 +124,6 @@ config DOUBLEFAULT
option saves about 4k and might cause you much additional grey
hair.
-config DEBUG_TLBFLUSH
- bool "Set upper limit of TLB entries to flush one-by-one"
- depends on DEBUG_KERNEL
- ---help---
-
- X86-only for now.
-
- This option allows the user to tune the amount of TLB entries the
- kernel flushes one-by-one instead of doing a full TLB flush. In
- certain situations, the former is cheaper. This is controlled by the
- tlb_flushall_shift knob under /sys/kernel/debug/x86. If you set it
- to -1, the code flushes the whole TLB unconditionally. Otherwise,
- for positive values of it, the kernel will use single TLB entry
- invalidating instructions according to the following formula:
-
- flush_entries <= active_tlb_entries / 2^tlb_flushall_shift
-
- If in doubt, say "N".
-
config IOMMU_DEBUG
bool "Enable IOMMU debugging"
depends on GART_IOMMU && DEBUG_KERNEL
diff --git a/mm/Kconfig.debug b/mm/Kconfig.debug
index e3df921208c0..e8622b26f0c2 100644
--- a/mm/Kconfig.debug
+++ b/mm/Kconfig.debug
@@ -111,3 +111,16 @@ config DEBUG_RODATA_TEST
depends on STRICT_KERNEL_RWX
---help---
This option enables a testcase for the setting rodata read-only.
+
+config HAVE_ARCH_DEBUG_TLBFLUSH
+ bool
+ depends on DEBUG_KERNEL
+
+config DEBUG_TLBFLUSH
+ bool "Save tlb flush statistics to vmstat"
+ depends on HAVE_ARCH_DEBUG_TLBFLUSH
+ help
+
+ Add tlbflush statistics to vmstat. It is really helpful understand tlbflush
+ performance and behavior. It should be enabled only for debugging purpose
+ by individual architectures explicitly by selecting HAVE_ARCH_DEBUG_TLBFLUSH.
--
2.21.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v3 2/3] RISC-V: Enable TLBFLUSH counters for debug kernel.
2019-04-29 21:27 [PATCH v3 0/3] TLB flush counters Atish Patra
2019-04-29 21:27 ` [PATCH v3 1/3] x86: Move DEBUG_TLBFLUSH option Atish Patra
@ 2019-04-29 21:27 ` Atish Patra
2019-04-29 21:27 ` [PATCH v3 3/3] RISC-V: Update tlb flush counters Atish Patra
2 siblings, 0 replies; 7+ messages in thread
From: Atish Patra @ 2019-04-29 21:27 UTC (permalink / raw)
To: linux-kernel
Cc: Atish Patra, Albert Ou, Andrew Morton, Anup Patel,
Borislav Petkov, Changbin Du, Gary Guo, H. Peter Anvin,
Ingo Molnar, Kees Cook, linux-mm, linux-riscv,
Luc Van Oostenryck, Palmer Dabbelt, Thomas Gleixner,
Vlastimil Babka, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
Christoph Hellwig
The TLB flush counters under vmstat seems to be very helpful while
debugging TLB flush performance in RISC-V.
Add the Kconfig option only for debug kernels.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index eb56c82d8aa1..c1ee876d1e7f 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -49,6 +49,7 @@ config RISCV
select GENERIC_IRQ_MULTI_HANDLER
select ARCH_HAS_PTE_SPECIAL
select HAVE_EBPF_JIT if 64BIT
+ select HAVE_ARCH_DEBUG_TLBFLUSH if DEBUG_KERNEL
config MMU
def_bool y
--
2.21.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v3 3/3] RISC-V: Update tlb flush counters
2019-04-29 21:27 [PATCH v3 0/3] TLB flush counters Atish Patra
2019-04-29 21:27 ` [PATCH v3 1/3] x86: Move DEBUG_TLBFLUSH option Atish Patra
2019-04-29 21:27 ` [PATCH v3 2/3] RISC-V: Enable TLBFLUSH counters for debug kernel Atish Patra
@ 2019-04-29 21:27 ` Atish Patra
2019-06-28 5:47 ` Paul Walmsley
2 siblings, 1 reply; 7+ messages in thread
From: Atish Patra @ 2019-04-29 21:27 UTC (permalink / raw)
To: linux-kernel
Cc: Atish Patra, Albert Ou, Andrew Morton, Anup Patel,
Borislav Petkov, Changbin Du, Gary Guo, H. Peter Anvin,
Ingo Molnar, Kees Cook, linux-mm, linux-riscv,
Luc Van Oostenryck, Palmer Dabbelt, Thomas Gleixner,
Vlastimil Babka, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
Christoph Hellwig
The TLB flush counters under vmstat seems to be very helpful while
debugging TLB flush performance in RISC-V.
Update the counters in every TLB flush methods respectively.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
arch/riscv/include/asm/tlbflush.h | 5 +++++
arch/riscv/mm/tlbflush.c | 12 ++++++++++++
2 files changed, 17 insertions(+)
diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h
index 29a780ca232a..19779a083f52 100644
--- a/arch/riscv/include/asm/tlbflush.h
+++ b/arch/riscv/include/asm/tlbflush.h
@@ -9,6 +9,7 @@
#define _ASM_RISCV_TLBFLUSH_H
#include <linux/mm_types.h>
+#include <linux/vmstat.h>
/*
* Flush entire local TLB. 'sfence.vma' implicitly fences with the instruction
@@ -16,11 +17,13 @@
*/
static inline void local_flush_tlb_all(void)
{
+ count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
__asm__ __volatile__ ("sfence.vma" : : : "memory");
}
static inline void local_flush_tlb_mm(struct mm_struct *mm)
{
+ count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
/* Flush ASID 0 so that global mappings are not affected */
__asm__ __volatile__ ("sfence.vma x0, %0" : : "r" (0) : "memory");
}
@@ -28,6 +31,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
static inline void local_flush_tlb_page(struct vm_area_struct *vma,
unsigned long addr)
{
+ count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
__asm__ __volatile__ ("sfence.vma %0, %1"
: : "r" (addr), "r" (0)
: "memory");
@@ -35,6 +39,7 @@ static inline void local_flush_tlb_page(struct vm_area_struct *vma,
static inline void local_flush_tlb_kernel_page(unsigned long addr)
{
+ count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
__asm__ __volatile__ ("sfence.vma %0" : : "r" (addr) : "memory");
}
diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
index ceee76f14a0a..8072d7da32bb 100644
--- a/arch/riscv/mm/tlbflush.c
+++ b/arch/riscv/mm/tlbflush.c
@@ -4,6 +4,8 @@
*/
#include <linux/mm.h>
+#include <linux/vmstat.h>
+#include <linux/cpumask.h>
#include <asm/sbi.h>
#define SFENCE_VMA_FLUSH_ALL ((unsigned long) -1)
@@ -110,6 +112,7 @@ static void ipi_remote_sfence_vma(void *info)
unsigned long size = data->size;
unsigned long i;
+ count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
if (size == SFENCE_VMA_FLUSH_ALL) {
local_flush_tlb_all();
}
@@ -129,6 +132,8 @@ static void ipi_remote_sfence_vma_asid(void *info)
unsigned long size = data->size;
unsigned long i;
+ count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
+ /* Flush entire MM context */
if (size == SFENCE_VMA_FLUSH_ALL) {
__asm__ __volatile__ ("sfence.vma x0, %0"
: : "r" (asid)
@@ -158,6 +163,13 @@ static void remote_sfence_vma(unsigned long start, unsigned long size)
static void remote_sfence_vma_asid(cpumask_t *mask, unsigned long start,
unsigned long size, unsigned long asid)
{
+ int cpuid = smp_processor_id();
+
+ if (cpumask_equal(mask, cpumask_of(cpuid)))
+ count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
+ else
+ count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
+
if (tlbi_ipi) {
struct tlbi info = {
.start = start,
--
2.21.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v3 3/3] RISC-V: Update tlb flush counters
2019-04-29 21:27 ` [PATCH v3 3/3] RISC-V: Update tlb flush counters Atish Patra
@ 2019-06-28 5:47 ` Paul Walmsley
2019-06-28 16:37 ` Atish Patra
0 siblings, 1 reply; 7+ messages in thread
From: Paul Walmsley @ 2019-06-28 5:47 UTC (permalink / raw)
To: Atish Patra
Cc: linux-kernel, Christoph Hellwig, Albert Ou, Thomas Gleixner,
Kees Cook, Changbin Du, Anup Patel, Palmer Dabbelt,
maintainer:X86 ARCHITECTURE 32-BIT AND 64-BIT, linux-mm,
Ingo Molnar, Borislav Petkov, Vlastimil Babka, Gary Guo,
H. Peter Anvin, Andrew Morton, linux-riscv, Luc Van Oostenryck
On Mon, 29 Apr 2019, Atish Patra wrote:
> The TLB flush counters under vmstat seems to be very helpful while
> debugging TLB flush performance in RISC-V.
>
> Update the counters in every TLB flush methods respectively.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
This one doesn't apply any longer. Care to update and repost?
- Paul
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 1/3] x86: Move DEBUG_TLBFLUSH option.
2019-04-29 21:27 ` [PATCH v3 1/3] x86: Move DEBUG_TLBFLUSH option Atish Patra
@ 2019-06-28 5:47 ` Paul Walmsley
0 siblings, 0 replies; 7+ messages in thread
From: Paul Walmsley @ 2019-06-28 5:47 UTC (permalink / raw)
To: Atish Patra, Ingo Molnar
Cc: linux-kernel, Christoph Hellwig, Albert Ou, Thomas Gleixner,
Kees Cook, Changbin Du, Anup Patel, Palmer Dabbelt,
maintainer:X86 ARCHITECTURE 32-BIT AND 64-BIT, linux-mm,
Borislav Petkov, Vlastimil Babka, Gary Guo, H. Peter Anvin,
Andrew Morton, linux-riscv, Luc Van Oostenryck
On Mon, 29 Apr 2019, Atish Patra wrote:
> CONFIG_DEBUG_TLBFLUSH was added in
>
> 'commit 3df3212f9722 ("x86/tlb: add tlb_flushall_shift knob into debugfs")'
> to support tlb_flushall_shift knob. The knob was removed in
>
> 'commit e9f4e0a9fe27 ("x86/mm: Rip out complicated, out-of-date, buggy
> TLB flushing")'.
> However, the debug option was never removed from Kconfig. It was reused
> in commit
>
> '9824cf9753ec ("mm: vmstats: tlb flush counters")'
> but the commit text was never updated accordingly.
>
> Update the Kconfig option description as per its current usage.
>
> Take this opportunity to make this kconfig option a common option as it
> touches the common vmstat code. Introduce another arch specific config
> HAVE_ARCH_DEBUG_TLBFLUSH that can be selected to enable this config.
Looks like this one still needs to be merged or acked by one of the x86
maintainers?
- Paul
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 3/3] RISC-V: Update tlb flush counters
2019-06-28 5:47 ` Paul Walmsley
@ 2019-06-28 16:37 ` Atish Patra
0 siblings, 0 replies; 7+ messages in thread
From: Atish Patra @ 2019-06-28 16:37 UTC (permalink / raw)
To: Paul Walmsley
Cc: linux-kernel, Christoph Hellwig, Albert Ou, Thomas Gleixner,
Kees Cook, Changbin Du, Anup Patel, Palmer Dabbelt,
maintainer:X86 ARCHITECTURE 32-BIT AND 64-BIT, linux-mm,
Ingo Molnar, Borislav Petkov, Vlastimil Babka, Gary Guo,
H. Peter Anvin, Andrew Morton, linux-riscv, Luc Van Oostenryck
On 6/27/19 10:47 PM, Paul Walmsley wrote:
> On Mon, 29 Apr 2019, Atish Patra wrote:
>
>> The TLB flush counters under vmstat seems to be very helpful while
>> debugging TLB flush performance in RISC-V.
>>
>> Update the counters in every TLB flush methods respectively.
>>
>> Signed-off-by: Atish Patra <atish.patra@wdc.com>
>
> This one doesn't apply any longer. Care to update and repost?
>
>
> - Paul
>
Yeah. The baseline patch (Gary's patch) was not accepted. I will rebase
it on top of master and resend.
--
Regards,
Atish
^ permalink raw reply [flat|nested] 7+ messages in thread
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2019-04-29 21:27 [PATCH v3 0/3] TLB flush counters Atish Patra
2019-04-29 21:27 ` [PATCH v3 1/3] x86: Move DEBUG_TLBFLUSH option Atish Patra
2019-06-28 5:47 ` Paul Walmsley
2019-04-29 21:27 ` [PATCH v3 2/3] RISC-V: Enable TLBFLUSH counters for debug kernel Atish Patra
2019-04-29 21:27 ` [PATCH v3 3/3] RISC-V: Update tlb flush counters Atish Patra
2019-06-28 5:47 ` Paul Walmsley
2019-06-28 16:37 ` Atish Patra
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