[PATCH 0/5] MTK NAND driver improvements and fixes

[PATCH 0/5] MTK NAND driver improvements and fixes

[Xiaolei Li]

Hello Maintainers,

The following patch set is used to do MTK NAND driver improvements and
bug fixes, include:
* Fix low level time calculation of read/write cycle to meet tRC_min
  and tWC_min requirements.
* Refine RE# pulse width calculation and data sampling to improve read
  performance.
* Add CS validity check.
* Fix oob buffer pointer wrongly setting and empty page threshold setting.

Changes relative to:
--------------------

tree    : git://git.infradead.org/linux-mtd.git
branch  : master
commit  :
        'commit 3e35730dd754 ("mtd: powernv_flash: Fix device
         registration error")

Tests:
------

* ubifs and jffs2 are validated on NAND device MT29F16G08ADBCA by
  'dd' command.
* all drivers/mtd/tests/* pass.
* speed test:
  eraseblock write speed is 11087 KiB/s
  eraseblock read speed is 19986 KiB/s
  page write speed is 10689 KiB/s
  page read speed is 18724 KiB/s
  2 page write speed is 10611 KiB/s
  2 page read speed is 18713 KiB/s
  erase speed is 103696 KiB/s
  2x multi-block erase speed is 354248 KiB/s
  4x multi-block erase speed is 350459 KiB/s
  8x multi-block erase speed is 356173 KiB/s
  16x multi-block erase speed is 356173 KiB/s
  32x multi-block erase speed is 358120 KiB/s
  64x multi-block erase speed is 356173 KiB/s

Xiaolei Li (5):
  mtd: rawnand: mtk: Correct low level time calculation of r/w cycle
  mtd: rawnand: mtk: Improve data sampling timing for read cycle
  mtd: rawnand: mtk: Add validity check for CE# pin setting
  mtd: rawnand: mtk: Fix wrongly assigned oob buffer pointer issue
  mtd: rawnand: mtk: Setup empty page threshold correctly

 drivers/mtd/nand/raw/mtk_nand.c | 73 ++++++++++++++++++++++++++-------
 1 file changed, 59 insertions(+), 14 deletions(-)

--
2.18.0



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[PATCH 1/5] mtd: rawnand: mtk: Correct low level time calculation of r/w cycle

[Xiaolei Li]

At present, the flow of calculating AC timing of read/write cycle in SDR
mode is that:
At first, calculate high hold time which is valid for both read and write
cycle using the max value between tREH_min and tWH_min.
Secondly, calculate WE# pulse width using tWP_min.
Thridly, calculate RE# pulse width using the bigger one between tREA_max
and tRP_min.

But NAND SPEC shows that Controller should also meet write/read cycle time.
That is write cycle time should be more than tWC_min and read cycle should
be more than tRC_min. Obviously, we do not achieve that now.

This patch corrects the low level time calculation to meet minimum
read/write cycle time required. After getting the high hold time, WE# low
level time will be promised to meet tWP_min and tWC_min requirement,
and RE# low level time will be promised to meet tREA_max, tRP_min and
tRC_min requirement.

Fixes: 93db446a424c ("mtd: nand: move raw NAND related code to the raw/ subdir")
Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
---
 drivers/mtd/nand/raw/mtk_nand.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
index b6b4602f5132..dd855f860a4b 100644
--- a/drivers/mtd/nand/raw/mtk_nand.c
+++ b/drivers/mtd/nand/raw/mtk_nand.c
@@ -508,7 +508,7 @@ static int mtk_nfc_setup_data_interface(struct nand_chip *chip, int csline,
 {
 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
 	const struct nand_sdr_timings *timings;
-	u32 rate, tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt;
+	u32 rate, tpoecs, tprecs, tc2r, tw2r, twh, twst = 0, trlt = 0;
 
 	timings = nand_get_sdr_timings(conf);
 	if (IS_ERR(timings))
@@ -544,11 +544,19 @@ static int mtk_nfc_setup_data_interface(struct nand_chip *chip, int csline,
 	twh = DIV_ROUND_UP(twh * rate, 1000000) - 1;
 	twh &= 0xf;
 
-	twst = timings->tWP_min / 1000;
+	/* Calculate min low level timing for write cycle */
+	if ((twh + 1) * 1000000 / rate < timings->tWC_min / 1000)
+		twst = (timings->tWC_min / 1000 - (twh + 1) * 1000000 / rate)
+			* 1000;
+	twst = max(timings->tWP_min, twst) / 1000;
 	twst = DIV_ROUND_UP(twst * rate, 1000000) - 1;
 	twst &= 0xf;
 
-	trlt = max(timings->tREA_max, timings->tRP_min) / 1000;
+	/* Calculate min low level timing for read cycle */
+	if ((twh + 1) * 1000000 / rate < timings->tRC_min / 1000)
+		trlt = (timings->tRC_min / 1000 - (twh + 1) * 1000000 / rate)
+			* 1000;
+	trlt = max3(trlt, timings->tREA_max, timings->tRP_min) / 1000;
 	trlt = DIV_ROUND_UP(trlt * rate, 1000000) - 1;
 	trlt &= 0xf;
 
-- 
2.18.0


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[PATCH 2/5] mtd: rawnand: mtk: Improve data sampling timing for read cycle

[Xiaolei Li]

Currently, we expand RE# low level time by choosing the max value
between RE# pulse width and RE# access time, and sample data at the
rising edge of RE#.

Then, if RE# access time is bigger than RE# pulse width, the real
read cycle time may be more than NAND SPEC required. This makes
read performance be worse than that expected.

This patch improves data sampling timing by calculating RE# low level
time according to RE# pulse width. If RE# access time is bigger than
RE# pulse width, then delay sampling data timing.

The result of contrast test base on MT2712 evaluat board is as follow.

nand: Micron MT29F16G08ADBCAH4
nand: 2048 MiB, SLC, erase size: 256 KiB, page size: 4096, OOB size: 224

NFI 2x clock rate: 124800000 HZ.

Test tool: mtd_speedtest.ko

Read speed without this patch:
mtd_speedtest: page read speed is 14012 KiB/s
mtd_speedtest: 2 page read speed is 14860 KiB/s

Read speed with this patch:
mtd_speedtest: page read speed is 18724 KiB/s
mtd_speedtest: 2 page read speed is 18713 KiB/s

Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
---
 drivers/mtd/nand/raw/mtk_nand.c | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
index dd855f860a4b..a2f7af536380 100644
--- a/drivers/mtd/nand/raw/mtk_nand.c
+++ b/drivers/mtd/nand/raw/mtk_nand.c
@@ -87,6 +87,10 @@
 #define NFI_FDMM(x)		(0xA4 + (x) * sizeof(u32) * 2)
 #define NFI_FDM_MAX_SIZE	(8)
 #define NFI_FDM_MIN_SIZE	(1)
+#define NFI_DEBUG_CON1		(0x220)
+#define		STROBE_MASK		GENMASK(4, 3)
+#define		STROBE_SHIFT		(3)
+#define		MAX_STROBE_DLY		(3)
 #define NFI_MASTER_STA		(0x224)
 #define		MASTER_STA_MASK		(0x0FFF)
 #define NFI_EMPTY_THRESH	(0x23C)
@@ -509,6 +513,7 @@ static int mtk_nfc_setup_data_interface(struct nand_chip *chip, int csline,
 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
 	const struct nand_sdr_timings *timings;
 	u32 rate, tpoecs, tprecs, tc2r, tw2r, twh, twst = 0, trlt = 0;
+	u32 tsel, reg;
 
 	timings = nand_get_sdr_timings(conf);
 	if (IS_ERR(timings))
@@ -556,10 +561,25 @@ static int mtk_nfc_setup_data_interface(struct nand_chip *chip, int csline,
 	if ((twh + 1) * 1000000 / rate < timings->tRC_min / 1000)
 		trlt = (timings->tRC_min / 1000 - (twh + 1) * 1000000 / rate)
 			* 1000;
-	trlt = max3(trlt, timings->tREA_max, timings->tRP_min) / 1000;
+	trlt = max(trlt, timings->tRP_min) / 1000;
 	trlt = DIV_ROUND_UP(trlt * rate, 1000000) - 1;
 	trlt &= 0xf;
 
+	/* Calculate strobe sel */
+	reg = nfi_readl(nfc, NFI_DEBUG_CON1);
+	reg &= ~STROBE_MASK;
+	if ((trlt + 1) * 1000000 / rate < timings->tREA_max / 1000) {
+		tsel = timings->tREA_max / 1000;
+		tsel = DIV_ROUND_UP(tsel * rate, 1000000);
+		tsel -= (trlt + 1);
+		if (tsel > MAX_STROBE_DLY) {
+			trlt += tsel - MAX_STROBE_DLY;
+			tsel = MAX_STROBE_DLY;
+		}
+		reg |= tsel << STROBE_SHIFT;
+	}
+	nfi_writel(nfc, reg, NFI_DEBUG_CON1);
+
 	/*
 	 * ACCON: access timing control register
 	 * -------------------------------------
-- 
2.18.0


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[PATCH 3/5] mtd: rawnand: mtk: Add validity check for CE# pin setting

[Xiaolei Li]

Currently, we only check how many CE# pins are set in device tree.
But it should be necessary to check whether CE# pin setting is
duplicated or if CE# pin index exceeds the maximum CE# number that
controller supports.

So, add validity check to avoid these invalid settings.

Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
---
 drivers/mtd/nand/raw/mtk_nand.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
index a2f7af536380..7a5e8c9cf61b 100644
--- a/drivers/mtd/nand/raw/mtk_nand.c
+++ b/drivers/mtd/nand/raw/mtk_nand.c
@@ -162,6 +162,8 @@ struct mtk_nfc {
 	struct list_head chips;
 
 	u8 *buffer;
+
+	unsigned long assigned_cs;
 };
 
 /*
@@ -1351,6 +1353,17 @@ static int mtk_nfc_nand_chip_init(struct device *dev, struct mtk_nfc *nfc,
 			dev_err(dev, "reg property failure : %d\n", ret);
 			return ret;
 		}
+
+		if (tmp >= MTK_NAND_MAX_NSELS) {
+			dev_err(dev, "invalid CS: %u\n", tmp);
+			return -EINVAL;
+		}
+
+		if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
+			dev_err(dev, "CS %u already assigned\n", tmp);
+			return -EINVAL;
+		}
+
 		chip->sels[i] = tmp;
 	}
 
-- 
2.18.0


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[PATCH 4/5] mtd: rawnand: mtk: Fix wrongly assigned oob buffer pointer issue

[Xiaolei Li]

One main goal of the function mtk_nfc_update_ecc_stats is to check
whether sectors are all empty. If they are empty, set these sectors's
data buffer and oob buffer as 0xff.

But now, the sector oob buffer pointer is wrongly assigned. We always
do memset from sector 0.

To fix this issue, pass start secotr number to make oob buffer pointer
be properly assigned.

Fixes: 93db446a424c ("mtd: nand: move raw NAND related code to the raw/ subdir")
Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
---
 drivers/mtd/nand/raw/mtk_nand.c | 21 ++++++++++-----------
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
index 7a5e8c9cf61b..cf5e50e704ae 100644
--- a/drivers/mtd/nand/raw/mtk_nand.c
+++ b/drivers/mtd/nand/raw/mtk_nand.c
@@ -873,19 +873,21 @@ static int mtk_nfc_write_oob_std(struct nand_chip *chip, int page)
 	return mtk_nfc_write_page_raw(chip, NULL, 1, page);
 }
 
-static int mtk_nfc_update_ecc_stats(struct mtd_info *mtd, u8 *buf, u32 sectors)
+static int mtk_nfc_update_ecc_stats(struct mtd_info *mtd, u8 *buf, u32 start,
+				    u32 sectors)
 {
 	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
 	struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
 	struct mtk_ecc_stats stats;
+	u32 reg_size = mtk_nand->fdm.reg_size;
 	int rc, i;
 
 	rc = nfi_readl(nfc, NFI_STA) & STA_EMP_PAGE;
 	if (rc) {
 		memset(buf, 0xff, sectors * chip->ecc.size);
 		for (i = 0; i < sectors; i++)
-			memset(oob_ptr(chip, i), 0xff, mtk_nand->fdm.reg_size);
+			memset(oob_ptr(chip, start + i), 0xff, reg_size);
 		return 0;
 	}
 
@@ -905,7 +907,7 @@ static int mtk_nfc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
 	u32 spare = mtk_nand->spare_per_sector;
 	u32 column, sectors, start, end, reg;
 	dma_addr_t addr;
-	int bitflips;
+	int bitflips = 0;
 	size_t len;
 	u8 *buf;
 	int rc;
@@ -972,14 +974,11 @@ static int mtk_nfc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
 	if (rc < 0) {
 		dev_err(nfc->dev, "subpage done timeout\n");
 		bitflips = -EIO;
-	} else {
-		bitflips = 0;
-		if (!raw) {
-			rc = mtk_ecc_wait_done(nfc->ecc, ECC_DECODE);
-			bitflips = rc < 0 ? -ETIMEDOUT :
-				mtk_nfc_update_ecc_stats(mtd, buf, sectors);
-			mtk_nfc_read_fdm(chip, start, sectors);
-		}
+	} else if (!raw) {
+		rc = mtk_ecc_wait_done(nfc->ecc, ECC_DECODE);
+		bitflips = rc < 0 ? -ETIMEDOUT :
+			mtk_nfc_update_ecc_stats(mtd, buf, start, sectors);
+		mtk_nfc_read_fdm(chip, start, sectors);
 	}
 
 	dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE);
-- 
2.18.0


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[PATCH 5/5] mtd: rawnand: mtk: Setup empty page threshold correctly

[Xiaolei Li]

MTK NAND Controller has the ability to check whether read data are
mostly 0xff by comparing zero bit conut of read data with empty
threshold automatically.

But now we never set this threshold and always make it be default value
which is 10.

This patch fixes this problem by setting empty threshold as the product
of read sector count and ecc strength.

Fixes: 93db446a424c ("mtd: nand: move raw NAND related code to the raw/ subdir")
Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
---
 drivers/mtd/nand/raw/mtk_nand.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
index cf5e50e704ae..675d4faa3480 100644
--- a/drivers/mtd/nand/raw/mtk_nand.c
+++ b/drivers/mtd/nand/raw/mtk_nand.c
@@ -94,6 +94,7 @@
 #define NFI_MASTER_STA		(0x224)
 #define		MASTER_STA_MASK		(0x0FFF)
 #define NFI_EMPTY_THRESH	(0x23C)
+#define		EMPTY_THRESH_MASK	GENMASK(7, 0)
 
 #define MTK_NAME		"mtk-nand"
 #define KB(x)			((x) * 1024UL)
@@ -931,6 +932,10 @@ static int mtk_nfc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
 		return -EINVAL;
 	}
 
+	/* Setup empty threshold */
+	reg = max(sectors * chip->ecc.strength, EMPTY_THRESH_MASK);
+	nfi_writel(nfc, reg, NFI_EMPTY_THRESH);
+
 	reg = nfi_readw(nfc, NFI_CNFG);
 	reg |= CNFG_READ_EN | CNFG_DMA_BURST_EN | CNFG_AHB;
 	if (!raw) {
-- 
2.18.0


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Re: [PATCH 1/5] mtd: rawnand: mtk: Correct low level time calculation of r/w cycle

[Miquel Raynal]

Hi Xiaolei,

Xiaolei Li <xiaolei.li@mediatek.com> wrote on Mon, 29 Apr 2019 14:38:30
+0800:

> At present, the flow of calculating AC timing of read/write cycle in SDR
> mode is that:
> At first, calculate high hold time which is valid for both read and write
> cycle using the max value between tREH_min and tWH_min.
> Secondly, calculate WE# pulse width using tWP_min.
> Thridly, calculate RE# pulse width using the bigger one between tREA_max
> and tRP_min.
> 
> But NAND SPEC shows that Controller should also meet write/read cycle time.
> That is write cycle time should be more than tWC_min and read cycle should
> be more than tRC_min. Obviously, we do not achieve that now.
> 
> This patch corrects the low level time calculation to meet minimum
> read/write cycle time required. After getting the high hold time, WE# low
> level time will be promised to meet tWP_min and tWC_min requirement,
> and RE# low level time will be promised to meet tREA_max, tRP_min and
> tRC_min requirement.
> 
> Fixes: 93db446a424c ("mtd: nand: move raw NAND related code to the raw/ subdir")

This is definitely not the faulty patch. Please use --follow when
searching for the culprit, to avoid being blocked by the
renaming/moving work.

Also a Cc: stable might be worth.

> Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
> ---
>  drivers/mtd/nand/raw/mtk_nand.c | 14 +++++++++++---
>  1 file changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
> index b6b4602f5132..dd855f860a4b 100644
> --- a/drivers/mtd/nand/raw/mtk_nand.c
> +++ b/drivers/mtd/nand/raw/mtk_nand.c
> @@ -508,7 +508,7 @@ static int mtk_nfc_setup_data_interface(struct nand_chip *chip, int csline,
>  {
>  	struct mtk_nfc *nfc = nand_get_controller_data(chip);
>  	const struct nand_sdr_timings *timings;
> -	u32 rate, tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt;
> +	u32 rate, tpoecs, tprecs, tc2r, tw2r, twh, twst = 0, trlt = 0;
>  
>  	timings = nand_get_sdr_timings(conf);
>  	if (IS_ERR(timings))
> @@ -544,11 +544,19 @@ static int mtk_nfc_setup_data_interface(struct nand_chip *chip, int csline,
>  	twh = DIV_ROUND_UP(twh * rate, 1000000) - 1;
>  	twh &= 0xf;
>  
> -	twst = timings->tWP_min / 1000;
> +	/* Calculate min low level timing for write cycle */
> +	if ((twh + 1) * 1000000 / rate < timings->tWC_min / 1000)
> +		twst = (timings->tWC_min / 1000 - (twh + 1) * 1000000 / rate)
> +			* 1000;
> +	twst = max(timings->tWP_min, twst) / 1000;
>  	twst = DIV_ROUND_UP(twst * rate, 1000000) - 1;
>  	twst &= 0xf;
>  
> -	trlt = max(timings->tREA_max, timings->tRP_min) / 1000;
> +	/* Calculate min low level timing for read cycle */
> +	if ((twh + 1) * 1000000 / rate < timings->tRC_min / 1000)
> +		trlt = (timings->tRC_min / 1000 - (twh + 1) * 1000000 / rate)
> +			* 1000;
> +	trlt = max3(trlt, timings->tREA_max, timings->tRP_min) / 1000;
>  	trlt = DIV_ROUND_UP(trlt * rate, 1000000) - 1;
>  	trlt &= 0xf;
>  


With this fixed,

Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>

Thanks,
Miquèl

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Re: [PATCH 2/5] mtd: rawnand: mtk: Improve data sampling timing for read cycle

[Miquel Raynal]

Hi Xiaolei,

Xiaolei Li <xiaolei.li@mediatek.com> wrote on Mon, 29 Apr 2019 14:38:31
+0800:

> Currently, we expand RE# low level time by choosing the max value
> between RE# pulse width and RE# access time, and sample data at the
> rising edge of RE#.
> 
> Then, if RE# access time is bigger than RE# pulse width, the real
> read cycle time may be more than NAND SPEC required. This makes
> read performance be worse than that expected.
> 
> This patch improves data sampling timing by calculating RE# low level
> time according to RE# pulse width. If RE# access time is bigger than
> RE# pulse width, then delay sampling data timing.
> 
> The result of contrast test base on MT2712 evaluat board is as follow.
> 
> nand: Micron MT29F16G08ADBCAH4
> nand: 2048 MiB, SLC, erase size: 256 KiB, page size: 4096, OOB size: 224
> 
> NFI 2x clock rate: 124800000 HZ.
> 
> Test tool: mtd_speedtest.ko
> 
> Read speed without this patch:
> mtd_speedtest: page read speed is 14012 KiB/s
> mtd_speedtest: 2 page read speed is 14860 KiB/s
> 
> Read speed with this patch:
> mtd_speedtest: page read speed is 18724 KiB/s
> mtd_speedtest: 2 page read speed is 18713 KiB/s
> 
> Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
> ---
>  drivers/mtd/nand/raw/mtk_nand.c | 22 +++++++++++++++++++++-
>  1 file changed, 21 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
> index dd855f860a4b..a2f7af536380 100644
> --- a/drivers/mtd/nand/raw/mtk_nand.c
> +++ b/drivers/mtd/nand/raw/mtk_nand.c
> @@ -87,6 +87,10 @@
>  #define NFI_FDMM(x)		(0xA4 + (x) * sizeof(u32) * 2)
>  #define NFI_FDM_MAX_SIZE	(8)
>  #define NFI_FDM_MIN_SIZE	(1)
> +#define NFI_DEBUG_CON1		(0x220)
> +#define		STROBE_MASK		GENMASK(4, 3)
> +#define		STROBE_SHIFT		(3)
> +#define		MAX_STROBE_DLY		(3)
>  #define NFI_MASTER_STA		(0x224)
>  #define		MASTER_STA_MASK		(0x0FFF)
>  #define NFI_EMPTY_THRESH	(0x23C)
> @@ -509,6 +513,7 @@ static int mtk_nfc_setup_data_interface(struct nand_chip *chip, int csline,
>  	struct mtk_nfc *nfc = nand_get_controller_data(chip);
>  	const struct nand_sdr_timings *timings;
>  	u32 rate, tpoecs, tprecs, tc2r, tw2r, twh, twst = 0, trlt = 0;
> +	u32 tsel, reg;
>  
>  	timings = nand_get_sdr_timings(conf);
>  	if (IS_ERR(timings))
> @@ -556,10 +561,25 @@ static int mtk_nfc_setup_data_interface(struct nand_chip *chip, int csline,
>  	if ((twh + 1) * 1000000 / rate < timings->tRC_min / 1000)
>  		trlt = (timings->tRC_min / 1000 - (twh + 1) * 1000000 / rate)
>  			* 1000;
> -	trlt = max3(trlt, timings->tREA_max, timings->tRP_min) / 1000;
> +	trlt = max(trlt, timings->tRP_min) / 1000;
>  	trlt = DIV_ROUND_UP(trlt * rate, 1000000) - 1;
>  	trlt &= 0xf;
>  
> +	/* Calculate strobe sel */
> +	reg = nfi_readl(nfc, NFI_DEBUG_CON1);
> +	reg &= ~STROBE_MASK;
> +	if ((trlt + 1) * 1000000 / rate < timings->tREA_max / 1000) {

Please do the calculation and condition in separate step, this is
hardly readable. Maybe you can explain it with a comment as well.

> +		tsel = timings->tREA_max / 1000;
> +		tsel = DIV_ROUND_UP(tsel * rate, 1000000);

Are you sure tsel * rate cannot overflow?

> +		tsel -= (trlt + 1);
> +		if (tsel > MAX_STROBE_DLY) {
> +			trlt += tsel - MAX_STROBE_DLY;
> +			tsel = MAX_STROBE_DLY;
> +		}
> +		reg |= tsel << STROBE_SHIFT;
> +	}
> +	nfi_writel(nfc, reg, NFI_DEBUG_CON1);
> +
>  	/*
>  	 * ACCON: access timing control register
>  	 * -------------------------------------




Thanks,
Miquèl

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Re: [PATCH 3/5] mtd: rawnand: mtk: Add validity check for CE# pin setting

[Miquel Raynal]

Hi Xiaolei,

Xiaolei Li <xiaolei.li@mediatek.com> wrote on Mon, 29 Apr 2019 14:38:32
+0800:

> Currently, we only check how many CE# pins are set in device tree.
> But it should be necessary to check whether CE# pin setting is
> duplicated or if CE# pin index exceeds the maximum CE# number that
> controller supports.
> 
> So, add validity check to avoid these invalid settings.
> 
> Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
> ---
>  drivers/mtd/nand/raw/mtk_nand.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
> index a2f7af536380..7a5e8c9cf61b 100644
> --- a/drivers/mtd/nand/raw/mtk_nand.c
> +++ b/drivers/mtd/nand/raw/mtk_nand.c
> @@ -162,6 +162,8 @@ struct mtk_nfc {
>  	struct list_head chips;
>  
>  	u8 *buffer;
> +
> +	unsigned long assigned_cs;
>  };
>  
>  /*
> @@ -1351,6 +1353,17 @@ static int mtk_nfc_nand_chip_init(struct device *dev, struct mtk_nfc *nfc,
>  			dev_err(dev, "reg property failure : %d\n", ret);
>  			return ret;
>  		}
> +
> +		if (tmp >= MTK_NAND_MAX_NSELS) {
> +			dev_err(dev, "invalid CS: %u\n", tmp);
> +			return -EINVAL;
> +		}
> +
> +		if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
> +			dev_err(dev, "CS %u already assigned\n", tmp);
> +			return -EINVAL;
> +		}
> +
>  		chip->sels[i] = tmp;
>  	}
>  

Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>


Thanks,
Miquèl

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Re: [PATCH 4/5] mtd: rawnand: mtk: Fix wrongly assigned oob buffer pointer issue

[Miquel Raynal]

Hi Xiaolei,

Xiaolei Li <xiaolei.li@mediatek.com> wrote on Mon, 29 Apr 2019 14:38:33
+0800:

> One main goal of the function mtk_nfc_update_ecc_stats is to check
> whether sectors are all empty. If they are empty, set these sectors's
> data buffer and oob buffer as 0xff.
> 
> But now, the sector oob buffer pointer is wrongly assigned. We always
> do memset from sector 0.
> 
> To fix this issue, pass start secotr number to make oob buffer pointer

                                sector

> be properly assigned.

Please use upper case for plain English acronyms: NAND, ECC, OOB, etc.

> 
> Fixes: 93db446a424c ("mtd: nand: move raw NAND related code to the raw/ subdir")

Same comment as before, wrong commit pointed in the Fixes tag.

> Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
> ---
>  drivers/mtd/nand/raw/mtk_nand.c | 21 ++++++++++-----------
>  1 file changed, 10 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
> index 7a5e8c9cf61b..cf5e50e704ae 100644
> --- a/drivers/mtd/nand/raw/mtk_nand.c
> +++ b/drivers/mtd/nand/raw/mtk_nand.c
> @@ -873,19 +873,21 @@ static int mtk_nfc_write_oob_std(struct nand_chip *chip, int page)
>  	return mtk_nfc_write_page_raw(chip, NULL, 1, page);
>  }
>  
> -static int mtk_nfc_update_ecc_stats(struct mtd_info *mtd, u8 *buf, u32 sectors)
> +static int mtk_nfc_update_ecc_stats(struct mtd_info *mtd, u8 *buf, u32 start,
> +				    u32 sectors)
>  {
>  	struct nand_chip *chip = mtd_to_nand(mtd);
>  	struct mtk_nfc *nfc = nand_get_controller_data(chip);
>  	struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
>  	struct mtk_ecc_stats stats;
> +	u32 reg_size = mtk_nand->fdm.reg_size;
>  	int rc, i;
>  
>  	rc = nfi_readl(nfc, NFI_STA) & STA_EMP_PAGE;
>  	if (rc) {
>  		memset(buf, 0xff, sectors * chip->ecc.size);
>  		for (i = 0; i < sectors; i++)
> -			memset(oob_ptr(chip, i), 0xff, mtk_nand->fdm.reg_size);
> +			memset(oob_ptr(chip, start + i), 0xff, reg_size);
>  		return 0;
>  	}
>  
> @@ -905,7 +907,7 @@ static int mtk_nfc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
>  	u32 spare = mtk_nand->spare_per_sector;
>  	u32 column, sectors, start, end, reg;
>  	dma_addr_t addr;
> -	int bitflips;
> +	int bitflips = 0;
>  	size_t len;
>  	u8 *buf;
>  	int rc;
> @@ -972,14 +974,11 @@ static int mtk_nfc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
>  	if (rc < 0) {
>  		dev_err(nfc->dev, "subpage done timeout\n");
>  		bitflips = -EIO;
> -	} else {
> -		bitflips = 0;
> -		if (!raw) {
> -			rc = mtk_ecc_wait_done(nfc->ecc, ECC_DECODE);
> -			bitflips = rc < 0 ? -ETIMEDOUT :
> -				mtk_nfc_update_ecc_stats(mtd, buf, sectors);
> -			mtk_nfc_read_fdm(chip, start, sectors);
> -		}
> +	} else if (!raw) {
> +		rc = mtk_ecc_wait_done(nfc->ecc, ECC_DECODE);
> +		bitflips = rc < 0 ? -ETIMEDOUT :
> +			mtk_nfc_update_ecc_stats(mtd, buf, start, sectors);
> +		mtk_nfc_read_fdm(chip, start, sectors);
>  	}
>  
>  	dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE);

With this addressed:

Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>


Thanks,
Miquèl

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Re: [PATCH 5/5] mtd: rawnand: mtk: Setup empty page threshold correctly

[Miquel Raynal]

Hi Xiaolei,

Xiaolei Li <xiaolei.li@mediatek.com> wrote on Mon, 29 Apr 2019 14:38:34
+0800:

> MTK NAND Controller has the ability to check whether read data are
> mostly 0xff by comparing zero bit conut of read data with empty

                                    count ? 
> threshold automatically.
> 
> But now we never set this threshold and always make it be default value
> which is 10.
> 
> This patch fixes this problem by setting empty threshold as the product
> of read sector count and ecc strength.

Do we use these feature yet?

s/ecc/ECC/

> 
> Fixes: 93db446a424c ("mtd: nand: move raw NAND related code to the raw/ subdir")

Ditto.

> Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
> ---
>  drivers/mtd/nand/raw/mtk_nand.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
> index cf5e50e704ae..675d4faa3480 100644
> --- a/drivers/mtd/nand/raw/mtk_nand.c
> +++ b/drivers/mtd/nand/raw/mtk_nand.c
> @@ -94,6 +94,7 @@
>  #define NFI_MASTER_STA		(0x224)
>  #define		MASTER_STA_MASK		(0x0FFF)
>  #define NFI_EMPTY_THRESH	(0x23C)
> +#define		EMPTY_THRESH_MASK	GENMASK(7, 0)
>  
>  #define MTK_NAME		"mtk-nand"
>  #define KB(x)			((x) * 1024UL)
> @@ -931,6 +932,10 @@ static int mtk_nfc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
>  		return -EINVAL;
>  	}
>  
> +	/* Setup empty threshold */
> +	reg = max(sectors * chip->ecc.strength, EMPTY_THRESH_MASK);
> +	nfi_writel(nfc, reg, NFI_EMPTY_THRESH);
> +
>  	reg = nfi_readw(nfc, NFI_CNFG);
>  	reg |= CNFG_READ_EN | CNFG_DMA_BURST_EN | CNFG_AHB;
>  	if (!raw) {




Thanks,
Miquèl

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Re: [PATCH 1/5] mtd: rawnand: mtk: Correct low level time calculation of r/w cycle

[xiaolei li]

Hi Miquel,

Thanks for your review.


On Mon, 2019-04-29 at 11:03 +0200, Miquel Raynal wrote:
> Hi Xiaolei,
> 
> Xiaolei Li <xiaolei.li@mediatek.com> wrote on Mon, 29 Apr 2019 14:38:30
> +0800:
> 
> > At present, the flow of calculating AC timing of read/write cycle in SDR
> > mode is that:
> > At first, calculate high hold time which is valid for both read and write
> > cycle using the max value between tREH_min and tWH_min.
> > Secondly, calculate WE# pulse width using tWP_min.
> > Thridly, calculate RE# pulse width using the bigger one between tREA_max
> > and tRP_min.
> > 
> > But NAND SPEC shows that Controller should also meet write/read cycle time.
> > That is write cycle time should be more than tWC_min and read cycle should
> > be more than tRC_min. Obviously, we do not achieve that now.
> > 
> > This patch corrects the low level time calculation to meet minimum
> > read/write cycle time required. After getting the high hold time, WE# low
> > level time will be promised to meet tWP_min and tWC_min requirement,
> > and RE# low level time will be promised to meet tREA_max, tRP_min and
> > tRC_min requirement.
> > 
> > Fixes: 93db446a424c ("mtd: nand: move raw NAND related code to the raw/ subdir")
> 
> This is definitely not the faulty patch. Please use --follow when
> searching for the culprit, to avoid being blocked by the
> renaming/moving work.
Yes. This issue exists before raw/ sudir being created.

The faulty patch should be 'commit edfee3619c49 ("mtd: nand: mtk: add
->setup_data_interface() hook")' which cannot be found in git history
now.

Should I list it here?

> 
> Also a Cc: stable might be worth.
OK. Thanks.

> 
> > Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
> > ---
> >  drivers/mtd/nand/raw/mtk_nand.c | 14 +++++++++++---
> >  1 file changed, 11 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
> > index b6b4602f5132..dd855f860a4b 100644
> > --- a/drivers/mtd/nand/raw/mtk_nand.c
> > +++ b/drivers/mtd/nand/raw/mtk_nand.c
> > @@ -508,7 +508,7 @@ static int mtk_nfc_setup_data_interface(struct nand_chip *chip, int csline,
> >  {
> >  	struct mtk_nfc *nfc = nand_get_controller_data(chip);
> >  	const struct nand_sdr_timings *timings;
> > -	u32 rate, tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt;
> > +	u32 rate, tpoecs, tprecs, tc2r, tw2r, twh, twst = 0, trlt = 0;
> >  
> >  	timings = nand_get_sdr_timings(conf);
> >  	if (IS_ERR(timings))
> > @@ -544,11 +544,19 @@ static int mtk_nfc_setup_data_interface(struct nand_chip *chip, int csline,
> >  	twh = DIV_ROUND_UP(twh * rate, 1000000) - 1;
> >  	twh &= 0xf;
> >  
> > -	twst = timings->tWP_min / 1000;
> > +	/* Calculate min low level timing for write cycle */
> > +	if ((twh + 1) * 1000000 / rate < timings->tWC_min / 1000)
> > +		twst = (timings->tWC_min / 1000 - (twh + 1) * 1000000 / rate)
> > +			* 1000;
> > +	twst = max(timings->tWP_min, twst) / 1000;
> >  	twst = DIV_ROUND_UP(twst * rate, 1000000) - 1;
> >  	twst &= 0xf;
> >  
> > -	trlt = max(timings->tREA_max, timings->tRP_min) / 1000;
> > +	/* Calculate min low level timing for read cycle */
> > +	if ((twh + 1) * 1000000 / rate < timings->tRC_min / 1000)
> > +		trlt = (timings->tRC_min / 1000 - (twh + 1) * 1000000 / rate)
> > +			* 1000;
> > +	trlt = max3(trlt, timings->tREA_max, timings->tRP_min) / 1000;
> >  	trlt = DIV_ROUND_UP(trlt * rate, 1000000) - 1;
> >  	trlt &= 0xf;
> >  
> 
> 
> With this fixed,
> 
> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
> 
> Thanks,
> Miquèl

Thanks,
Xiaolei


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Re: [PATCH 2/5] mtd: rawnand: mtk: Improve data sampling timing for read cycle

[xiaolei li]

On Mon, 2019-04-29 at 11:10 +0200, Miquel Raynal wrote:
> Hi Xiaolei,
> 
> Xiaolei Li <xiaolei.li@mediatek.com> wrote on Mon, 29 Apr 2019 14:38:31
> +0800:
> 
> > Currently, we expand RE# low level time by choosing the max value
> > between RE# pulse width and RE# access time, and sample data at the
> > rising edge of RE#.
> > 
> > Then, if RE# access time is bigger than RE# pulse width, the real
> > read cycle time may be more than NAND SPEC required. This makes
> > read performance be worse than that expected.
> > 
> > This patch improves data sampling timing by calculating RE# low level
> > time according to RE# pulse width. If RE# access time is bigger than
> > RE# pulse width, then delay sampling data timing.
> > 
> > The result of contrast test base on MT2712 evaluat board is as follow.
> > 
> > nand: Micron MT29F16G08ADBCAH4
> > nand: 2048 MiB, SLC, erase size: 256 KiB, page size: 4096, OOB size: 224
> > 
> > NFI 2x clock rate: 124800000 HZ.
> > 
> > Test tool: mtd_speedtest.ko
> > 
> > Read speed without this patch:
> > mtd_speedtest: page read speed is 14012 KiB/s
> > mtd_speedtest: 2 page read speed is 14860 KiB/s
> > 
> > Read speed with this patch:
> > mtd_speedtest: page read speed is 18724 KiB/s
> > mtd_speedtest: 2 page read speed is 18713 KiB/s
> > 
> > Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
> > ---
> >  drivers/mtd/nand/raw/mtk_nand.c | 22 +++++++++++++++++++++-
> >  1 file changed, 21 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
> > index dd855f860a4b..a2f7af536380 100644
> > --- a/drivers/mtd/nand/raw/mtk_nand.c
> > +++ b/drivers/mtd/nand/raw/mtk_nand.c
> > @@ -87,6 +87,10 @@
> >  #define NFI_FDMM(x)		(0xA4 + (x) * sizeof(u32) * 2)
> >  #define NFI_FDM_MAX_SIZE	(8)
> >  #define NFI_FDM_MIN_SIZE	(1)
> > +#define NFI_DEBUG_CON1		(0x220)
> > +#define		STROBE_MASK		GENMASK(4, 3)
> > +#define		STROBE_SHIFT		(3)
> > +#define		MAX_STROBE_DLY		(3)
> >  #define NFI_MASTER_STA		(0x224)
> >  #define		MASTER_STA_MASK		(0x0FFF)
> >  #define NFI_EMPTY_THRESH	(0x23C)
> > @@ -509,6 +513,7 @@ static int mtk_nfc_setup_data_interface(struct nand_chip *chip, int csline,
> >  	struct mtk_nfc *nfc = nand_get_controller_data(chip);
> >  	const struct nand_sdr_timings *timings;
> >  	u32 rate, tpoecs, tprecs, tc2r, tw2r, twh, twst = 0, trlt = 0;
> > +	u32 tsel, reg;
> >  
> >  	timings = nand_get_sdr_timings(conf);
> >  	if (IS_ERR(timings))
> > @@ -556,10 +561,25 @@ static int mtk_nfc_setup_data_interface(struct nand_chip *chip, int csline,
> >  	if ((twh + 1) * 1000000 / rate < timings->tRC_min / 1000)
> >  		trlt = (timings->tRC_min / 1000 - (twh + 1) * 1000000 / rate)
> >  			* 1000;
> > -	trlt = max3(trlt, timings->tREA_max, timings->tRP_min) / 1000;
> > +	trlt = max(trlt, timings->tRP_min) / 1000;
> >  	trlt = DIV_ROUND_UP(trlt * rate, 1000000) - 1;
> >  	trlt &= 0xf;
> >  
> > +	/* Calculate strobe sel */
> > +	reg = nfi_readl(nfc, NFI_DEBUG_CON1);
> > +	reg &= ~STROBE_MASK;
> > +	if ((trlt + 1) * 1000000 / rate < timings->tREA_max / 1000) {
> 
> Please do the calculation and condition in separate step, this is
> hardly readable. Maybe you can explain it with a comment as well.
Sorry to trouble you.
I will change it as your advice in next patch version.

> 
> > +		tsel = timings->tREA_max / 1000;
> > +		tsel = DIV_ROUND_UP(tsel * rate, 1000000);
> 
> Are you sure tsel * rate cannot overflow?
Thanks for your reminding.
The unit of tsel here is nano second, and the unit of rate is KHZ.
There should be no overflowing here.

> 
> > +		tsel -= (trlt + 1);
> > +		if (tsel > MAX_STROBE_DLY) {
> > +			trlt += tsel - MAX_STROBE_DLY;
> > +			tsel = MAX_STROBE_DLY;
> > +		}
> > +		reg |= tsel << STROBE_SHIFT;
> > +	}
> > +	nfi_writel(nfc, reg, NFI_DEBUG_CON1);
> > +
> >  	/*
> >  	 * ACCON: access timing control register
> >  	 * -------------------------------------
> 
> 
> 
> 
> Thanks,
> Miquèl



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Re: [PATCH 4/5] mtd: rawnand: mtk: Fix wrongly assigned oob buffer pointer issue

[xiaolei li]

Hi Miquel,

On Mon, 2019-04-29 at 11:14 +0200, Miquel Raynal wrote:
> Hi Xiaolei,
> 
> Xiaolei Li <xiaolei.li@mediatek.com> wrote on Mon, 29 Apr 2019 14:38:33
> +0800:
> 
> > One main goal of the function mtk_nfc_update_ecc_stats is to check
> > whether sectors are all empty. If they are empty, set these sectors's
> > data buffer and oob buffer as 0xff.
> > 
> > But now, the sector oob buffer pointer is wrongly assigned. We always
> > do memset from sector 0.
> > 
> > To fix this issue, pass start secotr number to make oob buffer pointer
> 
>                                 sector
Thanks. Will change this typo.

> 
> > be properly assigned.
> 
> Please use upper case for plain English acronyms: NAND, ECC, OOB, etc.
OK.

> 
> > 
> > Fixes: 93db446a424c ("mtd: nand: move raw NAND related code to the raw/ subdir")
> 
> Same comment as before, wrong commit pointed in the Fixes tag.
> 
> > Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
> > ---
> >  drivers/mtd/nand/raw/mtk_nand.c | 21 ++++++++++-----------
> >  1 file changed, 10 insertions(+), 11 deletions(-)
> > 
> > diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
> > index 7a5e8c9cf61b..cf5e50e704ae 100644
> > --- a/drivers/mtd/nand/raw/mtk_nand.c
> > +++ b/drivers/mtd/nand/raw/mtk_nand.c
> > @@ -873,19 +873,21 @@ static int mtk_nfc_write_oob_std(struct nand_chip *chip, int page)
> >  	return mtk_nfc_write_page_raw(chip, NULL, 1, page);
> >  }
> >  
> > -static int mtk_nfc_update_ecc_stats(struct mtd_info *mtd, u8 *buf, u32 sectors)
> > +static int mtk_nfc_update_ecc_stats(struct mtd_info *mtd, u8 *buf, u32 start,
> > +				    u32 sectors)
> >  {
> >  	struct nand_chip *chip = mtd_to_nand(mtd);
> >  	struct mtk_nfc *nfc = nand_get_controller_data(chip);
> >  	struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
> >  	struct mtk_ecc_stats stats;
> > +	u32 reg_size = mtk_nand->fdm.reg_size;
> >  	int rc, i;
> >  
> >  	rc = nfi_readl(nfc, NFI_STA) & STA_EMP_PAGE;
> >  	if (rc) {
> >  		memset(buf, 0xff, sectors * chip->ecc.size);
> >  		for (i = 0; i < sectors; i++)
> > -			memset(oob_ptr(chip, i), 0xff, mtk_nand->fdm.reg_size);
> > +			memset(oob_ptr(chip, start + i), 0xff, reg_size);
> >  		return 0;
> >  	}
> >  
> > @@ -905,7 +907,7 @@ static int mtk_nfc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
> >  	u32 spare = mtk_nand->spare_per_sector;
> >  	u32 column, sectors, start, end, reg;
> >  	dma_addr_t addr;
> > -	int bitflips;
> > +	int bitflips = 0;
> >  	size_t len;
> >  	u8 *buf;
> >  	int rc;
> > @@ -972,14 +974,11 @@ static int mtk_nfc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
> >  	if (rc < 0) {
> >  		dev_err(nfc->dev, "subpage done timeout\n");
> >  		bitflips = -EIO;
> > -	} else {
> > -		bitflips = 0;
> > -		if (!raw) {
> > -			rc = mtk_ecc_wait_done(nfc->ecc, ECC_DECODE);
> > -			bitflips = rc < 0 ? -ETIMEDOUT :
> > -				mtk_nfc_update_ecc_stats(mtd, buf, sectors);
> > -			mtk_nfc_read_fdm(chip, start, sectors);
> > -		}
> > +	} else if (!raw) {
> > +		rc = mtk_ecc_wait_done(nfc->ecc, ECC_DECODE);
> > +		bitflips = rc < 0 ? -ETIMEDOUT :
> > +			mtk_nfc_update_ecc_stats(mtd, buf, start, sectors);
> > +		mtk_nfc_read_fdm(chip, start, sectors);
> >  	}
> >  
> >  	dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE);
> 
> With this addressed:
> 
> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
> 
> 
> Thanks,
> Miquèl



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Re: [PATCH 5/5] mtd: rawnand: mtk: Setup empty page threshold correctly

[xiaolei li]

Hi Miquel,

On Mon, 2019-04-29 at 11:22 +0200, Miquel Raynal wrote:
> Hi Xiaolei,
> 
> Xiaolei Li <xiaolei.li@mediatek.com> wrote on Mon, 29 Apr 2019 14:38:34
> +0800:
> 
> > MTK NAND Controller has the ability to check whether read data are
> > mostly 0xff by comparing zero bit conut of read data with empty
> 
>                                     count ? 
Sorry for the typo. Will fix it.

> > threshold automatically.
> > 
> > But now we never set this threshold and always make it be default value
> > which is 10.
> > 
> > This patch fixes this problem by setting empty threshold as the product
> > of read sector count and ecc strength.
> 
> Do we use these feature yet?
Yes. This feature is always on.

NAND Controller counts zero bit when read data, and compare zero bit
count with empty threshold to determine whether data is mostly 0xff.
If zero bit count is less than the threshold, bit[12] of register
NFI_STA, STA_EMP_PAGE in mtk_nand.c, will be set as 1.

> 
> s/ecc/ECC/
OK.
> 
> > 
> > Fixes: 93db446a424c ("mtd: nand: move raw NAND related code to the raw/ subdir")
> 
> Ditto.
OK.

> 
> > Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
> > ---
> >  drivers/mtd/nand/raw/mtk_nand.c | 5 +++++
> >  1 file changed, 5 insertions(+)
> > 
> > diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
> > index cf5e50e704ae..675d4faa3480 100644
> > --- a/drivers/mtd/nand/raw/mtk_nand.c
> > +++ b/drivers/mtd/nand/raw/mtk_nand.c
> > @@ -94,6 +94,7 @@
> >  #define NFI_MASTER_STA		(0x224)
> >  #define		MASTER_STA_MASK		(0x0FFF)
> >  #define NFI_EMPTY_THRESH	(0x23C)
> > +#define		EMPTY_THRESH_MASK	GENMASK(7, 0)
> >  
> >  #define MTK_NAME		"mtk-nand"
> >  #define KB(x)			((x) * 1024UL)
> > @@ -931,6 +932,10 @@ static int mtk_nfc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
> >  		return -EINVAL;
> >  	}
> >  
> > +	/* Setup empty threshold */
> > +	reg = max(sectors * chip->ecc.strength, EMPTY_THRESH_MASK);
> > +	nfi_writel(nfc, reg, NFI_EMPTY_THRESH);
> > +
> >  	reg = nfi_readw(nfc, NFI_CNFG);
> >  	reg |= CNFG_READ_EN | CNFG_DMA_BURST_EN | CNFG_AHB;
> >  	if (!raw) {
> 
> 
> 
> 
> Thanks,
> Miquèl

Thanks,
Xiaolei


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Re: [PATCH 1/5] mtd: rawnand: mtk: Correct low level time calculation of r/w cycle

[Miquel Raynal]

Hi xiaolei,

xiaolei li <xiaolei.li@mediatek.com> wrote on Mon, 29 Apr 2019 17:35:53
+0800:

> Hi Miquel,
> 
> Thanks for your review.
> 
> 
> On Mon, 2019-04-29 at 11:03 +0200, Miquel Raynal wrote:
> > Hi Xiaolei,
> > 
> > Xiaolei Li <xiaolei.li@mediatek.com> wrote on Mon, 29 Apr 2019 14:38:30
> > +0800:
> >   
> > > At present, the flow of calculating AC timing of read/write cycle in SDR
> > > mode is that:
> > > At first, calculate high hold time which is valid for both read and write
> > > cycle using the max value between tREH_min and tWH_min.
> > > Secondly, calculate WE# pulse width using tWP_min.
> > > Thridly, calculate RE# pulse width using the bigger one between tREA_max
> > > and tRP_min.
> > > 
> > > But NAND SPEC shows that Controller should also meet write/read cycle time.
> > > That is write cycle time should be more than tWC_min and read cycle should
> > > be more than tRC_min. Obviously, we do not achieve that now.
> > > 
> > > This patch corrects the low level time calculation to meet minimum
> > > read/write cycle time required. After getting the high hold time, WE# low
> > > level time will be promised to meet tWP_min and tWC_min requirement,
> > > and RE# low level time will be promised to meet tREA_max, tRP_min and
> > > tRC_min requirement.
> > > 
> > > Fixes: 93db446a424c ("mtd: nand: move raw NAND related code to the raw/ subdir")  
> > 
> > This is definitely not the faulty patch. Please use --follow when
> > searching for the culprit, to avoid being blocked by the
> > renaming/moving work.  
> Yes. This issue exists before raw/ sudir being created.
> 
> The faulty patch should be 'commit edfee3619c49 ("mtd: nand: mtk: add
> ->setup_data_interface() hook")' which cannot be found in git history  
> now.
> 
> Should I list it here?

What do you mean? This commit exists, I can actually "git show" it.


Thanks,
Miquèl

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Re: [PATCH 1/5] mtd: rawnand: mtk: Correct low level time calculation of r/w cycle

[xiaolei li]

On Mon, 2019-04-29 at 12:02 +0200, Miquel Raynal wrote:
> Hi xiaolei,
> 
> xiaolei li <xiaolei.li@mediatek.com> wrote on Mon, 29 Apr 2019 17:35:53
> +0800:
> 
> > Hi Miquel,
> > 
> > Thanks for your review.
> > 
> > 
> > On Mon, 2019-04-29 at 11:03 +0200, Miquel Raynal wrote:
> > > Hi Xiaolei,
> > > 
> > > Xiaolei Li <xiaolei.li@mediatek.com> wrote on Mon, 29 Apr 2019 14:38:30
> > > +0800:
> > >   
> > > > At present, the flow of calculating AC timing of read/write cycle in SDR
> > > > mode is that:
> > > > At first, calculate high hold time which is valid for both read and write
> > > > cycle using the max value between tREH_min and tWH_min.
> > > > Secondly, calculate WE# pulse width using tWP_min.
> > > > Thridly, calculate RE# pulse width using the bigger one between tREA_max
> > > > and tRP_min.
> > > > 
> > > > But NAND SPEC shows that Controller should also meet write/read cycle time.
> > > > That is write cycle time should be more than tWC_min and read cycle should
> > > > be more than tRC_min. Obviously, we do not achieve that now.
> > > > 
> > > > This patch corrects the low level time calculation to meet minimum
> > > > read/write cycle time required. After getting the high hold time, WE# low
> > > > level time will be promised to meet tWP_min and tWC_min requirement,
> > > > and RE# low level time will be promised to meet tREA_max, tRP_min and
> > > > tRC_min requirement.
> > > > 
> > > > Fixes: 93db446a424c ("mtd: nand: move raw NAND related code to the raw/ subdir")  
> > > 
> > > This is definitely not the faulty patch. Please use --follow when
> > > searching for the culprit, to avoid being blocked by the
> > > renaming/moving work.  
> > Yes. This issue exists before raw/ sudir being created.
> > 
> > The faulty patch should be 'commit edfee3619c49 ("mtd: nand: mtk: add
> > ->setup_data_interface() hook")' which cannot be found in git history  
> > now.
> > 
> > Should I list it here?
> 
> What do you mean? This commit exists, I can actually "git show" it.
> 
Sorry. I find it. Will fix it in next patch version.
Thanks.

> 
> Thanks,
> Miquèl



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