From: Jungseung Lee <js07.lee@samsung.com>
To: Marek Vasut <marek.vasut@gmail.com>,
Tudor Ambarus <tudor.ambarus@microchip.com>,
David Woodhouse <dwmw2@infradead.org>,
Brian Norris <computersforpeace@gmail.com>,
Boris Brezillon <bbrezillon@kernel.org>,
Richard Weinberger <richard@nod.at>,
u.kleine-koenig@pengutronix.de, linux-mtd@lists.infradead.org,
js07.lee@gmail.com, js07.lee@samsung.com
Subject: [PATCH v3 1/4] mtd: spi-nor: rename SR_TB to indicate the using bit
Date: Sat, 13 Jul 2019 16:15:38 +0900 [thread overview]
Message-ID: <20190713071541.22090-1-js07.lee@samsung.com> (raw)
In-Reply-To: CGME20190801020509epcas1p155f87090273be705f1a9ae752c0bca5c@epcas1p1.samsung.com
Each vendor uses a different bits for SR_TB of flash.
To avoid misunderstandings, rename SR_TB to indicate the using bit.
Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
---
drivers/mtd/spi-nor/spi-nor.c | 10 +++++-----
include/linux/mtd/spi-nor.h | 6 +++++-
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 73172d7f512b..9ea03f4d943a 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1099,7 +1099,7 @@ static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
} else {
pow = ((sr & mask) ^ mask) >> shift;
*len = mtd->size >> pow;
- if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
+ if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB_BIT5)
*ofs = 0;
else
*ofs = mtd->size - *len;
@@ -1229,13 +1229,13 @@ static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
if (!(val & mask))
return -EINVAL;
- status_new = (status_old & ~mask & ~SR_TB) | val;
+ status_new = (status_old & ~mask & ~SR_TB_BIT5) | val;
/* Disallow further writes if WP pin is asserted */
status_new |= SR_SRWD;
if (!use_top)
- status_new |= SR_TB;
+ status_new |= SR_TB_BIT5;
/* Don't bother if they're the same */
if (status_new == status_old)
@@ -1311,14 +1311,14 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
return -EINVAL;
}
- status_new = (status_old & ~mask & ~SR_TB) | val;
+ status_new = (status_old & ~mask & ~SR_TB_BIT5) | val;
/* Don't protect status register if we're fully unlocked */
if (lock_len == 0)
status_new &= ~SR_SRWD;
if (!use_top)
- status_new |= SR_TB;
+ status_new |= SR_TB_BIT5;
/* Don't bother if they're the same */
if (status_new == status_old)
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index b3d360b0ee3d..f8bbc98432ff 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -126,8 +126,12 @@
#define SR_BP0 BIT(2) /* Block protect 0 */
#define SR_BP1 BIT(3) /* Block protect 1 */
#define SR_BP2 BIT(4) /* Block protect 2 */
-#define SR_TB BIT(5) /* Top/Bottom protect */
#define SR_SRWD BIT(7) /* SR write protect */
+/* Used for STM and Micron flashes */
+#define SR_TB_BIT5 BIT(5) /* Top/Bottom protect */
+/* Used for Winbond and GigaDevice flashes */
+#define SR_TB_BIT6 BIT(6) /* Top/Bottom protect */
+
/* Spansion/Cypress specific status bits */
#define SR_E_ERR BIT(5)
#define SR_P_ERR BIT(6)
--
2.17.1
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next parent reply other threads:[~2019-08-01 2:05 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20190801020509epcas1p155f87090273be705f1a9ae752c0bca5c@epcas1p1.samsung.com>
2019-07-13 7:15 ` Jungseung Lee [this message]
[not found] ` <CGME20190801020516epcas1p383452adf9755f7121812aac0f335a779@epcas1p3.samsung.com>
2019-07-13 7:15 ` [PATCH v3 2/4] mtd: spi-nor: introduce SR_BP_SHIFT define Jungseung Lee
[not found] ` <CGME20190801020520epcas1p3a9d8fc8175a5cc74be9077c2c6ee678c@epcas1p3.samsung.com>
2019-07-13 7:15 ` [PATCH v3 3/4] mtd: spi-nor: add 4bit block protection support Jungseung Lee
[not found] ` <CGME20190801020523epcas1p27580bead294a67fccea6fe8615e73da9@epcas1p2.samsung.com>
2019-07-13 7:15 ` [PATCH v3 4/4] mtd: spi-nor: support lock/unlock for a few Micron chips Jungseung Lee
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