[PATCH v3 0/2] mtd: rawnand: arasan: Fix clock rate in NV-DDR

[PATCH v3 0/2] mtd: rawnand: arasan: Fix clock rate in NV-DDR

[Amit Kumar Mahapatra]

Based on upstream discussion here:
https://lore.kernel.org/all/20211127180758.30884-1-okitain@gmail.com/

This patch series:
 - Updates NAND bus clock, instead of system clock, as per the timing modes.
 - Fixes clock rate in NV-DDR
---
BRANCH: mtd/next

Changes in v2:
- Add a patch to update NAND bus clk instead of system clk

Changes in v3:
- Set the NAND bus clk in anfc_setup_interface
---
Amit Kumar Mahapatra (1):
  mtd: rawnand: arasan: Update NAND bus clock instead of system clock

Olga Kitaina (1):
  mtd: rawnand: arasan: Fix clock rate in NV-DDR

 drivers/mtd/nand/raw/arasan-nand-controller.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

-- 
2.17.1


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[PATCH v3 1/2] mtd: rawnand: arasan: Update NAND bus clock instead of system clock

[Amit Kumar Mahapatra]

In current implementation the Arasan NAND driver is updating the
system clock(i.e., anand->clk) in accordance to the timing modes
(i.e., SDR or NVDDR). But as per the Arasan NAND controller spec the
flash clock or the NAND bus clock(i.e., nfc->bus_clk), need to be
updated instead. This patch keeps the system clock unchanged and updates
the NAND bus clock as per the timing modes.

Fixes: 197b88fecc50 ("mtd: rawnand: arasan: Add new Arasan NAND controller")
CC: stable@vger.kernel.org # 5.8+
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
---
 drivers/mtd/nand/raw/arasan-nand-controller.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/nand/raw/arasan-nand-controller.c b/drivers/mtd/nand/raw/arasan-nand-controller.c
index 53bd10738418..c5264fa223c4 100644
--- a/drivers/mtd/nand/raw/arasan-nand-controller.c
+++ b/drivers/mtd/nand/raw/arasan-nand-controller.c
@@ -347,17 +347,17 @@ static int anfc_select_target(struct nand_chip *chip, int target)
 
 	/* Update clock frequency */
 	if (nfc->cur_clk != anand->clk) {
-		clk_disable_unprepare(nfc->controller_clk);
-		ret = clk_set_rate(nfc->controller_clk, anand->clk);
+		clk_disable_unprepare(nfc->bus_clk);
+		ret = clk_set_rate(nfc->bus_clk, anand->clk);
 		if (ret) {
 			dev_err(nfc->dev, "Failed to change clock rate\n");
 			return ret;
 		}
 
-		ret = clk_prepare_enable(nfc->controller_clk);
+		ret = clk_prepare_enable(nfc->bus_clk);
 		if (ret) {
 			dev_err(nfc->dev,
-				"Failed to re-enable the controller clock\n");
+				"Failed to re-enable the bus clock\n");
 			return ret;
 		}
 
-- 
2.17.1


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[PATCH v3 2/2] mtd: rawnand: arasan: Fix clock rate in NV-DDR

[Amit Kumar Mahapatra]

From: Olga Kitaina <okitain@gmail.com>

According to the Arasan NAND controller spec, the flash clock rate for SDR
must be <= 100 MHz, while for NV-DDR it must be the same as the rate of the
CLK line for the mode. The driver previously always set 100 MHz for NV-DDR,
which would result in incorrect behavior for NV-DDR modes 0-4.

The appropriate clock rate can be calculated from the NV-DDR timing
parameters as 1/tCK, or for rates measured in picoseconds,
10^12 / nand_nvddr_timings->tCK_min.

Fixes: 197b88fecc50 ("mtd: rawnand: arasan: Add new Arasan NAND controller")
CC: stable@vger.kernel.org # 5.8+
Signed-off-by: Olga Kitaina <okitain@gmail.com>
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
---
 drivers/mtd/nand/raw/arasan-nand-controller.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/raw/arasan-nand-controller.c b/drivers/mtd/nand/raw/arasan-nand-controller.c
index c5264fa223c4..d4121d1243bf 100644
--- a/drivers/mtd/nand/raw/arasan-nand-controller.c
+++ b/drivers/mtd/nand/raw/arasan-nand-controller.c
@@ -1043,7 +1043,13 @@ static int anfc_setup_interface(struct nand_chip *chip, int target,
 				 DQS_BUFF_SEL_OUT(dqs_mode);
 	}
 
-	anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK;
+	if (nand_interface_is_sdr(conf)) {
+		anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK;
+	} else {
+		/* ONFI timings are defined in picoseconds */
+		anand->clk =  div_u64((u64)NSEC_PER_SEC * 1000,
+				      conf->timings.nvddr.tCK_min);
+	}
 
 	/*
 	 * Due to a hardware bug in the ZynqMP SoC, SDR timing modes 0-1 work
-- 
2.17.1


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Re: [PATCH v3 2/2] mtd: rawnand: arasan: Fix clock rate in NV-DDR

[Miquel Raynal]

On Tue, 2022-06-28 at 15:48:24 UTC, Amit Kumar Mahapatra wrote:
> From: Olga Kitaina <okitain@gmail.com>
> 
> According to the Arasan NAND controller spec, the flash clock rate for SDR
> must be <= 100 MHz, while for NV-DDR it must be the same as the rate of the
> CLK line for the mode. The driver previously always set 100 MHz for NV-DDR,
> which would result in incorrect behavior for NV-DDR modes 0-4.
> 
> The appropriate clock rate can be calculated from the NV-DDR timing
> parameters as 1/tCK, or for rates measured in picoseconds,
> 10^12 / nand_nvddr_timings->tCK_min.
> 
> Fixes: 197b88fecc50 ("mtd: rawnand: arasan: Add new Arasan NAND controller")
> CC: stable@vger.kernel.org # 5.8+
> Signed-off-by: Olga Kitaina <okitain@gmail.com>
> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>

Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.

Miquel

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Re: [PATCH v3 1/2] mtd: rawnand: arasan: Update NAND bus clock instead of system clock

[Miquel Raynal]

On Tue, 2022-06-28 at 15:48:23 UTC, Amit Kumar Mahapatra wrote:
> In current implementation the Arasan NAND driver is updating the
> system clock(i.e., anand->clk) in accordance to the timing modes
> (i.e., SDR or NVDDR). But as per the Arasan NAND controller spec the
> flash clock or the NAND bus clock(i.e., nfc->bus_clk), need to be
> updated instead. This patch keeps the system clock unchanged and updates
> the NAND bus clock as per the timing modes.
> 
> Fixes: 197b88fecc50 ("mtd: rawnand: arasan: Add new Arasan NAND controller")
> CC: stable@vger.kernel.org # 5.8+
> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>

Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.

Miquel

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