From: <yaliang.wang@windriver.com>
To: <tudor.ambarus@microchip.com>, <pratyush@kernel.org>,
<michael@walle.cc>, <miquel.raynal@bootlin.com>, <richard@nod.at>,
<vigneshr@ti.com>, <andy.yan@rock-chips.com>,
<cyrille.pitchen@wedev4u.fr>
Cc: <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v2 0/1] mtd: spi-nor: gigadevice: gd25q256: replace gd25q256_default_init with gd25q256_post_bfpt
Date: Mon, 17 Oct 2022 01:19:00 +0800 [thread overview]
Message-ID: <20221016171901.1483542-1-yaliang.wang@windriver.com> (raw)
In-Reply-To: <1dddc60f-44fd-df65-f491-be8379fe2380@microchip.com>
GD25Q256 'C' generation 'GD25Q256C' implements the JESD216 standards,
JESD216 doesn't define the QER field in BFPT, but the 'GD25Q256C'
does define QE bit in status register 1 bit 6, so we need to tweak
quad_enable to properly set the function.
'D' and 'E' generations implement the JESD216B standards, so parsing
the SFDP to set quad_enable function is enough for them.
As the default_init is deprecated, so the post_bfpt hook will be the
right place to do this tweak.
Changes since v1 [1]
- Just tweak the quad_enable function when needed.
Yaliang Wang (1):
mtd: spi-nor: gigadevice: gd25q256: replace gd25q256_default_init with gd25q256_post_bfpt
drivers/mtd/spi-nor/gigadevice.c | 28 +++++++++++++++++++++-------
1 file changed, 21 insertions(+), 7 deletions(-)
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next prev parent reply other threads:[~2022-10-16 17:20 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-13 8:40 [PATCH] mtd: spi-nor: gigadevice: gd25q256: replace gd25q256_default_init with gd25q256_post_bfpt yaliang.wang
[not found] ` <MN2PR17MB3375BC0E5878B19651475413B8479@MN2PR17MB3375.namprd17.prod.outlook.com>
2022-09-14 3:05 ` Yaliang Wang
2022-09-14 7:27 ` Michael Walle
2022-10-03 5:35 ` Tudor.Ambarus
2022-10-16 8:37 ` Yaliang Wang
2022-10-16 17:19 ` yaliang.wang [this message]
2022-10-16 17:19 ` yaliang.wang
2022-11-21 14:32 ` [PATCH v2 0/1] " Tudor Ambarus
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