* [PATCH 01/23] mtd: spi-nor: hisi-sfc: Drop nor->erase NULL assignment
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
@ 2019-09-17 15:54 ` Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 02/23] mtd: spi-nor: Introduce 'struct spi_nor_controller_ops' Tudor.Ambarus
` (22 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-17 15:54 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, Tudor.Ambarus, andrew, linux-kernel, vz,
linux-mediatek, joel, matthias.bgg, computersforpeace, dwmw2,
linux-arm-kernel
From: Tudor Ambarus <tudor.ambarus@microchip.com>
The pointer to 'struct spi_nor' is kzalloc'ed above in the code.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/hisi-sfc.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/hisi-sfc.c b/drivers/mtd/spi-nor/hisi-sfc.c
index 6dac9dd8bf42..c99ed9cdbf9c 100644
--- a/drivers/mtd/spi-nor/hisi-sfc.c
+++ b/drivers/mtd/spi-nor/hisi-sfc.c
@@ -364,7 +364,6 @@ static int hisi_spi_nor_register(struct device_node *np,
nor->write_reg = hisi_spi_nor_write_reg;
nor->read = hisi_spi_nor_read;
nor->write = hisi_spi_nor_write;
- nor->erase = NULL;
ret = spi_nor_scan(nor, NULL, &hwcaps);
if (ret)
return ret;
--
2.9.5
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 02/23] mtd: spi-nor: Introduce 'struct spi_nor_controller_ops'
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 01/23] mtd: spi-nor: hisi-sfc: Drop nor->erase NULL assignment Tudor.Ambarus
@ 2019-09-17 15:54 ` Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 03/23] mtd: spi-nor: cadence-quadspi: Fix cqspi_command_read() definition Tudor.Ambarus
` (21 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-17 15:54 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, Tudor.Ambarus, andrew, linux-kernel, vz,
linux-mediatek, joel, matthias.bgg, computersforpeace, dwmw2,
linux-arm-kernel
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Move all SPI NOR controller driver specific ops in a dedicated
structure. 'struct spi_nor' becomes lighter.
Use size_t for lengths in 'int (*write_reg)()' and 'int (*read_reg)()'.
Rename wite/read_buf to buf, the name of the functions are
suggestive enough. Constify buf in int (*write_reg). Comply with these
changes in the SPI NOR controller drivers.
Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/aspeed-smc.c | 23 ++++++-----
drivers/mtd/spi-nor/cadence-quadspi.c | 39 ++++++++++--------
drivers/mtd/spi-nor/hisi-sfc.c | 22 +++++-----
drivers/mtd/spi-nor/intel-spi.c | 24 ++++++-----
drivers/mtd/spi-nor/mtk-quadspi.c | 25 +++++++-----
drivers/mtd/spi-nor/nxp-spifi.c | 23 +++++++----
drivers/mtd/spi-nor/spi-nor.c | 76 ++++++++++++++++++++---------------
include/linux/mtd/spi-nor.h | 51 +++++++++++++----------
8 files changed, 166 insertions(+), 117 deletions(-)
diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c
index 009c1da8574c..2b7cabbb680c 100644
--- a/drivers/mtd/spi-nor/aspeed-smc.c
+++ b/drivers/mtd/spi-nor/aspeed-smc.c
@@ -320,7 +320,8 @@ static void aspeed_smc_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
mutex_unlock(&chip->controller->mutex);
}
-static int aspeed_smc_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+static int aspeed_smc_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
+ size_t len)
{
struct aspeed_smc_chip *chip = nor->priv;
@@ -331,8 +332,8 @@ static int aspeed_smc_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
return 0;
}
-static int aspeed_smc_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
- int len)
+static int aspeed_smc_write_reg(struct spi_nor *nor, u8 opcode, const u8 *buf,
+ size_t len)
{
struct aspeed_smc_chip *chip = nor->priv;
@@ -746,6 +747,15 @@ static int aspeed_smc_chip_setup_finish(struct aspeed_smc_chip *chip)
return 0;
}
+static const struct spi_nor_controller_ops aspeed_smc_controller_ops = {
+ .prepare = aspeed_smc_prep,
+ .unprepare = aspeed_smc_unprep,
+ .read_reg = aspeed_smc_read_reg,
+ .write_reg = aspeed_smc_write_reg,
+ .read = aspeed_smc_read_user,
+ .write = aspeed_smc_write_user,
+};
+
static int aspeed_smc_setup_flash(struct aspeed_smc_controller *controller,
struct device_node *np, struct resource *r)
{
@@ -805,12 +815,7 @@ static int aspeed_smc_setup_flash(struct aspeed_smc_controller *controller,
nor->dev = dev;
nor->priv = chip;
spi_nor_set_flash_node(nor, child);
- nor->read = aspeed_smc_read_user;
- nor->write = aspeed_smc_write_user;
- nor->read_reg = aspeed_smc_read_reg;
- nor->write_reg = aspeed_smc_write_reg;
- nor->prepare = aspeed_smc_prep;
- nor->unprepare = aspeed_smc_unprep;
+ nor->controller_ops = &aspeed_smc_controller_ops;
ret = aspeed_smc_chip_setup_init(chip, r);
if (ret)
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index 7bef63947b29..ebda612641a4 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -356,18 +356,19 @@ static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
static int cqspi_command_read(struct spi_nor *nor,
const u8 *txbuf, const unsigned n_tx,
- u8 *rxbuf, const unsigned n_rx)
+ u8 *rxbuf, size_t n_rx)
{
struct cqspi_flash_pdata *f_pdata = nor->priv;
struct cqspi_st *cqspi = f_pdata->cqspi;
void __iomem *reg_base = cqspi->iobase;
unsigned int rdreg;
unsigned int reg;
- unsigned int read_len;
+ size_t read_len;
int status;
if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
- dev_err(nor->dev, "Invalid input argument, len %d rxbuf 0x%p\n",
+ dev_err(nor->dev,
+ "Invalid input argument, len %zu rxbuf 0x%p\n",
n_rx, rxbuf);
return -EINVAL;
}
@@ -404,19 +405,19 @@ static int cqspi_command_read(struct spi_nor *nor,
}
static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
- const u8 *txbuf, const unsigned n_tx)
+ const u8 *txbuf, size_t n_tx)
{
struct cqspi_flash_pdata *f_pdata = nor->priv;
struct cqspi_st *cqspi = f_pdata->cqspi;
void __iomem *reg_base = cqspi->iobase;
unsigned int reg;
unsigned int data;
- u32 write_len;
+ size_t write_len;
int ret;
if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
dev_err(nor->dev,
- "Invalid input argument, cmdlen %d txbuf 0x%p\n",
+ "Invalid input argument, cmdlen %zu txbuf 0x%p\n",
n_tx, txbuf);
return -EINVAL;
}
@@ -1050,7 +1051,7 @@ static int cqspi_erase(struct spi_nor *nor, loff_t offs)
return ret;
/* Send write enable, then erase commands. */
- ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
if (ret)
return ret;
@@ -1080,7 +1081,7 @@ static void cqspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
mutex_unlock(&cqspi->bus_mutex);
}
-static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len)
{
int ret;
@@ -1091,7 +1092,8 @@ static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
return ret;
}
-static int cqspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+static int cqspi_write_reg(struct spi_nor *nor, u8 opcode, const u8 *buf,
+ size_t len)
{
int ret;
@@ -1216,6 +1218,16 @@ static void cqspi_request_mmap_dma(struct cqspi_st *cqspi)
init_completion(&cqspi->rx_dma_complete);
}
+static const struct spi_nor_controller_ops cqspi_controller_ops = {
+ .prepare = cqspi_prep,
+ .unprepare = cqspi_unprep,
+ .read_reg = cqspi_read_reg,
+ .write_reg = cqspi_write_reg,
+ .read = cqspi_read,
+ .write = cqspi_write,
+ .erase = cqspi_erase,
+};
+
static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
{
struct platform_device *pdev = cqspi->pdev;
@@ -1265,14 +1277,7 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
nor->dev = dev;
spi_nor_set_flash_node(nor, np);
nor->priv = f_pdata;
-
- nor->read_reg = cqspi_read_reg;
- nor->write_reg = cqspi_write_reg;
- nor->read = cqspi_read;
- nor->write = cqspi_write;
- nor->erase = cqspi_erase;
- nor->prepare = cqspi_prep;
- nor->unprepare = cqspi_unprep;
+ nor->controller_ops = &cqspi_controller_ops;
mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d",
dev_name(dev), cs);
diff --git a/drivers/mtd/spi-nor/hisi-sfc.c b/drivers/mtd/spi-nor/hisi-sfc.c
index c99ed9cdbf9c..a1258216f89d 100644
--- a/drivers/mtd/spi-nor/hisi-sfc.c
+++ b/drivers/mtd/spi-nor/hisi-sfc.c
@@ -177,7 +177,7 @@ static void hisi_spi_nor_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
}
static int hisi_spi_nor_op_reg(struct spi_nor *nor,
- u8 opcode, int len, u8 optype)
+ u8 opcode, size_t len, u8 optype)
{
struct hifmc_priv *priv = nor->priv;
struct hifmc_host *host = priv->host;
@@ -200,7 +200,7 @@ static int hisi_spi_nor_op_reg(struct spi_nor *nor,
}
static int hisi_spi_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
- int len)
+ size_t len)
{
struct hifmc_priv *priv = nor->priv;
struct hifmc_host *host = priv->host;
@@ -215,7 +215,7 @@ static int hisi_spi_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
}
static int hisi_spi_nor_write_reg(struct spi_nor *nor, u8 opcode,
- u8 *buf, int len)
+ const u8 *buf, size_t len)
{
struct hifmc_priv *priv = nor->priv;
struct hifmc_host *host = priv->host;
@@ -311,6 +311,15 @@ static ssize_t hisi_spi_nor_write(struct spi_nor *nor, loff_t to,
return len;
}
+static const struct spi_nor_controller_ops hisi_controller_ops = {
+ .prepare = hisi_spi_nor_prep,
+ .unprepare = hisi_spi_nor_unprep,
+ .read_reg = hisi_spi_nor_read_reg,
+ .write_reg = hisi_spi_nor_write_reg,
+ .read = hisi_spi_nor_read,
+ .write = hisi_spi_nor_write,
+};
+
/**
* Get spi flash device information and register it as a mtd device.
*/
@@ -357,13 +366,8 @@ static int hisi_spi_nor_register(struct device_node *np,
}
priv->host = host;
nor->priv = priv;
+ nor->controller_ops = &hisi_controller_ops;
- nor->prepare = hisi_spi_nor_prep;
- nor->unprepare = hisi_spi_nor_unprep;
- nor->read_reg = hisi_spi_nor_read_reg;
- nor->write_reg = hisi_spi_nor_write_reg;
- nor->read = hisi_spi_nor_read;
- nor->write = hisi_spi_nor_write;
ret = spi_nor_scan(nor, NULL, &hwcaps);
if (ret)
return ret;
diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c
index 43e55a2e9b27..dc38f19ac7ae 100644
--- a/drivers/mtd/spi-nor/intel-spi.c
+++ b/drivers/mtd/spi-nor/intel-spi.c
@@ -426,7 +426,7 @@ static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode, int optype)
return 0;
}
-static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, int len)
+static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, size_t len)
{
u32 val, status;
int ret;
@@ -469,7 +469,7 @@ static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, int len)
return 0;
}
-static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, int len,
+static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, size_t len,
int optype)
{
u32 val = 0, status;
@@ -535,7 +535,8 @@ static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, int len,
return 0;
}
-static int intel_spi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+static int intel_spi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
+ size_t len)
{
struct intel_spi *ispi = nor->priv;
int ret;
@@ -555,7 +556,8 @@ static int intel_spi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
return intel_spi_read_block(ispi, buf, len);
}
-static int intel_spi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+static int intel_spi_write_reg(struct spi_nor *nor, u8 opcode, const u8 *buf,
+ size_t len)
{
struct intel_spi *ispi = nor->priv;
int ret;
@@ -864,6 +866,14 @@ static void intel_spi_fill_partition(struct intel_spi *ispi,
}
}
+static const struct spi_nor_controller_ops intel_spi_controller_ops = {
+ .read_reg = intel_spi_read_reg,
+ .write_reg = intel_spi_write_reg,
+ .read = intel_spi_read,
+ .write = intel_spi_write,
+ .erase = intel_spi_erase,
+};
+
struct intel_spi *intel_spi_probe(struct device *dev,
struct resource *mem, const struct intel_spi_boardinfo *info)
{
@@ -897,11 +907,7 @@ struct intel_spi *intel_spi_probe(struct device *dev,
ispi->nor.dev = ispi->dev;
ispi->nor.priv = ispi;
- ispi->nor.read_reg = intel_spi_read_reg;
- ispi->nor.write_reg = intel_spi_write_reg;
- ispi->nor.read = intel_spi_read;
- ispi->nor.write = intel_spi_write;
- ispi->nor.erase = intel_spi_erase;
+ ispi->nor.controller_ops = &intel_spi_controller_ops;
ret = spi_nor_scan(&ispi->nor, NULL, &hwcaps);
if (ret) {
diff --git a/drivers/mtd/spi-nor/mtk-quadspi.c b/drivers/mtd/spi-nor/mtk-quadspi.c
index 34db01ab6cab..b1691680d174 100644
--- a/drivers/mtd/spi-nor/mtk-quadspi.c
+++ b/drivers/mtd/spi-nor/mtk-quadspi.c
@@ -151,9 +151,9 @@ static int mtk_nor_execute_cmd(struct mtk_nor *mtk_nor, u8 cmdval)
}
static int mtk_nor_do_tx_rx(struct mtk_nor *mtk_nor, u8 op,
- u8 *tx, int txlen, u8 *rx, int rxlen)
+ const u8 *tx, size_t txlen, u8 *rx, size_t rxlen)
{
- int len = 1 + txlen + rxlen;
+ size_t len = 1 + txlen + rxlen;
int i, ret, idx;
if (len > MTK_NOR_MAX_SHIFT)
@@ -193,7 +193,7 @@ static int mtk_nor_do_tx_rx(struct mtk_nor *mtk_nor, u8 op,
}
/* Do a WRSR (Write Status Register) command */
-static int mtk_nor_wr_sr(struct mtk_nor *mtk_nor, u8 sr)
+static int mtk_nor_wr_sr(struct mtk_nor *mtk_nor, const u8 sr)
{
writeb(sr, mtk_nor->base + MTK_NOR_PRGDATA5_REG);
writeb(8, mtk_nor->base + MTK_NOR_CNT_REG);
@@ -354,7 +354,7 @@ static ssize_t mtk_nor_write(struct spi_nor *nor, loff_t to, size_t len,
return len;
}
-static int mtk_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+static int mtk_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len)
{
int ret;
struct mtk_nor *mtk_nor = nor->priv;
@@ -376,8 +376,8 @@ static int mtk_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
return ret;
}
-static int mtk_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
- int len)
+static int mtk_nor_write_reg(struct spi_nor *nor, u8 opcode, const u8 *buf,
+ size_t len)
{
int ret;
struct mtk_nor *mtk_nor = nor->priv;
@@ -419,6 +419,13 @@ static int mtk_nor_enable_clk(struct mtk_nor *mtk_nor)
return 0;
}
+static const struct spi_nor_controller_ops mtk_controller_ops = {
+ .read_reg = mtk_nor_read_reg,
+ .write_reg = mtk_nor_write_reg,
+ .read = mtk_nor_read,
+ .write = mtk_nor_write,
+};
+
static int mtk_nor_init(struct mtk_nor *mtk_nor,
struct device_node *flash_node)
{
@@ -438,12 +445,8 @@ static int mtk_nor_init(struct mtk_nor *mtk_nor,
nor->dev = mtk_nor->dev;
nor->priv = mtk_nor;
spi_nor_set_flash_node(nor, flash_node);
+ nor->controller_ops = &mtk_controller_ops;
- /* fill the hooks to spi nor */
- nor->read = mtk_nor_read;
- nor->read_reg = mtk_nor_read_reg;
- nor->write = mtk_nor_write;
- nor->write_reg = mtk_nor_write_reg;
nor->mtd.name = "mtk_nor";
/* initialized with NULL */
ret = spi_nor_scan(nor, NULL, &hwcaps);
diff --git a/drivers/mtd/spi-nor/nxp-spifi.c b/drivers/mtd/spi-nor/nxp-spifi.c
index 4a871587392b..9a5b1a7c636a 100644
--- a/drivers/mtd/spi-nor/nxp-spifi.c
+++ b/drivers/mtd/spi-nor/nxp-spifi.c
@@ -123,7 +123,8 @@ static int nxp_spifi_set_memory_mode_on(struct nxp_spifi *spifi)
return ret;
}
-static int nxp_spifi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+static int nxp_spifi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
+ size_t len)
{
struct nxp_spifi *spifi = nor->priv;
u32 cmd;
@@ -145,7 +146,8 @@ static int nxp_spifi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
return nxp_spifi_wait_for_cmd(spifi);
}
-static int nxp_spifi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+static int nxp_spifi_write_reg(struct spi_nor *nor, u8 opcode, const u8 *buf,
+ size_t len)
{
struct nxp_spifi *spifi = nor->priv;
u32 cmd;
@@ -263,9 +265,18 @@ static int nxp_spifi_setup_memory_cmd(struct nxp_spifi *spifi)
static void nxp_spifi_dummy_id_read(struct spi_nor *nor)
{
u8 id[SPI_NOR_MAX_ID_LEN];
- nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
+ nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id,
+ SPI_NOR_MAX_ID_LEN);
}
+static const struct spi_nor_controller_ops nxp_spifi_controller_ops = {
+ .read_reg = nxp_spifi_read_reg,
+ .write_reg = nxp_spifi_write_reg,
+ .read = nxp_spifi_read,
+ .write = nxp_spifi_write,
+ .erase = nxp_spifi_erase,
+};
+
static int nxp_spifi_setup_flash(struct nxp_spifi *spifi,
struct device_node *np)
{
@@ -332,11 +343,7 @@ static int nxp_spifi_setup_flash(struct nxp_spifi *spifi,
spifi->nor.dev = spifi->dev;
spi_nor_set_flash_node(&spifi->nor, np);
spifi->nor.priv = spifi;
- spifi->nor.read = nxp_spifi_read;
- spifi->nor.write = nxp_spifi_write;
- spifi->nor.erase = nxp_spifi_erase;
- spifi->nor.read_reg = nxp_spifi_read_reg;
- spifi->nor.write_reg = nxp_spifi_write_reg;
+ spifi->nor.controller_ops = &nxp_spifi_controller_ops;
/*
* The first read on a hard reset isn't reliable so do a
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 1d8621d43160..b8c7ded0f145 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -338,7 +338,7 @@ static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
if (nor->spimem)
return spi_nor_spimem_read_data(nor, from, len, buf);
- return nor->read(nor, from, len, buf);
+ return nor->controller_ops->read(nor, from, len, buf);
}
/**
@@ -385,7 +385,7 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
if (nor->spimem)
return spi_nor_spimem_write_data(nor, to, len, buf);
- return nor->write(nor, to, len, buf);
+ return nor->controller_ops->write(nor, to, len, buf);
}
/*
@@ -406,7 +406,8 @@ static int read_sr(struct spi_nor *nor)
ret = spi_mem_exec_op(nor->spimem, &op);
} else {
- ret = nor->read_reg(nor, SPINOR_OP_RDSR, nor->bouncebuf, 1);
+ ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR,
+ nor->bouncebuf, 1);
}
if (ret < 0) {
@@ -435,7 +436,8 @@ static int read_fsr(struct spi_nor *nor)
ret = spi_mem_exec_op(nor->spimem, &op);
} else {
- ret = nor->read_reg(nor, SPINOR_OP_RDFSR, nor->bouncebuf, 1);
+ ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDFSR,
+ nor->bouncebuf, 1);
}
if (ret < 0) {
@@ -464,7 +466,8 @@ static int read_cr(struct spi_nor *nor)
ret = spi_mem_exec_op(nor->spimem, &op);
} else {
- ret = nor->read_reg(nor, SPINOR_OP_RDCR, nor->bouncebuf, 1);
+ ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDCR,
+ nor->bouncebuf, 1);
}
if (ret < 0) {
@@ -492,7 +495,8 @@ static int write_sr(struct spi_nor *nor, u8 val)
return spi_mem_exec_op(nor->spimem, &op);
}
- return nor->write_reg(nor, SPINOR_OP_WRSR, nor->bouncebuf, 1);
+ return nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR,
+ nor->bouncebuf, 1);
}
/*
@@ -511,7 +515,7 @@ static int write_enable(struct spi_nor *nor)
return spi_mem_exec_op(nor->spimem, &op);
}
- return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
+ return nor->controller_ops->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
}
/*
@@ -529,7 +533,7 @@ static int write_disable(struct spi_nor *nor)
return spi_mem_exec_op(nor->spimem, &op);
}
- return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
+ return nor->controller_ops->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
}
static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
@@ -631,8 +635,9 @@ static int macronix_set_4byte(struct spi_nor *nor, bool enable)
return spi_mem_exec_op(nor->spimem, &op);
}
- return nor->write_reg(nor, enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B,
- NULL, 0);
+ return nor->controller_ops->write_reg(nor, enable ? SPINOR_OP_EN4B :
+ SPINOR_OP_EX4B,
+ NULL, 0);
}
static int st_micron_set_4byte(struct spi_nor *nor, bool enable)
@@ -660,7 +665,8 @@ static int spansion_set_4byte(struct spi_nor *nor, bool enable)
return spi_mem_exec_op(nor->spimem, &op);
}
- return nor->write_reg(nor, SPINOR_OP_BRWR, nor->bouncebuf, 1);
+ return nor->controller_ops->write_reg(nor, SPINOR_OP_BRWR,
+ nor->bouncebuf, 1);
}
static int spi_nor_write_ear(struct spi_nor *nor, u8 ear)
@@ -677,7 +683,8 @@ static int spi_nor_write_ear(struct spi_nor *nor, u8 ear)
return spi_mem_exec_op(nor->spimem, &op);
}
- return nor->write_reg(nor, SPINOR_OP_WREAR, nor->bouncebuf, 1);
+ return nor->controller_ops->write_reg(nor, SPINOR_OP_WREAR,
+ nor->bouncebuf, 1);
}
static int winbond_set_4byte(struct spi_nor *nor, bool enable)
@@ -712,7 +719,7 @@ static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
return spi_mem_exec_op(nor->spimem, &op);
}
- return nor->read_reg(nor, SPINOR_OP_XRDSR, sr, 1);
+ return nor->controller_ops->read_reg(nor, SPINOR_OP_XRDSR, sr, 1);
}
static int s3an_sr_ready(struct spi_nor *nor)
@@ -740,7 +747,7 @@ static int spi_nor_clear_sr(struct spi_nor *nor)
return spi_mem_exec_op(nor->spimem, &op);
}
- return nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
+ return nor->controller_ops->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
}
static int spi_nor_sr_ready(struct spi_nor *nor)
@@ -774,7 +781,7 @@ static int spi_nor_clear_fsr(struct spi_nor *nor)
return spi_mem_exec_op(nor->spimem, &op);
}
- return nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
+ return nor->controller_ops->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
}
static int spi_nor_fsr_ready(struct spi_nor *nor)
@@ -871,7 +878,8 @@ static int erase_chip(struct spi_nor *nor)
return spi_mem_exec_op(nor->spimem, &op);
}
- return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
+ return nor->controller_ops->write_reg(nor, SPINOR_OP_CHIP_ERASE,
+ NULL, 0);
}
static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
@@ -880,10 +888,9 @@ static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
mutex_lock(&nor->lock);
- if (nor->prepare) {
- ret = nor->prepare(nor, ops);
+ if (nor->controller_ops && nor->controller_ops->prepare) {
+ ret = nor->controller_ops->prepare(nor, ops);
if (ret) {
- dev_err(nor->dev, "failed in the preparation.\n");
mutex_unlock(&nor->lock);
return ret;
}
@@ -893,8 +900,8 @@ static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
{
- if (nor->unprepare)
- nor->unprepare(nor, ops);
+ if (nor->controller_ops && nor->controller_ops->unprepare)
+ nor->controller_ops->unprepare(nor, ops);
mutex_unlock(&nor->lock);
}
@@ -935,8 +942,8 @@ static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
addr = spi_nor_convert_addr(nor, addr);
- if (nor->erase)
- return nor->erase(nor, addr);
+ if (nor->controller_ops && nor->controller_ops->erase)
+ return nor->controller_ops->erase(nor, addr);
if (nor->spimem) {
struct spi_mem_op op =
@@ -957,8 +964,8 @@ static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
addr >>= 8;
}
- return nor->write_reg(nor, nor->erase_opcode, nor->bouncebuf,
- nor->addr_width);
+ return nor->controller_ops->write_reg(nor, nor->erase_opcode,
+ nor->bouncebuf, nor->addr_width);
}
/**
@@ -1678,7 +1685,8 @@ static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
ret = spi_mem_exec_op(nor->spimem, &op);
} else {
- ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR,
+ sr_cr, 2);
}
if (ret < 0) {
@@ -1873,7 +1881,7 @@ static int spi_nor_write_sr2(struct spi_nor *nor, u8 *sr2)
return spi_mem_exec_op(nor->spimem, &op);
}
- return nor->write_reg(nor, SPINOR_OP_WRSR2, sr2, 1);
+ return nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR2, sr2, 1);
}
static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
@@ -1888,7 +1896,7 @@ static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
return spi_mem_exec_op(nor->spimem, &op);
}
- return nor->read_reg(nor, SPINOR_OP_RDSR2, sr2, 1);
+ return nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2, sr2, 1);
}
/**
@@ -2520,8 +2528,8 @@ static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
tmp = spi_mem_exec_op(nor->spimem, &op);
} else {
- tmp = nor->read_reg(nor, SPINOR_OP_RDID, id,
- SPI_NOR_MAX_ID_LEN);
+ tmp = nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id,
+ SPI_NOR_MAX_ID_LEN);
}
if (tmp < 0) {
dev_err(nor->dev, "error %d reading JEDEC ID\n", tmp);
@@ -2722,9 +2730,11 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
static int spi_nor_check(struct spi_nor *nor)
{
if (!nor->dev ||
- (!nor->spimem &&
- (!nor->read || !nor->write || !nor->read_reg ||
- !nor->write_reg))) {
+ (!nor->spimem && nor->controller_ops &&
+ (!nor->controller_ops->read ||
+ !nor->controller_ops->write ||
+ !nor->controller_ops->read_reg ||
+ !nor->controller_ops->write_reg))) {
pr_err("spi-nor: please fill all the necessary fields!\n");
return -EINVAL;
}
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index fc0b4b19c900..d1d736d3c8ab 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -466,6 +466,34 @@ enum spi_nor_pp_command_index {
struct spi_nor;
/**
+ * struct spi_nor_controller_ops - SPI NOR controller driver specific
+ * operations.
+ * @prepare: [OPTIONAL] do some preparations for the
+ * read/write/erase/lock/unlock operations.
+ * @unprepare: [OPTIONAL] do some post work after the
+ * read/write/erase/lock/unlock operations.
+ * @read_reg: read out the register.
+ * @write_reg: write data to the register.
+ * @read: read data from the SPI NOR.
+ * @write: write data to the SPI NOR.
+ * @erase: erase a sector of the SPI NOR at the offset @offs; if
+ * not provided by the driver, spi-nor will send the erase
+ * opcode via write_reg().
+ */
+struct spi_nor_controller_ops {
+ int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
+ void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
+ int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len);
+ int (*write_reg)(struct spi_nor *nor, u8 opcode, const u8 *buf,
+ size_t len);
+
+ ssize_t (*read)(struct spi_nor *nor, loff_t from, size_t len, u8 *buf);
+ ssize_t (*write)(struct spi_nor *nor, loff_t to, size_t len,
+ const u8 *buf);
+ int (*erase)(struct spi_nor *nor, loff_t offs);
+};
+
+/**
* struct spi_nor_locking_ops - SPI NOR locking methods
* @lock: lock a region of the SPI NOR.
* @unlock: unlock a region of the SPI NOR.
@@ -549,17 +577,7 @@ struct flash_info;
* @read_proto: the SPI protocol for read operations
* @write_proto: the SPI protocol for write operations
* @reg_proto the SPI protocol for read_reg/write_reg/erase operations
- * @prepare: [OPTIONAL] do some preparations for the
- * read/write/erase/lock/unlock operations
- * @unprepare: [OPTIONAL] do some post work after the
- * read/write/erase/lock/unlock operations
- * @read_reg: [DRIVER-SPECIFIC] read out the register
- * @write_reg: [DRIVER-SPECIFIC] write data to the register
- * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
- * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
- * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
- * at the offset @offs; if not provided by the driver,
- * spi-nor will send the erase opcode via write_reg()
+ * @controller_ops: SPI NOR controller driver specific operations.
* @clear_sr_bp: [FLASH-SPECIFIC] clears the Block Protection Bits from
* the SPI NOR Status Register.
* @params: [FLASH-SPECIFIC] SPI-NOR flash parameters and settings.
@@ -588,16 +606,7 @@ struct spi_nor {
bool sst_write_second;
u32 flags;
- int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
- void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
- int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
- int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
-
- ssize_t (*read)(struct spi_nor *nor, loff_t from,
- size_t len, u_char *read_buf);
- ssize_t (*write)(struct spi_nor *nor, loff_t to,
- size_t len, const u_char *write_buf);
- int (*erase)(struct spi_nor *nor, loff_t offs);
+ const struct spi_nor_controller_ops *controller_ops;
int (*clear_sr_bp)(struct spi_nor *nor);
struct spi_nor_flash_parameter params;
--
2.9.5
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 03/23] mtd: spi-nor: cadence-quadspi: Fix cqspi_command_read() definition
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 01/23] mtd: spi-nor: hisi-sfc: Drop nor->erase NULL assignment Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 02/23] mtd: spi-nor: Introduce 'struct spi_nor_controller_ops' Tudor.Ambarus
@ 2019-09-17 15:54 ` Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 04/23] mtd: spi-nor: Rename nor->params to nor->flash Tudor.Ambarus
` (20 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-17 15:54 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, Tudor.Ambarus, andrew, linux-kernel, vz,
linux-mediatek, joel, matthias.bgg, computersforpeace, dwmw2,
linux-arm-kernel
From: Tudor Ambarus <tudor.ambarus@microchip.com>
n_tx was never used, drop it. Replace 'const u8 *txbuf' with 'u8 opcode',
to comply with the SPI NOR int (*read_reg)() method. The 'const'
qualifier has no meaning for parameters passed by value, drop it.
Going furher, the opcode was passed to cqspi_calc_rdreg() and never used,
drop it.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/cadence-quadspi.c | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index ebda612641a4..22008fecd326 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -285,7 +285,7 @@ static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
return IRQ_HANDLED;
}
-static unsigned int cqspi_calc_rdreg(struct spi_nor *nor, const u8 opcode)
+static unsigned int cqspi_calc_rdreg(struct spi_nor *nor)
{
struct cqspi_flash_pdata *f_pdata = nor->priv;
u32 rdreg = 0;
@@ -354,8 +354,7 @@ static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
return cqspi_wait_idle(cqspi);
}
-static int cqspi_command_read(struct spi_nor *nor,
- const u8 *txbuf, const unsigned n_tx,
+static int cqspi_command_read(struct spi_nor *nor, u8 opcode,
u8 *rxbuf, size_t n_rx)
{
struct cqspi_flash_pdata *f_pdata = nor->priv;
@@ -373,9 +372,9 @@ static int cqspi_command_read(struct spi_nor *nor,
return -EINVAL;
}
- reg = txbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
+ reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
- rdreg = cqspi_calc_rdreg(nor, txbuf[0]);
+ rdreg = cqspi_calc_rdreg(nor);
writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
@@ -471,7 +470,7 @@ static int cqspi_read_setup(struct spi_nor *nor)
unsigned int reg;
reg = nor->read_opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
- reg |= cqspi_calc_rdreg(nor, nor->read_opcode);
+ reg |= cqspi_calc_rdreg(nor);
/* Setup dummy clock cycles */
dummy_clk = nor->read_dummy;
@@ -604,7 +603,7 @@ static int cqspi_write_setup(struct spi_nor *nor)
/* Set opcode. */
reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
writel(reg, reg_base + CQSPI_REG_WR_INSTR);
- reg = cqspi_calc_rdreg(nor, nor->program_opcode);
+ reg = cqspi_calc_rdreg(nor);
writel(reg, reg_base + CQSPI_REG_RD_INSTR);
reg = readl(reg_base + CQSPI_REG_SIZE);
@@ -1087,7 +1086,7 @@ static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len)
ret = cqspi_set_protocol(nor, 0);
if (!ret)
- ret = cqspi_command_read(nor, &opcode, 1, buf, len);
+ ret = cqspi_command_read(nor, opcode, buf, len);
return ret;
}
--
2.9.5
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 04/23] mtd: spi-nor: Rename nor->params to nor->flash
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
` (2 preceding siblings ...)
2019-09-17 15:54 ` [PATCH 03/23] mtd: spi-nor: cadence-quadspi: Fix cqspi_command_read() definition Tudor.Ambarus
@ 2019-09-17 15:54 ` Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 05/23] mtd: spi-nor: Rework read_sr() Tudor.Ambarus
` (19 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-17 15:54 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, Tudor.Ambarus, andrew, linux-kernel, vz,
linux-mediatek, joel, matthias.bgg, computersforpeace, dwmw2,
linux-arm-kernel
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Rename nor->params to nor->flash for a clearer separation
between the controller and flash operations.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 286 +++++++++++++++++++++---------------------
include/linux/mtd/spi-nor.h | 12 +-
2 files changed, 149 insertions(+), 149 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index b8c7ded0f145..7d0c1b598250 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -172,7 +172,7 @@ struct spi_nor_fixups {
int (*post_bfpt)(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header,
const struct sfdp_bfpt *bfpt,
- struct spi_nor_flash_parameter *params);
+ struct spi_nor_flash_parameter *flash);
void (*post_sfdp)(struct spi_nor *nor);
};
@@ -608,7 +608,7 @@ static void spi_nor_set_4byte_opcodes(struct spi_nor *nor)
nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
if (!spi_nor_has_uniform_erase(nor)) {
- struct spi_nor_erase_map *map = &nor->params.erase_map;
+ struct spi_nor_erase_map *map = &nor->flash.erase_map;
struct spi_nor_erase_type *erase;
int i;
@@ -927,10 +927,10 @@ static u32 s3an_convert_addr(struct spi_nor *nor, u32 addr)
static u32 spi_nor_convert_addr(struct spi_nor *nor, loff_t addr)
{
- if (!nor->params.convert_addr)
+ if (!nor->flash.convert_addr)
return addr;
- return nor->params.convert_addr(nor, addr);
+ return nor->flash.convert_addr(nor, addr);
}
/*
@@ -1140,7 +1140,7 @@ static int spi_nor_init_erase_cmd_list(struct spi_nor *nor,
struct list_head *erase_list,
u64 addr, u32 len)
{
- const struct spi_nor_erase_map *map = &nor->params.erase_map;
+ const struct spi_nor_erase_map *map = &nor->flash.erase_map;
const struct spi_nor_erase_type *erase, *prev_erase = NULL;
struct spi_nor_erase_region *region;
struct spi_nor_erase_command *cmd = NULL;
@@ -1628,7 +1628,7 @@ static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
if (ret)
return ret;
- ret = nor->params.locking_ops->lock(nor, ofs, len);
+ ret = nor->flash.locking_ops->lock(nor, ofs, len);
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
return ret;
@@ -1643,7 +1643,7 @@ static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
if (ret)
return ret;
- ret = nor->params.locking_ops->unlock(nor, ofs, len);
+ ret = nor->flash.locking_ops->unlock(nor, ofs, len);
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
return ret;
@@ -1658,7 +1658,7 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
if (ret)
return ret;
- ret = nor->params.locking_ops->is_locked(nor, ofs, len);
+ ret = nor->flash.locking_ops->is_locked(nor, ofs, len);
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
return ret;
@@ -2093,7 +2093,7 @@ static int
is25lp256_post_bfpt_fixups(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header,
const struct sfdp_bfpt *bfpt,
- struct spi_nor_flash_parameter *params)
+ struct spi_nor_flash_parameter *flash)
{
/*
* IS25LP256 supports 4B opcodes, but the BFPT advertises a
@@ -2115,7 +2115,7 @@ static int
mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header,
const struct sfdp_bfpt *bfpt,
- struct spi_nor_flash_parameter *params)
+ struct spi_nor_flash_parameter *flash)
{
/*
* MX25L25635F supports 4B opcodes but MX25L25635E does not.
@@ -2144,7 +2144,7 @@ static void gd25q256_default_init(struct spi_nor *nor)
* indicate the quad_enable method for this case, we need
* to set it in the default_init fixup hook.
*/
- nor->params.quad_enable = macronix_quad_enable;
+ nor->flash.quad_enable = macronix_quad_enable;
}
static struct spi_nor_fixups gd25q256_fixups = {
@@ -2777,7 +2777,7 @@ static int s3an_nor_setup(struct spi_nor *nor,
nor->mtd.erasesize = 8 * nor->page_size;
} else {
/* Flash in Default addressing mode */
- nor->params.convert_addr = s3an_convert_addr;
+ nor->flash.convert_addr = s3an_convert_addr;
nor->mtd.erasesize = nor->info->sector_size;
}
@@ -3017,7 +3017,7 @@ static int spi_nor_spimem_check_pp(struct spi_nor *nor,
static void
spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
{
- struct spi_nor_flash_parameter *params = &nor->params;
+ struct spi_nor_flash_parameter *flash = &nor->flash;
unsigned int cap;
/* DTR modes are not supported yet, mask them all. */
@@ -3034,7 +3034,7 @@ spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
rdidx = spi_nor_hwcaps_read2cmd(BIT(cap));
if (rdidx >= 0 &&
- spi_nor_spimem_check_readop(nor, ¶ms->reads[rdidx]))
+ spi_nor_spimem_check_readop(nor, &flash->reads[rdidx]))
*hwcaps &= ~BIT(cap);
ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap));
@@ -3042,7 +3042,7 @@ spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
continue;
if (spi_nor_spimem_check_pp(nor,
- ¶ms->page_programs[ppidx]))
+ &flash->page_programs[ppidx]))
*hwcaps &= ~BIT(cap);
}
}
@@ -3091,7 +3091,7 @@ spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
}
struct sfdp_bfpt_read {
- /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
+ /* The Fast Read x-y-z hardware capability in flash->hwcaps.mask. */
u32 hwcaps;
/*
@@ -3322,11 +3322,11 @@ static int
spi_nor_post_bfpt_fixups(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header,
const struct sfdp_bfpt *bfpt,
- struct spi_nor_flash_parameter *params)
+ struct spi_nor_flash_parameter *flash)
{
if (nor->info->fixups && nor->info->fixups->post_bfpt)
return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt,
- params);
+ flash);
return 0;
}
@@ -3336,7 +3336,7 @@ spi_nor_post_bfpt_fixups(struct spi_nor *nor,
* @nor: pointer to a 'struct spi_nor'
* @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
* the Basic Flash Parameter Table length and version
- * @params: pointer to the 'struct spi_nor_flash_parameter' to be
+ * @flash: pointer to the 'struct spi_nor_flash_parameter' to be
* filled
*
* The Basic Flash Parameter Table is the main and only mandatory table as
@@ -3363,9 +3363,9 @@ spi_nor_post_bfpt_fixups(struct spi_nor *nor,
*/
static int spi_nor_parse_bfpt(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header,
- struct spi_nor_flash_parameter *params)
+ struct spi_nor_flash_parameter *flash)
{
- struct spi_nor_erase_map *map = ¶ms->erase_map;
+ struct spi_nor_erase_map *map = &flash->erase_map;
struct spi_nor_erase_type *erase_type = map->erase_type;
struct sfdp_bfpt bfpt;
size_t len;
@@ -3406,23 +3406,23 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
}
/* Flash Memory Density (in bits). */
- params->size = bfpt.dwords[BFPT_DWORD(2)];
- if (params->size & BIT(31)) {
- params->size &= ~BIT(31);
+ flash->size = bfpt.dwords[BFPT_DWORD(2)];
+ if (flash->size & BIT(31)) {
+ flash->size &= ~BIT(31);
/*
- * Prevent overflows on params->size. Anyway, a NOR of 2^64
+ * Prevent overflows on flash->size. Anyway, a NOR of 2^64
* bits is unlikely to exist so this error probably means
* the BFPT we are reading is corrupted/wrong.
*/
- if (params->size > 63)
+ if (flash->size > 63)
return -EINVAL;
- params->size = 1ULL << params->size;
+ flash->size = 1ULL << flash->size;
} else {
- params->size++;
+ flash->size++;
}
- params->size >>= 3; /* Convert to bytes. */
+ flash->size >>= 3; /* Convert to bytes. */
/* Fast Read settings. */
for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
@@ -3430,13 +3430,13 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
struct spi_nor_read_command *read;
if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
- params->hwcaps.mask &= ~rd->hwcaps;
+ flash->hwcaps.mask &= ~rd->hwcaps;
continue;
}
- params->hwcaps.mask |= rd->hwcaps;
+ flash->hwcaps.mask |= rd->hwcaps;
cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
- read = ¶ms->reads[cmd];
+ read = &flash->reads[cmd];
half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
}
@@ -3446,7 +3446,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
* Erase Types defined in the bfpt table.
*/
erase_mask = 0;
- memset(¶ms->erase_map, 0, sizeof(params->erase_map));
+ memset(&flash->erase_map, 0, sizeof(flash->erase_map));
for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
u32 erasesize;
@@ -3465,7 +3465,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
spi_nor_set_erase_settings_from_bfpt(&erase_type[i], erasesize,
opcode, i);
}
- spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
+ spi_nor_init_uniform_erase_map(map, erase_mask, flash->size);
/*
* Sort all the map's Erase Types in ascending order with the smallest
* erase size being the first member in the erase_type array.
@@ -3483,43 +3483,42 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
/* Stop here if not JESD216 rev A or later. */
if (bfpt_header->length < BFPT_DWORD_MAX)
- return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt,
- params);
+ return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, flash);
/* Page size: this field specifies 'N' so the page size = 2^N bytes. */
- params->page_size = bfpt.dwords[BFPT_DWORD(11)];
- params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
- params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
- params->page_size = 1U << params->page_size;
+ flash->page_size = bfpt.dwords[BFPT_DWORD(11)];
+ flash->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
+ flash->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
+ flash->page_size = 1U << flash->page_size;
/* Quad Enable Requirements. */
switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
case BFPT_DWORD15_QER_NONE:
- params->quad_enable = NULL;
+ flash->quad_enable = NULL;
break;
case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
- params->quad_enable = spansion_no_read_cr_quad_enable;
+ flash->quad_enable = spansion_no_read_cr_quad_enable;
break;
case BFPT_DWORD15_QER_SR1_BIT6:
- params->quad_enable = macronix_quad_enable;
+ flash->quad_enable = macronix_quad_enable;
break;
case BFPT_DWORD15_QER_SR2_BIT7:
- params->quad_enable = sr2_bit7_quad_enable;
+ flash->quad_enable = sr2_bit7_quad_enable;
break;
case BFPT_DWORD15_QER_SR2_BIT1:
- params->quad_enable = spansion_read_cr_quad_enable;
+ flash->quad_enable = spansion_read_cr_quad_enable;
break;
default:
return -EINVAL;
}
- return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params);
+ return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, flash);
}
#define SMPT_CMD_ADDRESS_LEN_MASK GENMASK(23, 22)
@@ -3721,7 +3720,7 @@ spi_nor_region_check_overlay(struct spi_nor_erase_region *region,
/**
* spi_nor_init_non_uniform_erase_map() - initialize the non-uniform erase map
* @nor: pointer to a 'struct spi_nor'
- * @params: pointer to a duplicate 'struct spi_nor_flash_parameter' that is
+ * @flash: pointer to a duplicate 'struct spi_nor_flash_parameter' that is
* used for storing SFDP parsed data
* @smpt: pointer to the sector map parameter table
*
@@ -3729,10 +3728,10 @@ spi_nor_region_check_overlay(struct spi_nor_erase_region *region,
*/
static int
spi_nor_init_non_uniform_erase_map(struct spi_nor *nor,
- struct spi_nor_flash_parameter *params,
+ struct spi_nor_flash_parameter *flash,
const u32 *smpt)
{
- struct spi_nor_erase_map *map = ¶ms->erase_map;
+ struct spi_nor_erase_map *map = &flash->erase_map;
struct spi_nor_erase_type *erase = map->erase_type;
struct spi_nor_erase_region *region;
u64 offset;
@@ -3811,7 +3810,7 @@ spi_nor_init_non_uniform_erase_map(struct spi_nor *nor,
* spi_nor_parse_smpt() - parse Sector Map Parameter Table
* @nor: pointer to a 'struct spi_nor'
* @smpt_header: sector map parameter table header
- * @params: pointer to a duplicate 'struct spi_nor_flash_parameter'
+ * @flash: pointer to a duplicate 'struct spi_nor_flash_parameter'
* that is used for storing SFDP parsed data
*
* This table is optional, but when available, we parse it to identify the
@@ -3822,7 +3821,7 @@ spi_nor_init_non_uniform_erase_map(struct spi_nor *nor,
*/
static int spi_nor_parse_smpt(struct spi_nor *nor,
const struct sfdp_parameter_header *smpt_header,
- struct spi_nor_flash_parameter *params)
+ struct spi_nor_flash_parameter *flash)
{
const u32 *sector_map;
u32 *smpt;
@@ -3851,11 +3850,11 @@ static int spi_nor_parse_smpt(struct spi_nor *nor,
goto out;
}
- ret = spi_nor_init_non_uniform_erase_map(nor, params, sector_map);
+ ret = spi_nor_init_non_uniform_erase_map(nor, flash, sector_map);
if (ret)
goto out;
- spi_nor_regions_sort_erase_types(¶ms->erase_map);
+ spi_nor_regions_sort_erase_types(&flash->erase_map);
/* fall through */
out:
kfree(smpt);
@@ -3880,13 +3879,13 @@ struct sfdp_4bait {
* @nor: pointer to a 'struct spi_nor'.
* @param_header: pointer to the 'struct sfdp_parameter_header' describing
* the 4-Byte Address Instruction Table length and version.
- * @params: pointer to the 'struct spi_nor_flash_parameter' to be.
+ * @flash: pointer to the 'struct spi_nor_flash_parameter' to be.
*
* Return: 0 on success, -errno otherwise.
*/
static int spi_nor_parse_4bait(struct spi_nor *nor,
const struct sfdp_parameter_header *param_header,
- struct spi_nor_flash_parameter *params)
+ struct spi_nor_flash_parameter *flash)
{
static const struct sfdp_4bait reads[] = {
{ SNOR_HWCAPS_READ, BIT(0) },
@@ -3910,8 +3909,8 @@ static int spi_nor_parse_4bait(struct spi_nor *nor,
{ 0u /* not used */, BIT(11) },
{ 0u /* not used */, BIT(12) },
};
- struct spi_nor_pp_command *params_pp = params->page_programs;
- struct spi_nor_erase_map *map = ¶ms->erase_map;
+ struct spi_nor_pp_command *flash_pp = flash->page_programs;
+ struct spi_nor_erase_map *map = &flash->erase_map;
struct spi_nor_erase_type *erase_type = map->erase_type;
u32 *dwords;
size_t len;
@@ -3949,7 +3948,7 @@ static int spi_nor_parse_4bait(struct spi_nor *nor,
const struct sfdp_4bait *read = &reads[i];
discard_hwcaps |= read->hwcaps;
- if ((params->hwcaps.mask & read->hwcaps) &&
+ if ((flash->hwcaps.mask & read->hwcaps) &&
(dwords[0] & read->supported_bit))
read_hwcaps |= read->hwcaps;
}
@@ -3965,7 +3964,7 @@ static int spi_nor_parse_4bait(struct spi_nor *nor,
/*
* The 4 Byte Address Instruction (Optional) Table is the only
* SFDP table that indicates support for Page Program Commands.
- * Bypass the params->hwcaps.mask and consider 4BAIT the biggest
+ * Bypass the flash->hwcaps.mask and consider 4BAIT the biggest
* authority for specifying Page Program support.
*/
discard_hwcaps |= program->hwcaps;
@@ -4000,26 +3999,26 @@ static int spi_nor_parse_4bait(struct spi_nor *nor,
* Discard all operations from the 4-byte instruction set which are
* not supported by this memory.
*/
- params->hwcaps.mask &= ~discard_hwcaps;
- params->hwcaps.mask |= (read_hwcaps | pp_hwcaps);
+ flash->hwcaps.mask &= ~discard_hwcaps;
+ flash->hwcaps.mask |= (read_hwcaps | pp_hwcaps);
/* Use the 4-byte address instruction set. */
for (i = 0; i < SNOR_CMD_READ_MAX; i++) {
- struct spi_nor_read_command *read_cmd = ¶ms->reads[i];
+ struct spi_nor_read_command *read_cmd = &flash->reads[i];
read_cmd->opcode = spi_nor_convert_3to4_read(read_cmd->opcode);
}
/* 4BAIT is the only SFDP table that indicates page program support. */
if (pp_hwcaps & SNOR_HWCAPS_PP)
- spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP],
+ spi_nor_set_pp_settings(&flash_pp[SNOR_CMD_PP],
SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1);
if (pp_hwcaps & SNOR_HWCAPS_PP_1_1_4)
- spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP_1_1_4],
+ spi_nor_set_pp_settings(&flash_pp[SNOR_CMD_PP_1_1_4],
SPINOR_OP_PP_1_1_4_4B,
SNOR_PROTO_1_1_4);
if (pp_hwcaps & SNOR_HWCAPS_PP_1_4_4)
- spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP_1_4_4],
+ spi_nor_set_pp_settings(&flash_pp[SNOR_CMD_PP_1_4_4],
SPINOR_OP_PP_1_4_4_4B,
SNOR_PROTO_1_4_4);
@@ -4050,7 +4049,7 @@ static int spi_nor_parse_4bait(struct spi_nor *nor,
/**
* spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
* @nor: pointer to a 'struct spi_nor'
- * @params: pointer to the 'struct spi_nor_flash_parameter' to be
+ * @flash: pointer to the 'struct spi_nor_flash_parameter' to be
* filled
*
* The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
@@ -4062,7 +4061,7 @@ static int spi_nor_parse_4bait(struct spi_nor *nor,
* Return: 0 on success, -errno otherwise.
*/
static int spi_nor_parse_sfdp(struct spi_nor *nor,
- struct spi_nor_flash_parameter *params)
+ struct spi_nor_flash_parameter *flash)
{
const struct sfdp_parameter_header *param_header, *bfpt_header;
struct sfdp_parameter_header *param_headers = NULL;
@@ -4131,7 +4130,7 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor,
bfpt_header = param_header;
}
- err = spi_nor_parse_bfpt(nor, bfpt_header, params);
+ err = spi_nor_parse_bfpt(nor, bfpt_header, flash);
if (err)
goto exit;
@@ -4141,11 +4140,11 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor,
switch (SFDP_PARAM_HEADER_ID(param_header)) {
case SFDP_SECTOR_MAP_ID:
- err = spi_nor_parse_smpt(nor, param_header, params);
+ err = spi_nor_parse_smpt(nor, param_header, flash);
break;
case SFDP_4BAIT_ID:
- err = spi_nor_parse_4bait(nor, param_header, params);
+ err = spi_nor_parse_4bait(nor, param_header, flash);
break;
default:
@@ -4183,7 +4182,7 @@ static int spi_nor_select_read(struct spi_nor *nor,
if (cmd < 0)
return -EINVAL;
- read = &nor->params.reads[cmd];
+ read = &nor->flash.reads[cmd];
nor->read_opcode = read->opcode;
nor->read_proto = read->proto;
@@ -4214,7 +4213,7 @@ static int spi_nor_select_pp(struct spi_nor *nor,
if (cmd < 0)
return -EINVAL;
- pp = &nor->params.page_programs[cmd];
+ pp = &nor->flash.page_programs[cmd];
nor->program_opcode = pp->opcode;
nor->write_proto = pp->proto;
return 0;
@@ -4275,7 +4274,7 @@ spi_nor_select_uniform_erase(struct spi_nor_erase_map *map,
static int spi_nor_select_erase(struct spi_nor *nor)
{
- struct spi_nor_erase_map *map = &nor->params.erase_map;
+ struct spi_nor_erase_map *map = &nor->flash.erase_map;
const struct spi_nor_erase_type *erase = NULL;
struct mtd_info *mtd = &nor->mtd;
u32 wanted_size = nor->info->sector_size;
@@ -4324,7 +4323,7 @@ static int spi_nor_select_erase(struct spi_nor *nor)
static int spi_nor_default_setup(struct spi_nor *nor,
const struct spi_nor_hwcaps *hwcaps)
{
- struct spi_nor_flash_parameter *params = &nor->params;
+ struct spi_nor_flash_parameter *flash = &nor->flash;
u32 ignored_mask, shared_mask;
int err;
@@ -4332,7 +4331,7 @@ static int spi_nor_default_setup(struct spi_nor *nor,
* Keep only the hardware capabilities supported by both the SPI
* controller and the SPI flash memory.
*/
- shared_mask = hwcaps->mask & params->hwcaps.mask;
+ shared_mask = hwcaps->mask & flash->hwcaps.mask;
if (nor->spimem) {
/*
@@ -4385,36 +4384,36 @@ static int spi_nor_default_setup(struct spi_nor *nor,
static int spi_nor_setup(struct spi_nor *nor,
const struct spi_nor_hwcaps *hwcaps)
{
- if (!nor->params.setup)
+ if (!nor->flash.setup)
return 0;
- return nor->params.setup(nor, hwcaps);
+ return nor->flash.setup(nor, hwcaps);
}
static void macronix_set_default_init(struct spi_nor *nor)
{
- nor->params.quad_enable = macronix_quad_enable;
- nor->params.set_4byte = macronix_set_4byte;
+ nor->flash.quad_enable = macronix_quad_enable;
+ nor->flash.set_4byte = macronix_set_4byte;
}
static void st_micron_set_default_init(struct spi_nor *nor)
{
nor->flags |= SNOR_F_HAS_LOCK;
- nor->params.quad_enable = NULL;
- nor->params.set_4byte = st_micron_set_4byte;
+ nor->flash.quad_enable = NULL;
+ nor->flash.set_4byte = st_micron_set_4byte;
}
static void winbond_set_default_init(struct spi_nor *nor)
{
- nor->params.set_4byte = winbond_set_4byte;
+ nor->flash.set_4byte = winbond_set_4byte;
}
/**
- * spi_nor_manufacturer_init_params() - Initialize the flash's parameters and
- * settings based on MFR register and ->default_init() hook.
+ * spi_nor_manufacturer_init_flash_params() - Initialize the flash's
+ * parameters and settings based on MFR register and ->default_init() hook.
* @nor: pointer to a 'struct spi-nor'.
*/
-static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
+static void spi_nor_manufacturer_init_flash_params(struct spi_nor *nor)
{
/* Init flash parameters based on MFR */
switch (JEDEC_MFR(nor->info)) {
@@ -4440,93 +4439,93 @@ static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
}
/**
- * spi_nor_sfdp_init_params() - Initialize the flash's parameters and settings
- * based on JESD216 SFDP standard.
+ * spi_nor_sfdp_init_flash_params() - Initialize the flash's parameters and
+ * settings based on JESD216 SFDP standard.
* @nor: pointer to a 'struct spi-nor'.
*
* The method has a roll-back mechanism: in case the SFDP parsing fails, the
* legacy flash parameters and settings will be restored.
*/
-static void spi_nor_sfdp_init_params(struct spi_nor *nor)
+static void spi_nor_sfdp_init_flash_params(struct spi_nor *nor)
{
- struct spi_nor_flash_parameter sfdp_params;
+ struct spi_nor_flash_parameter sfdp_flash;
- memcpy(&sfdp_params, &nor->params, sizeof(sfdp_params));
+ memcpy(&sfdp_flash, &nor->flash, sizeof(sfdp_flash));
- if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
+ if (spi_nor_parse_sfdp(nor, &sfdp_flash)) {
nor->addr_width = 0;
nor->flags &= ~SNOR_F_4B_OPCODES;
} else {
- memcpy(&nor->params, &sfdp_params, sizeof(nor->params));
+ memcpy(&nor->flash, &sfdp_flash, sizeof(nor->flash));
}
}
/**
- * spi_nor_info_init_params() - Initialize the flash's parameters and settings
- * based on nor->info data.
+ * spi_nor_info_init_flash_params() - Initialize the flash's parameters and
+ * settings based on nor->info data.
* @nor: pointer to a 'struct spi-nor'.
*/
-static void spi_nor_info_init_params(struct spi_nor *nor)
+static void spi_nor_info_init_flash_params(struct spi_nor *nor)
{
- struct spi_nor_flash_parameter *params = &nor->params;
- struct spi_nor_erase_map *map = ¶ms->erase_map;
+ struct spi_nor_flash_parameter *flash = &nor->flash;
+ struct spi_nor_erase_map *map = &flash->erase_map;
const struct flash_info *info = nor->info;
struct device_node *np = spi_nor_get_flash_node(nor);
u8 i, erase_mask;
/* Initialize legacy flash parameters and settings. */
- params->quad_enable = spansion_quad_enable;
- params->set_4byte = spansion_set_4byte;
- params->setup = spi_nor_default_setup;
+ flash->quad_enable = spansion_quad_enable;
+ flash->set_4byte = spansion_set_4byte;
+ flash->setup = spi_nor_default_setup;
/* Set SPI NOR sizes. */
- params->size = (u64)info->sector_size * info->n_sectors;
- params->page_size = info->page_size;
+ flash->size = (u64)info->sector_size * info->n_sectors;
+ flash->page_size = info->page_size;
if (!(info->flags & SPI_NOR_NO_FR)) {
/* Default to Fast Read for DT and non-DT platform devices. */
- params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
+ flash->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
/* Mask out Fast Read if not requested at DT instantiation. */
if (np && !of_property_read_bool(np, "m25p,fast-read"))
- params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
+ flash->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
}
/* (Fast) Read settings. */
- params->hwcaps.mask |= SNOR_HWCAPS_READ;
- spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
+ flash->hwcaps.mask |= SNOR_HWCAPS_READ;
+ spi_nor_set_read_settings(&flash->reads[SNOR_CMD_READ],
0, 0, SPINOR_OP_READ,
SNOR_PROTO_1_1_1);
- if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST)
- spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],
+ if (flash->hwcaps.mask & SNOR_HWCAPS_READ_FAST)
+ spi_nor_set_read_settings(&flash->reads[SNOR_CMD_READ_FAST],
0, 8, SPINOR_OP_READ_FAST,
SNOR_PROTO_1_1_1);
if (info->flags & SPI_NOR_DUAL_READ) {
- params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
- spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2],
+ flash->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
+ spi_nor_set_read_settings(&flash->reads[SNOR_CMD_READ_1_1_2],
0, 8, SPINOR_OP_READ_1_1_2,
SNOR_PROTO_1_1_2);
}
if (info->flags & SPI_NOR_QUAD_READ) {
- params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
- spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
+ flash->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
+ spi_nor_set_read_settings(&flash->reads[SNOR_CMD_READ_1_1_4],
0, 8, SPINOR_OP_READ_1_1_4,
SNOR_PROTO_1_1_4);
}
if (info->flags & SPI_NOR_OCTAL_READ) {
- params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
- spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8],
+ flash->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+ spi_nor_set_read_settings(&flash->reads[SNOR_CMD_READ_1_1_8],
0, 8, SPINOR_OP_READ_1_1_8,
SNOR_PROTO_1_1_8);
}
/* Page Program settings. */
- params->hwcaps.mask |= SNOR_HWCAPS_PP;
- spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
+ flash->hwcaps.mask |= SNOR_HWCAPS_PP;
+ spi_nor_set_pp_settings(&flash->page_programs[SNOR_CMD_PP],
SPINOR_OP_PP, SNOR_PROTO_1_1_1);
/*
@@ -4549,7 +4548,7 @@ static void spi_nor_info_init_params(struct spi_nor *nor)
erase_mask |= BIT(i);
spi_nor_set_erase_type(&map->erase_type[i], info->sector_size,
SPINOR_OP_SE);
- spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
+ spi_nor_init_uniform_erase_map(map, erase_mask, flash->size);
}
static void spansion_post_sfdp_fixups(struct spi_nor *nor)
@@ -4567,7 +4566,7 @@ static void spansion_post_sfdp_fixups(struct spi_nor *nor)
static void s3an_post_sfdp_fixups(struct spi_nor *nor)
{
- nor->params.setup = s3an_nor_setup;
+ nor->flash.setup = s3an_nor_setup;
}
/**
@@ -4599,24 +4598,25 @@ static void spi_nor_post_sfdp_fixups(struct spi_nor *nor)
}
/**
- * spi_nor_late_init_params() - Late initialization of default flash parameters.
+ * spi_nor_late_init_flash_params() - Late initialization of default flash
+ * parameters.
* @nor: pointer to a 'struct spi_nor'
*
* Used to set default flash parameters and settings when the ->default_init()
* hook or the SFDP parser let voids.
*/
-static void spi_nor_late_init_params(struct spi_nor *nor)
+static void spi_nor_late_init_flash_params(struct spi_nor *nor)
{
/*
* NOR protection support. When locking_ops are not provided, we pick
* the default ones.
*/
- if (nor->flags & SNOR_F_HAS_LOCK && !nor->params.locking_ops)
- nor->params.locking_ops = &stm_locking_ops;
+ if (nor->flags & SNOR_F_HAS_LOCK && !nor->flash.locking_ops)
+ nor->flash.locking_ops = &stm_locking_ops;
}
/**
- * spi_nor_init_params() - Initialize the flash's parameters and settings.
+ * spi_nor_init_flash_params() - Initialize the flash's parameters and settings.
* @nor: pointer to a 'struct spi-nor'.
*
* The flash parameters and settings are initialized based on a sequence of
@@ -4624,18 +4624,18 @@ static void spi_nor_late_init_params(struct spi_nor *nor)
*
* 1/ Default flash parameters initialization. The initializations are done
* based on nor->info data:
- * spi_nor_info_init_params()
+ * spi_nor_info_init_flash_params()
*
* which can be overwritten by:
* 2/ Manufacturer flash parameters initialization. The initializations are
* done based on MFR register, or when the decisions can not be done solely
* based on MFR, by using specific flash_info tweeks, ->default_init():
- * spi_nor_manufacturer_init_params()
+ * spi_nor_manufacturer_init_flash_params()
*
* which can be overwritten by:
* 3/ SFDP flash parameters initialization. JESD216 SFDP is a standard and
* should be more accurate that the above.
- * spi_nor_sfdp_init_params()
+ * spi_nor_sfdp_init_flash_params()
*
* Please note that there is a ->post_bfpt() fixup hook that can overwrite
* the flash parameters and settings immediately after parsing the Basic
@@ -4649,22 +4649,22 @@ static void spi_nor_late_init_params(struct spi_nor *nor)
* spi_nor_post_sfdp_fixups()
*
* 5/ Late default flash parameters initialization, used when the
- * ->default_init() hook or the SFDP parser do not set specific params.
- * spi_nor_late_init_params()
+ * ->default_init() hook or the SFDP parser do not set specific flash params.
+ * spi_nor_late_init_flash_params()
*/
-static void spi_nor_init_params(struct spi_nor *nor)
+static void spi_nor_init_flash_params(struct spi_nor *nor)
{
- spi_nor_info_init_params(nor);
+ spi_nor_info_init_flash_params(nor);
- spi_nor_manufacturer_init_params(nor);
+ spi_nor_manufacturer_init_flash_params(nor);
if ((nor->info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) &&
!(nor->info->flags & SPI_NOR_SKIP_SFDP))
- spi_nor_sfdp_init_params(nor);
+ spi_nor_sfdp_init_flash_params(nor);
spi_nor_post_sfdp_fixups(nor);
- spi_nor_late_init_params(nor);
+ spi_nor_late_init_flash_params(nor);
}
/**
@@ -4675,14 +4675,14 @@ static void spi_nor_init_params(struct spi_nor *nor)
*/
static int spi_nor_quad_enable(struct spi_nor *nor)
{
- if (!nor->params.quad_enable)
+ if (!nor->flash.quad_enable)
return 0;
if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 ||
spi_nor_get_protocol_width(nor->write_proto) == 4))
return 0;
- return nor->params.quad_enable(nor);
+ return nor->flash.quad_enable(nor);
}
static int spi_nor_init(struct spi_nor *nor)
@@ -4690,7 +4690,7 @@ static int spi_nor_init(struct spi_nor *nor)
int err;
if (nor->clear_sr_bp) {
- if (nor->params.quad_enable == spansion_quad_enable)
+ if (nor->flash.quad_enable == spansion_quad_enable)
nor->clear_sr_bp = spi_nor_spansion_clear_sr_bp;
err = nor->clear_sr_bp(nor);
@@ -4717,7 +4717,7 @@ static int spi_nor_init(struct spi_nor *nor)
*/
WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
"enabling reset hack; may not recover from unexpected reboots\n");
- nor->params.set_4byte(nor, true);
+ nor->flash.set_4byte(nor, true);
}
return 0;
@@ -4741,7 +4741,7 @@ void spi_nor_restore(struct spi_nor *nor)
/* restore the addressing mode */
if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES) &&
nor->flags & SNOR_F_BROKEN_RESET)
- nor->params.set_4byte(nor, false);
+ nor->flash.set_4byte(nor, false);
}
EXPORT_SYMBOL_GPL(spi_nor_restore);
@@ -4841,7 +4841,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
struct device *dev = nor->dev;
struct mtd_info *mtd = &nor->mtd;
struct device_node *np = spi_nor_get_flash_node(nor);
- struct spi_nor_flash_parameter *params = &nor->params;
+ struct spi_nor_flash_parameter *flash = &nor->flash;
int ret;
int i;
@@ -4900,7 +4900,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
nor->clear_sr_bp = spi_nor_clear_sr_bp;
/* Init flash parameters based on flash_info struct and SFDP */
- spi_nor_init_params(nor);
+ spi_nor_init_flash_params(nor);
if (!mtd->name)
mtd->name = dev_name(dev);
@@ -4908,12 +4908,12 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
mtd->type = MTD_NORFLASH;
mtd->writesize = 1;
mtd->flags = MTD_CAP_NORFLASH;
- mtd->size = params->size;
+ mtd->size = flash->size;
mtd->_erase = spi_nor_erase;
mtd->_read = spi_nor_read;
mtd->_resume = spi_nor_resume;
- if (nor->params.locking_ops) {
+ if (nor->flash.locking_ops) {
mtd->_lock = spi_nor_lock;
mtd->_unlock = spi_nor_unlock;
mtd->_is_locked = spi_nor_is_locked;
@@ -4938,7 +4938,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
mtd->flags |= MTD_NO_ERASE;
mtd->dev.parent = dev;
- nor->page_size = params->page_size;
+ nor->page_size = flash->page_size;
mtd->writebufsize = nor->page_size;
if (of_property_read_bool(np, "broken-flash-reset"))
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index d1d736d3c8ab..12961b157743 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -580,10 +580,10 @@ struct flash_info;
* @controller_ops: SPI NOR controller driver specific operations.
* @clear_sr_bp: [FLASH-SPECIFIC] clears the Block Protection Bits from
* the SPI NOR Status Register.
- * @params: [FLASH-SPECIFIC] SPI-NOR flash parameters and settings.
- * The structure includes legacy flash parameters and
- * settings that can be overwritten by the spi_nor_fixups
- * hooks, or dynamically when parsing the SFDP tables.
+ * @flash: SPI-NOR flash parameters and settings. The structure
+ * includes default flash parameters and settings that can
+ * be overwritten by the spi_nor_fixups hooks, or
+ * dynamically when parsing the SFDP tables.
* @priv: the private data
*/
struct spi_nor {
@@ -609,7 +609,7 @@ struct spi_nor {
const struct spi_nor_controller_ops *controller_ops;
int (*clear_sr_bp)(struct spi_nor *nor);
- struct spi_nor_flash_parameter params;
+ struct spi_nor_flash_parameter flash;
void *priv;
};
@@ -640,7 +640,7 @@ spi_nor_region_mark_overlay(struct spi_nor_erase_region *region)
static bool __maybe_unused spi_nor_has_uniform_erase(const struct spi_nor *nor)
{
- return !!nor->params.erase_map.uniform_erase_type;
+ return !!nor->flash.erase_map.uniform_erase_type;
}
static inline void spi_nor_set_flash_node(struct spi_nor *nor,
--
2.9.5
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 05/23] mtd: spi-nor: Rework read_sr()
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
` (3 preceding siblings ...)
2019-09-17 15:54 ` [PATCH 04/23] mtd: spi-nor: Rename nor->params to nor->flash Tudor.Ambarus
@ 2019-09-17 15:54 ` Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 06/23] mtd: spi-nor: Rework read_fsr() Tudor.Ambarus
` (18 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-17 15:54 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, Tudor.Ambarus, andrew, linux-kernel, vz,
linux-mediatek, joel, matthias.bgg, computersforpeace, dwmw2,
linux-arm-kernel
From: Tudor Ambarus <tudor.ambarus@microchip.com>
static int read_sr(struct spi_nor *nor)
becomes
static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
The new function returns 0 on success and -errno otherwise.
We let the callers pass the pointer to the buffer where the
value of the Status Register will be written. This way we avoid
the casts between int and u8, which can be confusing.
Prepend spi_nor_ to the function name, all functions should begin
with that.
S/pr_err/dev_err and drop duplicated dev_err in callers, in case the
function returns error.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 131 +++++++++++++++++++++---------------------
1 file changed, 65 insertions(+), 66 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 7d0c1b598250..a23783641146 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -388,12 +388,14 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
return nor->controller_ops->write(nor, to, len, buf);
}
-/*
- * Read the status register, returning its value in the location
- * Return the status register value.
- * Returns negative if error occurred.
+/**
+ * spi_nor_read_sr() - Read the Status Register.
+ * @nor: pointer to 'struct spi_nor'
+ * @sr: buffer where the value of the Status Register will be written.
+ *
+ * Return: 0 on success, -errno otherwise.
*/
-static int read_sr(struct spi_nor *nor)
+static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
{
int ret;
@@ -402,20 +404,17 @@ static int read_sr(struct spi_nor *nor)
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 1),
SPI_MEM_OP_NO_ADDR,
SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 1));
+ SPI_MEM_OP_DATA_IN(1, sr, 1));
ret = spi_mem_exec_op(nor->spimem, &op);
} else {
- ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR,
- nor->bouncebuf, 1);
+ ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR, sr, 1);
}
- if (ret < 0) {
- pr_err("error %d reading SR\n", (int) ret);
- return ret;
- }
+ if (ret)
+ dev_err(nor->dev, "error %d reading SR\n", ret);
- return nor->bouncebuf[0];
+ return ret;
}
/*
@@ -752,12 +751,14 @@ static int spi_nor_clear_sr(struct spi_nor *nor)
static int spi_nor_sr_ready(struct spi_nor *nor)
{
- int sr = read_sr(nor);
- if (sr < 0)
- return sr;
+ int ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
+
+ if (ret)
+ return ret;
- if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
- if (sr & SR_E_ERR)
+ if (nor->flags & SNOR_F_USE_CLSR &&
+ nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
+ if (nor->bouncebuf[0] & SR_E_ERR)
dev_err(nor->dev, "Erase Error occurred\n");
else
dev_err(nor->dev, "Programming Error occurred\n");
@@ -766,7 +767,7 @@ static int spi_nor_sr_ready(struct spi_nor *nor)
return -EIO;
}
- return !(sr & SR_WIP);
+ return !(nor->bouncebuf[0] & SR_WIP);
}
static int spi_nor_clear_fsr(struct spi_nor *nor)
@@ -1341,11 +1342,11 @@ static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
if (ret)
return ret;
- ret = read_sr(nor);
- if (ret < 0)
+ ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
+ if (ret)
return ret;
- return ((ret & mask) != (status_new & mask)) ? -EIO : 0;
+ return ((nor->bouncebuf[0] & mask) != (status_new & mask)) ? -EIO : 0;
}
static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
@@ -1440,16 +1441,18 @@ static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
{
struct mtd_info *mtd = &nor->mtd;
- int status_old, status_new;
+ int ret, status_old, status_new;
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
u8 shift = ffs(mask) - 1, pow, val;
loff_t lock_len;
bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
bool use_top;
- status_old = read_sr(nor);
- if (status_old < 0)
- return status_old;
+ ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
+ if (ret)
+ return ret;
+
+ status_old = nor->bouncebuf[0];
/* If nothing in our range is unlocked, we don't need to do anything */
if (stm_is_locked_sr(nor, ofs, len, status_old))
@@ -1520,16 +1523,18 @@ static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
{
struct mtd_info *mtd = &nor->mtd;
- int status_old, status_new;
+ int ret, status_old, status_new;
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
u8 shift = ffs(mask) - 1, pow, val;
loff_t lock_len;
bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
bool use_top;
- status_old = read_sr(nor);
- if (status_old < 0)
- return status_old;
+ ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
+ if (ret)
+ return ret;
+
+ status_old = nor->bouncebuf[0];
/* If nothing in our range is locked, we don't need to do anything */
if (stm_is_unlocked_sr(nor, ofs, len, status_old))
@@ -1604,13 +1609,12 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
*/
static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
{
- int status;
+ int ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
- status = read_sr(nor);
- if (status < 0)
- return status;
+ if (ret)
+ return ret;
- return stm_is_locked_sr(nor, ofs, len, status);
+ return stm_is_locked_sr(nor, ofs, len, nor->bouncebuf[0]);
}
static const struct spi_nor_locking_ops stm_locking_ops = {
@@ -1717,24 +1721,28 @@ static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
*/
static int macronix_quad_enable(struct spi_nor *nor)
{
- int ret, val;
+ int ret;
- val = read_sr(nor);
- if (val < 0)
- return val;
- if (val & SR_QUAD_EN_MX)
+ ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
+ if (ret)
+ return ret;
+
+ if (nor->bouncebuf[0] & SR_QUAD_EN_MX)
return 0;
write_enable(nor);
- write_sr(nor, val | SR_QUAD_EN_MX);
+ write_sr(nor, nor->bouncebuf[0] | SR_QUAD_EN_MX);
ret = spi_nor_wait_till_ready(nor);
if (ret)
return ret;
- ret = read_sr(nor);
- if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
+ ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
+ if (ret)
+ return ret;
+
+ if (!(nor->bouncebuf[0] & SR_QUAD_EN_MX)) {
dev_err(nor->dev, "Macronix Quad bit not set\n");
return -EINVAL;
}
@@ -1805,12 +1813,10 @@ static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
int ret;
/* Keep the current value of the Status Register. */
- ret = read_sr(nor);
- if (ret < 0) {
- dev_err(nor->dev, "error while reading status register\n");
- return -EINVAL;
- }
- sr_cr[0] = ret;
+ ret = spi_nor_read_sr(nor, &sr_cr[0]);
+ if (ret)
+ return ret;
+
sr_cr[1] = CR_QUAD_EN_SPAN;
return write_sr_cr(nor, sr_cr);
@@ -1848,12 +1854,9 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
sr_cr[1] = ret | CR_QUAD_EN_SPAN;
/* Keep the current value of the Status Register. */
- ret = read_sr(nor);
- if (ret < 0) {
- dev_err(dev, "error while reading status register\n");
- return -EINVAL;
- }
- sr_cr[0] = ret;
+ ret = spi_nor_read_sr(nor, &sr_cr[0]);
+ if (ret)
+ return ret;
ret = write_sr_cr(nor, sr_cr);
if (ret)
@@ -1964,15 +1967,13 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor)
int ret;
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
- ret = read_sr(nor);
- if (ret < 0) {
- dev_err(nor->dev, "error while reading status register\n");
+ ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
+ if (ret)
return ret;
- }
write_enable(nor);
- ret = write_sr(nor, ret & ~mask);
+ ret = write_sr(nor, nor->bouncebuf[0] & ~mask);
if (ret) {
dev_err(nor->dev, "write to status register failed\n");
return ret;
@@ -2018,13 +2019,11 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor)
if (ret & CR_QUAD_EN_SPAN) {
sr_cr[1] = ret;
- ret = read_sr(nor);
- if (ret < 0) {
- dev_err(nor->dev,
- "error while reading status register\n");
+ ret = spi_nor_read_sr(nor, &sr_cr[0]);
+ if (ret)
return ret;
- }
- sr_cr[0] = ret & ~mask;
+
+ sr_cr[0] &= ~mask;
ret = write_sr_cr(nor, sr_cr);
if (ret)
--
2.9.5
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 06/23] mtd: spi-nor: Rework read_fsr()
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
` (4 preceding siblings ...)
2019-09-17 15:54 ` [PATCH 05/23] mtd: spi-nor: Rework read_sr() Tudor.Ambarus
@ 2019-09-17 15:55 ` Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 07/23] mtd: spi-nor: Rework read_cr() Tudor.Ambarus
` (17 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-17 15:55 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, Tudor.Ambarus, andrew, linux-kernel, vz,
linux-mediatek, joel, matthias.bgg, computersforpeace, dwmw2,
linux-arm-kernel
From: Tudor Ambarus <tudor.ambarus@microchip.com>
static int read_fsr(struct spi_nor *nor)
becomes
static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
The new function returns 0 on success and -errno otherwise.
We let the callers pass the pointer to the buffer where the
value of the Flag Status Register will be written. This way
we avoid the casts between int and u8, which can be confusing.
Prepend spi_nor_ to the function name, all functions should begin
with that.
S/pr_err/dev_err and drop duplicated dev_err in callers, in case the
function returns error.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 42 ++++++++++++++++++++++--------------------
1 file changed, 22 insertions(+), 20 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index a23783641146..8cd1cadcb8b1 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -417,12 +417,15 @@ static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
return ret;
}
-/*
- * Read the flag status register, returning its value in the location
- * Return the status register value.
- * Returns negative if error occurred.
+/**
+ * spi_nor_read_fsr() - Read the Flag Status Register.
+ * @nor: pointer to 'struct spi_nor'
+ * @fsr: buffer where the value of the Flag Status Register will be
+ * written.
+ *
+ * Return: 0 on success, -errno otherwise.
*/
-static int read_fsr(struct spi_nor *nor)
+static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
{
int ret;
@@ -431,20 +434,18 @@ static int read_fsr(struct spi_nor *nor)
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 1),
SPI_MEM_OP_NO_ADDR,
SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 1));
+ SPI_MEM_OP_DATA_IN(1, fsr, 1));
ret = spi_mem_exec_op(nor->spimem, &op);
} else {
ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDFSR,
- nor->bouncebuf, 1);
+ fsr, 1);
}
- if (ret < 0) {
- pr_err("error %d reading FSR\n", ret);
- return ret;
- }
+ if (ret)
+ dev_err(nor->dev, "error %d reading FSR\n", ret);
- return nor->bouncebuf[0];
+ return ret;
}
/*
@@ -787,25 +788,26 @@ static int spi_nor_clear_fsr(struct spi_nor *nor)
static int spi_nor_fsr_ready(struct spi_nor *nor)
{
- int fsr = read_fsr(nor);
- if (fsr < 0)
- return fsr;
+ int ret = spi_nor_read_fsr(nor, &nor->bouncebuf[0]);
+
+ if (ret)
+ return ret;
- if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
- if (fsr & FSR_E_ERR)
+ if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) {
+ if (nor->bouncebuf[0] & FSR_E_ERR)
dev_err(nor->dev, "Erase operation failed.\n");
else
dev_err(nor->dev, "Program operation failed.\n");
- if (fsr & FSR_PT_ERR)
+ if (nor->bouncebuf[0] & FSR_PT_ERR)
dev_err(nor->dev,
- "Attempted to modify a protected sector.\n");
+ "Attempted to modify a protected sector.\n");
spi_nor_clear_fsr(nor);
return -EIO;
}
- return fsr & FSR_READY;
+ return nor->bouncebuf[0] & FSR_READY;
}
static int spi_nor_ready(struct spi_nor *nor)
--
2.9.5
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 07/23] mtd: spi-nor: Rework read_cr()
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
` (5 preceding siblings ...)
2019-09-17 15:55 ` [PATCH 06/23] mtd: spi-nor: Rework read_fsr() Tudor.Ambarus
@ 2019-09-17 15:55 ` Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 08/23] mtd: spi-nor: Rework write_enable/disable() Tudor.Ambarus
` (16 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-17 15:55 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, Tudor.Ambarus, andrew, linux-kernel, vz,
linux-mediatek, joel, matthias.bgg, computersforpeace, dwmw2,
linux-arm-kernel
From: Tudor Ambarus <tudor.ambarus@microchip.com>
static int read_cr(struct spi_nor *nor)
becomes
static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
The new function returns 0 on success and -errno otherwise.
We let the callers pass the pointer to the buffer where the
value of the Configuration Register will be written. This way
we avoid the casts between int and u8, which can be confusing.
Prepend spi_nor_ to the function name, all functions should begin
with that.
Vendors are using both the "Configuration Register" and the
"Status Register 2" terminology when referring to the second byte
of the Status Register. Indicate in the description of the function
that we use the SPINOR_OP_RDCR (35h) command to interrogate the
Configuration Register.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 66 +++++++++++++++++++++----------------------
1 file changed, 33 insertions(+), 33 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 8cd1cadcb8b1..04491885b9bb 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -448,12 +448,16 @@ static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
return ret;
}
-/*
- * Read configuration register, returning its value in the
- * location. Return the configuration register value.
- * Returns negative if error occurred.
+/**
+ * spi_nor_read_cr() - Read the Configuration Register using the
+ * SPINOR_OP_RDCR (35h) command.
+ * @nor: pointer to 'struct spi_nor'
+ * @fsr: buffer where the value of the Configuration Register
+ * will be written.
+ *
+ * Return: 0 on success, -errno otherwise.
*/
-static int read_cr(struct spi_nor *nor)
+static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
{
int ret;
@@ -462,20 +466,17 @@ static int read_cr(struct spi_nor *nor)
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 1),
SPI_MEM_OP_NO_ADDR,
SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 1));
+ SPI_MEM_OP_DATA_IN(1, cr, 1));
ret = spi_mem_exec_op(nor->spimem, &op);
} else {
- ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDCR,
- nor->bouncebuf, 1);
+ ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDCR, cr, 1);
}
- if (ret < 0) {
+ if (ret)
dev_err(nor->dev, "error %d reading CR\n", ret);
- return ret;
- }
- return nor->bouncebuf[0];
+ return ret;
}
/*
@@ -1768,7 +1769,8 @@ static int macronix_quad_enable(struct spi_nor *nor)
* some very old and few memories don't support this instruction. If a pull-up
* resistor is present on the MISO/IO1 line, we might still be able to pass the
* "read back" test because the QSPI memory doesn't recognize the command,
- * so leaves the MISO/IO1 line state unchanged, hence read_cr() returns 0xFF.
+ * so leaves the MISO/IO1 line state unchanged, hence spi_nor_read_cr(nor, cr)
+ * gets the 0xFF value.
*
* bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
* memories.
@@ -1787,8 +1789,11 @@ static int spansion_quad_enable(struct spi_nor *nor)
return ret;
/* read back and check it */
- ret = read_cr(nor);
- if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
+ ret = spi_nor_read_cr(nor, &nor->bouncebuf[0]);
+ if (ret)
+ return ret;
+
+ if (!(nor->bouncebuf[0] & CR_QUAD_EN_SPAN)) {
dev_err(nor->dev, "Spansion Quad bit not set\n");
return -EINVAL;
}
@@ -1839,21 +1844,18 @@ static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
*/
static int spansion_read_cr_quad_enable(struct spi_nor *nor)
{
- struct device *dev = nor->dev;
u8 *sr_cr = nor->bouncebuf;
int ret;
/* Check current Quad Enable bit value. */
- ret = read_cr(nor);
- if (ret < 0) {
- dev_err(dev, "error while reading configuration register\n");
- return -EINVAL;
- }
+ ret = spi_nor_read_cr(nor, &sr_cr[1]);
+ if (ret)
+ return ret;
- if (ret & CR_QUAD_EN_SPAN)
+ if (sr_cr[1] & CR_QUAD_EN_SPAN)
return 0;
- sr_cr[1] = ret | CR_QUAD_EN_SPAN;
+ sr_cr[1] |= CR_QUAD_EN_SPAN;
/* Keep the current value of the Status Register. */
ret = spi_nor_read_sr(nor, &sr_cr[0]);
@@ -1865,8 +1867,11 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
return ret;
/* Read back and check it. */
- ret = read_cr(nor);
- if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
+ ret = spi_nor_read_cr(nor, &sr_cr[1]);
+ if (ret)
+ return ret;
+
+ if (!(sr_cr[1] & CR_QUAD_EN_SPAN)) {
dev_err(nor->dev, "Spansion Quad bit not set\n");
return -EINVAL;
}
@@ -2007,20 +2012,15 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor)
u8 *sr_cr = nor->bouncebuf;
/* Check current Quad Enable bit value. */
- ret = read_cr(nor);
- if (ret < 0) {
- dev_err(nor->dev,
- "error while reading configuration register\n");
+ ret = spi_nor_read_cr(nor, &sr_cr[1]);
+ if (ret)
return ret;
- }
/*
* When the configuration register Quad Enable bit is one, only the
* Write Status (01h) command with two data bytes may be used.
*/
- if (ret & CR_QUAD_EN_SPAN) {
- sr_cr[1] = ret;
-
+ if (sr_cr[1] & CR_QUAD_EN_SPAN) {
ret = spi_nor_read_sr(nor, &sr_cr[0]);
if (ret)
return ret;
--
2.9.5
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 08/23] mtd: spi-nor: Rework write_enable/disable()
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
` (6 preceding siblings ...)
2019-09-17 15:55 ` [PATCH 07/23] mtd: spi-nor: Rework read_cr() Tudor.Ambarus
@ 2019-09-17 15:55 ` Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 09/23] mtd: spi-nor: Fix retlen handling in sst_write() Tudor.Ambarus
` (15 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-17 15:55 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, Tudor.Ambarus, andrew, linux-kernel, vz,
linux-mediatek, joel, matthias.bgg, computersforpeace, dwmw2,
linux-arm-kernel
From: Tudor Ambarus <tudor.ambarus@microchip.com>
static int write_enable(struct spi_nor *nor)
static int write_disable(struct spi_nor *nor)
become
static int spi_nor_write_enable(struct spi_nor *nor)
static int spi_nor_write_disable(struct spi_nor *nor)
Check for errors after each call to them. Move them up in the
file as the first SPI NOR Register Operations, to avoid further
forward declarations.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 175 +++++++++++++++++++++++++++++-------------
1 file changed, 120 insertions(+), 55 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 04491885b9bb..271c2b465038 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -389,6 +389,64 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
}
/**
+ * spi_nor_write_enable() - Set write enable latch with Write Enable command.
+ * @nor: pointer to 'struct spi_nor'
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_write_enable(struct spi_nor *nor)
+{
+ int ret;
+
+ if (nor->spimem) {
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 1),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_NO_DATA);
+
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ } else {
+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WREN,
+ NULL, 0);
+ }
+
+ if (ret)
+ dev_err(nor->dev, "error %d on Write Enable\n", ret);
+
+ return ret;
+}
+
+/**
+ * spi_nor_write_disable() - Send Write Disable instruction to the chip.
+ * @nor: pointer to 'struct spi_nor'
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_write_disable(struct spi_nor *nor)
+{
+ int ret;
+
+ if (nor->spimem) {
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 1),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_NO_DATA);
+
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ } else {
+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRDI,
+ NULL, 0);
+ }
+
+ if (ret)
+ dev_err(nor->dev, "error %d on Write Disable\n", ret);
+
+ return ret;
+}
+
+/**
* spi_nor_read_sr() - Read the Status Register.
* @nor: pointer to 'struct spi_nor'
* @sr: buffer where the value of the Status Register will be written.
@@ -500,43 +558,6 @@ static int write_sr(struct spi_nor *nor, u8 val)
nor->bouncebuf, 1);
}
-/*
- * Set write enable latch with Write Enable command.
- * Returns negative if error occurred.
- */
-static int write_enable(struct spi_nor *nor)
-{
- if (nor->spimem) {
- struct spi_mem_op op =
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 1),
- SPI_MEM_OP_NO_ADDR,
- SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_NO_DATA);
-
- return spi_mem_exec_op(nor->spimem, &op);
- }
-
- return nor->controller_ops->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
-}
-
-/*
- * Send write disable instruction to the chip.
- */
-static int write_disable(struct spi_nor *nor)
-{
- if (nor->spimem) {
- struct spi_mem_op op =
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 1),
- SPI_MEM_OP_NO_ADDR,
- SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_NO_DATA);
-
- return spi_mem_exec_op(nor->spimem, &op);
- }
-
- return nor->controller_ops->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
-}
-
static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
{
return mtd->priv;
@@ -645,9 +666,15 @@ static int st_micron_set_4byte(struct spi_nor *nor, bool enable)
{
int ret;
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
+
ret = macronix_set_4byte(nor, enable);
- write_disable(nor);
+ if (ret)
+ return ret;
+
+ ret = spi_nor_write_disable(nor);
return ret;
}
@@ -701,9 +728,15 @@ static int winbond_set_4byte(struct spi_nor *nor, bool enable)
* Register to be set to 1, so all 3-byte-address reads come from the
* second 16M. We must clear the register to enable normal behavior.
*/
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
+
ret = spi_nor_write_ear(nor, 0);
- write_disable(nor);
+ if (ret)
+ return ret;
+
+ ret = spi_nor_write_disable(nor);
return ret;
}
@@ -1219,7 +1252,9 @@ static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len)
list_for_each_entry_safe(cmd, next, &erase_list, list) {
nor->erase_opcode = cmd->opcode;
while (cmd->count) {
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ goto destroy_erase_cmd_list;
ret = spi_nor_erase_sector(nor, addr);
if (ret)
@@ -1274,7 +1309,9 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
unsigned long timeout;
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ goto erase_err;
if (erase_chip(nor)) {
ret = -EIO;
@@ -1302,7 +1339,9 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
/* "sector"-at-a-time erase */
} else if (spi_nor_has_uniform_erase(nor)) {
while (len) {
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ goto erase_err;
ret = spi_nor_erase_sector(nor, addr);
if (ret)
@@ -1323,7 +1362,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
goto erase_err;
}
- write_disable(nor);
+ ret = spi_nor_write_disable(nor);
erase_err:
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
@@ -1336,7 +1375,10 @@ static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
{
int ret;
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
+
ret = write_sr(nor, status_new);
if (ret)
return ret;
@@ -1681,7 +1723,9 @@ static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
{
int ret;
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
if (nor->spimem) {
struct spi_mem_op op =
@@ -1733,7 +1777,9 @@ static int macronix_quad_enable(struct spi_nor *nor)
if (nor->bouncebuf[0] & SR_QUAD_EN_MX)
return 0;
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
write_sr(nor, nor->bouncebuf[0] | SR_QUAD_EN_MX);
@@ -1936,7 +1982,9 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor)
/* Update the Quad Enable bit. */
*sr2 |= SR2_QUAD_EN_BIT7;
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
ret = spi_nor_write_sr2(nor, sr2);
if (ret < 0) {
@@ -1978,7 +2026,9 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor)
if (ret)
return ret;
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
ret = write_sr(nor, nor->bouncebuf[0] & ~mask);
if (ret) {
@@ -2601,7 +2651,9 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
if (ret)
return ret;
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ goto unlock_and_unprep;
nor->sst_write_second = false;
@@ -2640,14 +2692,19 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
}
nor->sst_write_second = false;
- write_disable(nor);
+ ret = spi_nor_write_disable(nor);
+ if (ret)
+ goto sst_write_err;
+
ret = spi_nor_wait_till_ready(nor);
if (ret)
goto sst_write_err;
/* Write out trailing byte if it exists. */
if (actual != len) {
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ goto sst_write_err;
nor->program_opcode = SPINOR_OP_BP;
ret = spi_nor_write_data(nor, to, 1, buf + actual);
@@ -2658,11 +2715,16 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
ret = spi_nor_wait_till_ready(nor);
if (ret)
goto sst_write_err;
- write_disable(nor);
+
+ ret = spi_nor_write_disable(nor);
+ if (ret)
+ goto sst_write_err;
+
actual += 1;
}
sst_write_err:
*retlen += actual;
+unlock_and_unprep:
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
return ret;
}
@@ -2710,7 +2772,10 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
addr = spi_nor_convert_addr(nor, addr);
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ goto write_err;
+
ret = spi_nor_write_data(nor, addr, page_remain, buf + i);
if (ret < 0)
goto write_err;
--
2.9.5
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 09/23] mtd: spi-nor: Fix retlen handling in sst_write()
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
` (7 preceding siblings ...)
2019-09-17 15:55 ` [PATCH 08/23] mtd: spi-nor: Rework write_enable/disable() Tudor.Ambarus
@ 2019-09-17 15:55 ` Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 10/23] mtd: spi-nor: Rework write_sr() Tudor.Ambarus
` (14 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-17 15:55 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, Tudor.Ambarus, andrew, linux-kernel, vz,
linux-mediatek, joel, matthias.bgg, computersforpeace, dwmw2,
linux-arm-kernel
From: Tudor Ambarus <tudor.ambarus@microchip.com>
In case the write of the first byte failed, retlen was incorrectly
incremented to *retlen += actual; on the exit path. retlen should be
incremented when actual data was written to the flash.
Rename 'sst_write_err' label to 'out' as it is no longer generic for
all the write errors in the sst_write() method, and may introduce
confusion.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 271c2b465038..151db98f7d49 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -2665,12 +2665,12 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
/* write one byte. */
ret = spi_nor_write_data(nor, to, 1, buf);
if (ret < 0)
- goto sst_write_err;
+ goto unlock_and_unprep;
WARN(ret != 1, "While writing 1 byte written %i bytes\n",
(int)ret);
ret = spi_nor_wait_till_ready(nor);
if (ret)
- goto sst_write_err;
+ goto unlock_and_unprep;
}
to += actual;
@@ -2681,12 +2681,12 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
/* write two bytes. */
ret = spi_nor_write_data(nor, to, 2, buf + actual);
if (ret < 0)
- goto sst_write_err;
+ goto out;
WARN(ret != 2, "While writing 2 bytes written %i bytes\n",
(int)ret);
ret = spi_nor_wait_till_ready(nor);
if (ret)
- goto sst_write_err;
+ goto out;
to += 2;
nor->sst_write_second = true;
}
@@ -2694,35 +2694,35 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
ret = spi_nor_write_disable(nor);
if (ret)
- goto sst_write_err;
+ goto out;
ret = spi_nor_wait_till_ready(nor);
if (ret)
- goto sst_write_err;
+ goto out;
/* Write out trailing byte if it exists. */
if (actual != len) {
ret = spi_nor_write_enable(nor);
if (ret)
- goto sst_write_err;
+ goto out;
nor->program_opcode = SPINOR_OP_BP;
ret = spi_nor_write_data(nor, to, 1, buf + actual);
if (ret < 0)
- goto sst_write_err;
+ goto out;
WARN(ret != 1, "While writing 1 byte written %i bytes\n",
(int)ret);
ret = spi_nor_wait_till_ready(nor);
if (ret)
- goto sst_write_err;
+ goto out;
ret = spi_nor_write_disable(nor);
if (ret)
- goto sst_write_err;
+ goto out;
actual += 1;
}
-sst_write_err:
+out:
*retlen += actual;
unlock_and_unprep:
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
--
2.9.5
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 10/23] mtd: spi-nor: Rework write_sr()
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
` (8 preceding siblings ...)
2019-09-17 15:55 ` [PATCH 09/23] mtd: spi-nor: Fix retlen handling in sst_write() Tudor.Ambarus
@ 2019-09-17 15:55 ` Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 11/23] mtd: spi-nor: Rework spi_nor_read/write_sr2() Tudor.Ambarus
` (13 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-17 15:55 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, Tudor.Ambarus, andrew, linux-kernel, vz,
linux-mediatek, joel, matthias.bgg, computersforpeace, dwmw2,
linux-arm-kernel
From: Tudor Ambarus <tudor.ambarus@microchip.com>
The Status Register can be written with one or two bytes.
Merge:
static int write_sr(struct spi_nor *nor, u8 val)
static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
into
static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)
Avoid duplicating code by moving the calls to spi_nor_write_enable() and
spi_nor_wait_till_ready() inside spi_nor_write_sr().
Move the spi_nor_wait_till_ready() together with the spi_nor_ready()
methods to avoid forward declarations.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 426 +++++++++++++++++++-----------------------
1 file changed, 191 insertions(+), 235 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 151db98f7d49..89800bbaa179 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -537,25 +537,198 @@ static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
return ret;
}
+static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
+{
+ if (nor->spimem) {
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 1),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_IN(1, sr, 1));
+
+ return spi_mem_exec_op(nor->spimem, &op);
+ }
+
+ return nor->controller_ops->read_reg(nor, SPINOR_OP_XRDSR, sr, 1);
+}
+
+static int s3an_sr_ready(struct spi_nor *nor)
+{
+ int ret;
+
+ ret = spi_nor_xread_sr(nor, nor->bouncebuf);
+ if (ret < 0) {
+ dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
+ return ret;
+ }
+
+ return !!(nor->bouncebuf[0] & XSR_RDY);
+}
+
+static int spi_nor_clear_sr(struct spi_nor *nor)
+{
+ if (nor->spimem) {
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 1),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_NO_DATA);
+
+ return spi_mem_exec_op(nor->spimem, &op);
+ }
+
+ return nor->controller_ops->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
+}
+
+static int spi_nor_sr_ready(struct spi_nor *nor)
+{
+ int ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
+
+ if (ret)
+ return ret;
+
+ if (nor->flags & SNOR_F_USE_CLSR &&
+ nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
+ if (nor->bouncebuf[0] & SR_E_ERR)
+ dev_err(nor->dev, "Erase Error occurred\n");
+ else
+ dev_err(nor->dev, "Programming Error occurred\n");
+
+ spi_nor_clear_sr(nor);
+ return -EIO;
+ }
+
+ return !(nor->bouncebuf[0] & SR_WIP);
+}
+
+static int spi_nor_clear_fsr(struct spi_nor *nor)
+{
+ if (nor->spimem) {
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 1),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_NO_DATA);
+
+ return spi_mem_exec_op(nor->spimem, &op);
+ }
+
+ return nor->controller_ops->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
+}
+
+static int spi_nor_fsr_ready(struct spi_nor *nor)
+{
+ int ret = spi_nor_read_fsr(nor, &nor->bouncebuf[0]);
+
+ if (ret)
+ return ret;
+
+ if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) {
+ if (nor->bouncebuf[0] & FSR_E_ERR)
+ dev_err(nor->dev, "Erase operation failed.\n");
+ else
+ dev_err(nor->dev, "Program operation failed.\n");
+
+ if (nor->bouncebuf[0] & FSR_PT_ERR)
+ dev_err(nor->dev,
+ "Attempted to modify a protected sector.\n");
+
+ spi_nor_clear_fsr(nor);
+ return -EIO;
+ }
+
+ return nor->bouncebuf[0] & FSR_READY;
+}
+
+static int spi_nor_ready(struct spi_nor *nor)
+{
+ int sr, fsr;
+
+ if (nor->flags & SNOR_F_READY_XSR_RDY)
+ sr = s3an_sr_ready(nor);
+ else
+ sr = spi_nor_sr_ready(nor);
+ if (sr < 0)
+ return sr;
+ fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
+ if (fsr < 0)
+ return fsr;
+ return sr && fsr;
+}
+
/*
- * Write status register 1 byte
- * Returns negative if error occurred.
+ * Service routine to read status register until ready, or timeout occurs.
+ * Returns non-zero if error.
+ */
+static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
+ unsigned long timeout_jiffies)
+{
+ unsigned long deadline;
+ int timeout = 0, ret;
+
+ deadline = jiffies + timeout_jiffies;
+
+ while (!timeout) {
+ if (time_after_eq(jiffies, deadline))
+ timeout = 1;
+
+ ret = spi_nor_ready(nor);
+ if (ret < 0)
+ return ret;
+ if (ret)
+ return 0;
+
+ cond_resched();
+ }
+
+ dev_err(nor->dev, "flash operation timed out\n");
+
+ return -ETIMEDOUT;
+}
+
+static int spi_nor_wait_till_ready(struct spi_nor *nor)
+{
+ return spi_nor_wait_till_ready_with_timeout(nor,
+ DEFAULT_READY_WAIT_JIFFIES);
+}
+
+/**
+ * spi_nor_write_sr() - Write the Status Register.
+ * @nor: pointer to 'struct spi_nor'.
+ * @sr: buffer to write to the Status Register.
+ * len: number of bytes to write to the Status Register.
+ *
+ * Return: 0 on success, -errno otherwise.
*/
-static int write_sr(struct spi_nor *nor, u8 val)
+static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)
{
- nor->bouncebuf[0] = val;
+ int ret;
+
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
+
if (nor->spimem) {
struct spi_mem_op op =
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1),
SPI_MEM_OP_NO_ADDR,
SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 1));
+ SPI_MEM_OP_DATA_OUT(len, sr, 1));
- return spi_mem_exec_op(nor->spimem, &op);
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ } else {
+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR,
+ sr, len);
}
- return nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR,
- nor->bouncebuf, 1);
+ if (ret) {
+ dev_err(nor->dev, "error while writing Status Register\n");
+ return ret;
+ }
+
+ ret = spi_nor_wait_till_ready(nor);
+
+ return ret;
}
static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
@@ -741,161 +914,6 @@ static int winbond_set_4byte(struct spi_nor *nor, bool enable)
return ret;
}
-static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
-{
- if (nor->spimem) {
- struct spi_mem_op op =
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 1),
- SPI_MEM_OP_NO_ADDR,
- SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_IN(1, sr, 1));
-
- return spi_mem_exec_op(nor->spimem, &op);
- }
-
- return nor->controller_ops->read_reg(nor, SPINOR_OP_XRDSR, sr, 1);
-}
-
-static int s3an_sr_ready(struct spi_nor *nor)
-{
- int ret;
-
- ret = spi_nor_xread_sr(nor, nor->bouncebuf);
- if (ret < 0) {
- dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
- return ret;
- }
-
- return !!(nor->bouncebuf[0] & XSR_RDY);
-}
-
-static int spi_nor_clear_sr(struct spi_nor *nor)
-{
- if (nor->spimem) {
- struct spi_mem_op op =
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 1),
- SPI_MEM_OP_NO_ADDR,
- SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_NO_DATA);
-
- return spi_mem_exec_op(nor->spimem, &op);
- }
-
- return nor->controller_ops->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
-}
-
-static int spi_nor_sr_ready(struct spi_nor *nor)
-{
- int ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
-
- if (ret)
- return ret;
-
- if (nor->flags & SNOR_F_USE_CLSR &&
- nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
- if (nor->bouncebuf[0] & SR_E_ERR)
- dev_err(nor->dev, "Erase Error occurred\n");
- else
- dev_err(nor->dev, "Programming Error occurred\n");
-
- spi_nor_clear_sr(nor);
- return -EIO;
- }
-
- return !(nor->bouncebuf[0] & SR_WIP);
-}
-
-static int spi_nor_clear_fsr(struct spi_nor *nor)
-{
- if (nor->spimem) {
- struct spi_mem_op op =
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 1),
- SPI_MEM_OP_NO_ADDR,
- SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_NO_DATA);
-
- return spi_mem_exec_op(nor->spimem, &op);
- }
-
- return nor->controller_ops->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
-}
-
-static int spi_nor_fsr_ready(struct spi_nor *nor)
-{
- int ret = spi_nor_read_fsr(nor, &nor->bouncebuf[0]);
-
- if (ret)
- return ret;
-
- if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) {
- if (nor->bouncebuf[0] & FSR_E_ERR)
- dev_err(nor->dev, "Erase operation failed.\n");
- else
- dev_err(nor->dev, "Program operation failed.\n");
-
- if (nor->bouncebuf[0] & FSR_PT_ERR)
- dev_err(nor->dev,
- "Attempted to modify a protected sector.\n");
-
- spi_nor_clear_fsr(nor);
- return -EIO;
- }
-
- return nor->bouncebuf[0] & FSR_READY;
-}
-
-static int spi_nor_ready(struct spi_nor *nor)
-{
- int sr, fsr;
-
- if (nor->flags & SNOR_F_READY_XSR_RDY)
- sr = s3an_sr_ready(nor);
- else
- sr = spi_nor_sr_ready(nor);
- if (sr < 0)
- return sr;
- fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
- if (fsr < 0)
- return fsr;
- return sr && fsr;
-}
-
-/*
- * Service routine to read status register until ready, or timeout occurs.
- * Returns non-zero if error.
- */
-static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
- unsigned long timeout_jiffies)
-{
- unsigned long deadline;
- int timeout = 0, ret;
-
- deadline = jiffies + timeout_jiffies;
-
- while (!timeout) {
- if (time_after_eq(jiffies, deadline))
- timeout = 1;
-
- ret = spi_nor_ready(nor);
- if (ret < 0)
- return ret;
- if (ret)
- return 0;
-
- cond_resched();
- }
-
- dev_err(nor->dev, "flash operation timed out\n");
-
- return -ETIMEDOUT;
-}
-
-static int spi_nor_wait_till_ready(struct spi_nor *nor)
-{
- return spi_nor_wait_till_ready_with_timeout(nor,
- DEFAULT_READY_WAIT_JIFFIES);
-}
-
/*
* Erase the whole flash memory
*
@@ -1375,15 +1393,9 @@ static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
{
int ret;
- ret = spi_nor_write_enable(nor);
- if (ret)
- return ret;
-
- ret = write_sr(nor, status_new);
- if (ret)
- return ret;
+ nor->bouncebuf[0] = status_new;
- ret = spi_nor_wait_till_ready(nor);
+ ret = spi_nor_write_sr(nor, &nor->bouncebuf[0], 1);
if (ret)
return ret;
@@ -1713,49 +1725,6 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
return ret;
}
-/*
- * Write status Register and configuration register with 2 bytes
- * The first byte will be written to the status register, while the
- * second byte will be written to the configuration register.
- * Return negative if error occurred.
- */
-static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
-{
- int ret;
-
- ret = spi_nor_write_enable(nor);
- if (ret)
- return ret;
-
- if (nor->spimem) {
- struct spi_mem_op op =
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1),
- SPI_MEM_OP_NO_ADDR,
- SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_OUT(2, sr_cr, 1));
-
- ret = spi_mem_exec_op(nor->spimem, &op);
- } else {
- ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR,
- sr_cr, 2);
- }
-
- if (ret < 0) {
- dev_err(nor->dev,
- "error while writing configuration register\n");
- return -EINVAL;
- }
-
- ret = spi_nor_wait_till_ready(nor);
- if (ret) {
- dev_err(nor->dev,
- "timeout while writing configuration register\n");
- return ret;
- }
-
- return 0;
-}
-
/**
* macronix_quad_enable() - set QE bit in Status Register.
* @nor: pointer to a 'struct spi_nor'
@@ -1777,13 +1746,9 @@ static int macronix_quad_enable(struct spi_nor *nor)
if (nor->bouncebuf[0] & SR_QUAD_EN_MX)
return 0;
- ret = spi_nor_write_enable(nor);
- if (ret)
- return ret;
-
- write_sr(nor, nor->bouncebuf[0] | SR_QUAD_EN_MX);
+ nor->bouncebuf[0] |= SR_QUAD_EN_MX;
- ret = spi_nor_wait_till_ready(nor);
+ ret = spi_nor_write_sr(nor, &nor->bouncebuf[0], 1);
if (ret)
return ret;
@@ -1830,7 +1795,7 @@ static int spansion_quad_enable(struct spi_nor *nor)
sr_cr[0] = 0;
sr_cr[1] = CR_QUAD_EN_SPAN;
- ret = write_sr_cr(nor, sr_cr);
+ ret = spi_nor_write_sr(nor, sr_cr, 2);
if (ret)
return ret;
@@ -1872,7 +1837,7 @@ static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
sr_cr[1] = CR_QUAD_EN_SPAN;
- return write_sr_cr(nor, sr_cr);
+ return spi_nor_write_sr(nor, sr_cr, 2);
}
/**
@@ -1908,7 +1873,7 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
if (ret)
return ret;
- ret = write_sr_cr(nor, sr_cr);
+ ret = spi_nor_write_sr(nor, sr_cr, 2);
if (ret)
return ret;
@@ -2026,19 +1991,10 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor)
if (ret)
return ret;
- ret = spi_nor_write_enable(nor);
- if (ret)
- return ret;
+ nor->bouncebuf[0] &= mask;
- ret = write_sr(nor, nor->bouncebuf[0] & ~mask);
- if (ret) {
- dev_err(nor->dev, "write to status register failed\n");
- return ret;
- }
+ ret = spi_nor_write_sr(nor, &nor->bouncebuf[0], 1);
- ret = spi_nor_wait_till_ready(nor);
- if (ret)
- dev_err(nor->dev, "timeout while writing status register\n");
return ret;
}
@@ -2077,7 +2033,7 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor)
sr_cr[0] &= ~mask;
- ret = write_sr_cr(nor, sr_cr);
+ ret = spi_nor_write_sr(nor, sr_cr, 2);
if (ret)
dev_err(nor->dev, "16-bit write register failed\n");
return ret;
--
2.9.5
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 11/23] mtd: spi-nor: Rework spi_nor_read/write_sr2()
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
` (9 preceding siblings ...)
2019-09-17 15:55 ` [PATCH 10/23] mtd: spi-nor: Rework write_sr() Tudor.Ambarus
@ 2019-09-17 15:55 ` Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 12/23] mtd: spi-nor: Report error in spi_nor_xread_sr() Tudor.Ambarus
` (12 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-17 15:55 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, Tudor.Ambarus, andrew, linux-kernel, vz,
linux-mediatek, joel, matthias.bgg, computersforpeace, dwmw2,
linux-arm-kernel
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Move the methods up in the file, where the other Register
operations reside.
The error is reported inside each SR2 function, to spare the callers
of duplicating code.
Constify sr2 in spi_nor_write_sr2(). Do the spi_nor_write_enable() and
spi_nor_wait_till_ready() inside spi_nor_write_sr2(), as the
spi_nor_write_sr() does.
While modyfing sr2_bit7_quad_enable(), add a new line for better code
readability.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 118 ++++++++++++++++++++++++++----------------
1 file changed, 74 insertions(+), 44 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 89800bbaa179..c06de7ad6434 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -731,6 +731,74 @@ static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)
return ret;
}
+/**
+ * spi_nor_write_sr2() - Write the Status Register 2 using the
+ * SPINOR_OP_WRSR2 (3eh) command.
+ * @nor: pointer to 'struct spi_nor'.
+ * @sr2: buffer to write to the Status Register.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2)
+{
+ int ret;
+
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
+
+ if (nor->spimem) {
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 1),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_OUT(1, sr2, 1));
+
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ } else {
+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR2,
+ sr2, 1);
+ }
+
+ if (ret)
+ dev_err(nor->dev, "error while writing Status Register 2\n");
+
+ ret = spi_nor_wait_till_ready(nor);
+
+ return ret;
+}
+
+/**
+ * spi_nor_read_sr2() - Read the Status Register 2 using the
+ * SPINOR_OP_RDSR2 (3fh) command.
+ * @nor: pointer to 'struct spi_nor'
+ * @sr2: buffer where the value of the Status Register will be written.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
+{
+ int ret;
+
+ if (nor->spimem) {
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 1),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_IN(1, sr2, 1));
+
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ } else {
+ ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2,
+ sr2, 1);
+ }
+
+ if (ret)
+ dev_err(nor->dev, "error while reading Status Register 2\n");
+
+ return ret;
+}
+
static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
{
return mtd->priv;
@@ -1890,36 +1958,6 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
return 0;
}
-static int spi_nor_write_sr2(struct spi_nor *nor, u8 *sr2)
-{
- if (nor->spimem) {
- struct spi_mem_op op =
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 1),
- SPI_MEM_OP_NO_ADDR,
- SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_OUT(1, sr2, 1));
-
- return spi_mem_exec_op(nor->spimem, &op);
- }
-
- return nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR2, sr2, 1);
-}
-
-static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
-{
- if (nor->spimem) {
- struct spi_mem_op op =
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 1),
- SPI_MEM_OP_NO_ADDR,
- SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_IN(1, sr2, 1));
-
- return spi_mem_exec_op(nor->spimem, &op);
- }
-
- return nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2, sr2, 1);
-}
-
/**
* sr2_bit7_quad_enable() - set QE bit in Status Register 2.
* @nor: pointer to a 'struct spi_nor'
@@ -1941,31 +1979,23 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor)
ret = spi_nor_read_sr2(nor, sr2);
if (ret)
return ret;
+
if (*sr2 & SR2_QUAD_EN_BIT7)
return 0;
/* Update the Quad Enable bit. */
*sr2 |= SR2_QUAD_EN_BIT7;
- ret = spi_nor_write_enable(nor);
- if (ret)
- return ret;
-
ret = spi_nor_write_sr2(nor, sr2);
- if (ret < 0) {
- dev_err(nor->dev, "error while writing status register 2\n");
- return -EINVAL;
- }
-
- ret = spi_nor_wait_till_ready(nor);
- if (ret < 0) {
- dev_err(nor->dev, "timeout while writing status register 2\n");
+ if (ret)
return ret;
- }
/* Read back and check it. */
ret = spi_nor_read_sr2(nor, sr2);
- if (!(ret > 0 && (*sr2 & SR2_QUAD_EN_BIT7))) {
+ if (ret)
+ return ret;
+
+ if (!(*sr2 & SR2_QUAD_EN_BIT7)) {
dev_err(nor->dev, "SR2 Quad bit not set\n");
return -EINVAL;
}
--
2.9.5
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^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 12/23] mtd: spi-nor: Report error in spi_nor_xread_sr()
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
` (10 preceding siblings ...)
2019-09-17 15:55 ` [PATCH 11/23] mtd: spi-nor: Rework spi_nor_read/write_sr2() Tudor.Ambarus
@ 2019-09-17 15:55 ` Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 13/23] mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr() Tudor.Ambarus
` (11 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-17 15:55 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, Tudor.Ambarus, andrew, linux-kernel, vz,
linux-mediatek, joel, matthias.bgg, computersforpeace, dwmw2,
linux-arm-kernel
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Report error inside spi_nor_xread_sr(), to spare the callers of
duplicating the error message.
Add method description. Drop unnecessary cast to int when reporting
the error. Comparing the return code with zero is enough, drop the
checking for negative return values.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 27 +++++++++++++++++++--------
1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index c06de7ad6434..a34614753d7b 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -537,8 +537,17 @@ static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
return ret;
}
+/**
+ * spi_nor_xread_sr() - Read the Status Register on S3AN flashes.
+ * @nor: pointer to 'struct spi_nor'
+ * @sr: buffer where the value of the Status Register will be written.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
{
+ int ret;
+
if (nor->spimem) {
struct spi_mem_op op =
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 1),
@@ -546,10 +555,16 @@ static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
SPI_MEM_OP_NO_DUMMY,
SPI_MEM_OP_DATA_IN(1, sr, 1));
- return spi_mem_exec_op(nor->spimem, &op);
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ } else {
+ ret = nor->controller_ops->read_reg(nor, SPINOR_OP_XRDSR,
+ sr, 1);
}
- return nor->controller_ops->read_reg(nor, SPINOR_OP_XRDSR, sr, 1);
+ if (ret)
+ dev_err(nor->dev, "error %d reading XRDSR\n", ret);
+
+ return ret;
}
static int s3an_sr_ready(struct spi_nor *nor)
@@ -557,10 +572,8 @@ static int s3an_sr_ready(struct spi_nor *nor)
int ret;
ret = spi_nor_xread_sr(nor, nor->bouncebuf);
- if (ret < 0) {
- dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
+ if (ret)
return ret;
- }
return !!(nor->bouncebuf[0] & XSR_RDY);
}
@@ -2800,10 +2813,8 @@ static int s3an_nor_setup(struct spi_nor *nor,
int ret;
ret = spi_nor_xread_sr(nor, nor->bouncebuf);
- if (ret < 0) {
- dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
+ if (ret)
return ret;
- }
nor->erase_opcode = SPINOR_OP_XSE;
nor->program_opcode = SPINOR_OP_XPP;
--
2.9.5
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^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 13/23] mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr()
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
` (11 preceding siblings ...)
2019-09-17 15:55 ` [PATCH 12/23] mtd: spi-nor: Report error in spi_nor_xread_sr() Tudor.Ambarus
@ 2019-09-17 15:55 ` Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 14/23] mtd: spi-nor: Drop duplicated new line Tudor.Ambarus
` (10 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-17 15:55 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, Tudor.Ambarus, andrew, linux-kernel, vz,
linux-mediatek, joel, matthias.bgg, computersforpeace, dwmw2,
linux-arm-kernel
From: Tudor Ambarus <tudor.ambarus@microchip.com>
spi_nor_clear_sr() and spi_nor_clear_fsr() are called just in case
of errors. The callers didn't check their return value. Make them
of type void and print an error in case the operations fail.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 36 ++++++++++++++++++++++++++++++------
1 file changed, 30 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index a34614753d7b..62b9298473b4 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -578,8 +578,16 @@ static int s3an_sr_ready(struct spi_nor *nor)
return !!(nor->bouncebuf[0] & XSR_RDY);
}
-static int spi_nor_clear_sr(struct spi_nor *nor)
+/**
+ * spi_nor_clear_sr() - Clear the Status Register 1.
+ * @nor: pointer to 'struct spi_nor'
+ *
+ * Prints error in case the operation fails.
+ */
+static void spi_nor_clear_sr(struct spi_nor *nor)
{
+ int ret;
+
if (nor->spimem) {
struct spi_mem_op op =
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 1),
@@ -587,10 +595,14 @@ static int spi_nor_clear_sr(struct spi_nor *nor)
SPI_MEM_OP_NO_DUMMY,
SPI_MEM_OP_NO_DATA);
- return spi_mem_exec_op(nor->spimem, &op);
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ } else {
+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CLSR,
+ NULL, 0);
}
- return nor->controller_ops->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
+ if (ret)
+ dev_err(nor->dev, "error %d clearing Status Register 1\n", ret);
}
static int spi_nor_sr_ready(struct spi_nor *nor)
@@ -614,8 +626,16 @@ static int spi_nor_sr_ready(struct spi_nor *nor)
return !(nor->bouncebuf[0] & SR_WIP);
}
-static int spi_nor_clear_fsr(struct spi_nor *nor)
+/**
+ * spi_nor_clear_fsr() - Clear the Flag Status Register.
+ * @nor: pointer to 'struct spi_nor'
+ *
+ * Prints error in case the operation fails.
+ */
+static void spi_nor_clear_fsr(struct spi_nor *nor)
{
+ int ret;
+
if (nor->spimem) {
struct spi_mem_op op =
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 1),
@@ -623,10 +643,14 @@ static int spi_nor_clear_fsr(struct spi_nor *nor)
SPI_MEM_OP_NO_DUMMY,
SPI_MEM_OP_NO_DATA);
- return spi_mem_exec_op(nor->spimem, &op);
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ } else {
+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CLFSR,
+ NULL, 0);
}
- return nor->controller_ops->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
+ if (ret)
+ dev_err(nor->dev, "error %d clearing FSR\n", ret);
}
static int spi_nor_fsr_ready(struct spi_nor *nor)
--
2.9.5
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^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 14/23] mtd: spi-nor: Drop duplicated new line
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
` (12 preceding siblings ...)
2019-09-17 15:55 ` [PATCH 13/23] mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr() Tudor.Ambarus
@ 2019-09-17 15:55 ` Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 15/23] mtd: spi-nor: Drop spansion_quad_enable() Tudor.Ambarus
` (9 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-17 15:55 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, Tudor.Ambarus, andrew, linux-kernel, vz,
linux-mediatek, joel, matthias.bgg, computersforpeace, dwmw2,
linux-arm-kernel
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Two new lines, remove one.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 62b9298473b4..3e4691b6522d 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -841,7 +841,6 @@ static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
return mtd->priv;
}
-
static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
{
size_t i;
--
2.9.5
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^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 15/23] mtd: spi-nor: Drop spansion_quad_enable()
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
` (13 preceding siblings ...)
2019-09-17 15:55 ` [PATCH 14/23] mtd: spi-nor: Drop duplicated new line Tudor.Ambarus
@ 2019-09-17 15:55 ` Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 16/23] mtd: spi-nor: Fix errno on quad_enable methods Tudor.Ambarus
` (8 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-17 15:55 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, Tudor.Ambarus, andrew, linux-kernel, vz,
linux-mediatek, joel, matthias.bgg, computersforpeace, dwmw2,
linux-arm-kernel
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Drop the default spansion_quad_enable() method and replace it with
spansion_read_cr_quad_enable().
The function was buggy, it didn't care about the previous values
of the Status and Configuration Registers. spansion_read_cr_quad_enable()
is a Read-Modify-Write-Check function that keeps track of what were
the previous values of the Status and Configuration Registers.
In terms of instruction types sent to the flash, the only difference
between the spansion_quad_enable() and spansion_read_cr_quad_enable()
is that the later calls spi_nor_read_sr(). We can safely assume that all
flashes support spi_nor_read_sr(), because all flashes call it in
spi_nor_sr_ready(). The transition from spansion_quad_enable() to
spansion_read_cr_quad_enable() will not affect anybody, drop the buggy
code.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 58 ++++---------------------------------------
1 file changed, 5 insertions(+), 53 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 3e4691b6522d..20d32b7db268 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1869,54 +1869,6 @@ static int macronix_quad_enable(struct spi_nor *nor)
}
/**
- * spansion_quad_enable() - set QE bit in Configuraiton Register.
- * @nor: pointer to a 'struct spi_nor'
- *
- * Set the Quad Enable (QE) bit in the Configuration Register.
- * This function is kept for legacy purpose because it has been used for a
- * long time without anybody complaining but it should be considered as
- * deprecated and maybe buggy.
- * First, this function doesn't care about the previous values of the Status
- * and Configuration Registers when it sets the QE bit (bit 1) in the
- * Configuration Register: all other bits are cleared, which may have unwanted
- * side effects like removing some block protections.
- * Secondly, it uses the Read Configuration Register (35h) instruction though
- * some very old and few memories don't support this instruction. If a pull-up
- * resistor is present on the MISO/IO1 line, we might still be able to pass the
- * "read back" test because the QSPI memory doesn't recognize the command,
- * so leaves the MISO/IO1 line state unchanged, hence spi_nor_read_cr(nor, cr)
- * gets the 0xFF value.
- *
- * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
- * memories.
- *
- * Return: 0 on success, -errno otherwise.
- */
-static int spansion_quad_enable(struct spi_nor *nor)
-{
- u8 *sr_cr = nor->bouncebuf;
- int ret;
-
- sr_cr[0] = 0;
- sr_cr[1] = CR_QUAD_EN_SPAN;
- ret = spi_nor_write_sr(nor, sr_cr, 2);
- if (ret)
- return ret;
-
- /* read back and check it */
- ret = spi_nor_read_cr(nor, &nor->bouncebuf[0]);
- if (ret)
- return ret;
-
- if (!(nor->bouncebuf[0] & CR_QUAD_EN_SPAN)) {
- dev_err(nor->dev, "Spansion Quad bit not set\n");
- return -EINVAL;
- }
-
- return 0;
-}
-
-/**
* spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
* @nor: pointer to a 'struct spi_nor'
*
@@ -2071,9 +2023,9 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor)
*
* Read-modify-write function that clears the Block Protection bits from the
* Status Register without affecting other bits. The function is tightly
- * coupled with the spansion_quad_enable() function. Both assume that the Write
- * Register with 16 bits, together with the Read Configuration Register (35h)
- * instructions are supported.
+ * coupled with the spansion_read_cr_quad_enable() function. Both assume that
+ * the Write Register with 16 bits, together with the Read Configuration
+ * Register (35h) instructions are supported.
*
* Return: 0 on success, -errno otherwise.
*/
@@ -4560,7 +4512,7 @@ static void spi_nor_info_init_flash_params(struct spi_nor *nor)
u8 i, erase_mask;
/* Initialize legacy flash parameters and settings. */
- flash->quad_enable = spansion_quad_enable;
+ flash->quad_enable = spansion_read_cr_quad_enable;
flash->set_4byte = spansion_set_4byte;
flash->setup = spi_nor_default_setup;
@@ -4776,7 +4728,7 @@ static int spi_nor_init(struct spi_nor *nor)
int err;
if (nor->clear_sr_bp) {
- if (nor->flash.quad_enable == spansion_quad_enable)
+ if (nor->flash.quad_enable == spansion_read_cr_quad_enable)
nor->clear_sr_bp = spi_nor_spansion_clear_sr_bp;
err = nor->clear_sr_bp(nor);
--
2.9.5
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^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 16/23] mtd: spi-nor: Fix errno on quad_enable methods
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
` (14 preceding siblings ...)
2019-09-17 15:55 ` [PATCH 15/23] mtd: spi-nor: Drop spansion_quad_enable() Tudor.Ambarus
@ 2019-09-17 15:55 ` Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 17/23] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() Tudor.Ambarus
` (7 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-17 15:55 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, Tudor.Ambarus, andrew, linux-kernel, vz,
linux-mediatek, joel, matthias.bgg, computersforpeace, dwmw2,
linux-arm-kernel
From: Tudor Ambarus <tudor.ambarus@microchip.com>
When the Read-Modify-Write-Read-Back Quad Enable methods failed on
the Read-Back, they returned -EINVAL. Since this is an I/O error,
return -EIO.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 20d32b7db268..303a7bcf3423 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1862,7 +1862,7 @@ static int macronix_quad_enable(struct spi_nor *nor)
if (!(nor->bouncebuf[0] & SR_QUAD_EN_MX)) {
dev_err(nor->dev, "Macronix Quad bit not set\n");
- return -EINVAL;
+ return -EIO;
}
return 0;
@@ -1940,7 +1940,7 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
if (!(sr_cr[1] & CR_QUAD_EN_SPAN)) {
dev_err(nor->dev, "Spansion Quad bit not set\n");
- return -EINVAL;
+ return -EIO;
}
return 0;
@@ -1985,7 +1985,7 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor)
if (!(*sr2 & SR2_QUAD_EN_BIT7)) {
dev_err(nor->dev, "SR2 Quad bit not set\n");
- return -EINVAL;
+ return -EIO;
}
return 0;
--
2.9.5
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^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 17/23] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
` (15 preceding siblings ...)
2019-09-17 15:55 ` [PATCH 16/23] mtd: spi-nor: Fix errno on quad_enable methods Tudor.Ambarus
@ 2019-09-17 15:55 ` Tudor.Ambarus
2019-09-19 14:33 ` Vignesh Raghavendra
2019-09-17 15:55 ` [PATCH 18/23] mtd: spi-nor: Rework macronix_quad_enable() Tudor.Ambarus
` (6 subsequent siblings)
23 siblings, 1 reply; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-17 15:55 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, Tudor.Ambarus, andrew, linux-kernel, vz,
linux-mediatek, joel, matthias.bgg, computersforpeace, dwmw2,
linux-arm-kernel
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Make sure that when doing a lock() or an unlock() operation we don't clear
the QE bit from Status Register 2.
JESD216 revB or later offers information about the *default* Status
Register commands to use (see BFPT DWORDS[15], bits 22:20). In this
standard, Status Register 1 refers to the first data byte transferred on a
Read Status (05h) or Write Status (01h) command. Status register 2 refers
to the byte read using instruction 35h. Status register 2 is the second
byte transferred in a Write Status (01h) command.
Industry naming and definitions of these Status Registers may differ.
The definitions are described in JESD216B, BFPT DWORDS[15], bits 22:20.
There are cases in which writing only one byte to the Status Register 1
has the side-effect of clearing Status Register 2 and implicitly the Quad
Enable bit. This side-effect is hit just by the
BFPT_DWORD15_QER_SR2_BIT1_BUGGY and BFPT_DWORD15_QER_SR2_BIT1 cases.
Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 170 +++++++++++++++++++++++++++++++++++++-----
include/linux/mtd/spi-nor.h | 2 +
2 files changed, 152 insertions(+), 20 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 303a7bcf3423..4a513ed13807 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -836,6 +836,132 @@ static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
return ret;
}
+/**
+ * spi_nor_write_sr1_and_check() - Write one byte to the Status Register and
+ * ensure the bits in the mask match the written value.
+ * @nor: pointer to a 'struct spi_nor'.
+ * status_new: byte value to be written to the Status Register.
+ * mask: mask with which to check the written value.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 status_new,
+ u8 mask)
+{
+ int ret;
+
+ nor->bouncebuf[0] = status_new;
+
+ ret = spi_nor_write_sr(nor, &nor->bouncebuf[0], 1);
+ if (ret)
+ return ret;
+
+ ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
+ if (ret)
+ return ret;
+
+ if ((nor->bouncebuf[0] & mask) != (status_new & mask)) {
+ dev_err(nor->dev, "Read back test failed\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+/**
+ * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and the
+ * Status Register 2 in one shot. Ensure that the bits in the mask match the
+ * written value in the Status Register 1, and that the 16-bit Write did not
+ * affect what was already in the Status Register 2.
+ * @nor: pointer to a 'struct spi_nor'.
+ * status_new: byte value to be written to the Status Register 1.
+ * mask: mask with which to check the written value on Status Register 1.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 status_new,
+ u8 mask)
+{
+ int ret;
+ u8 *sr_cr = nor->bouncebuf;
+ u8 cr_written;
+
+ /* Make sure we don't overwrite the contents of Status Register 2. */
+ if (!(nor->flags & SNOR_F_NO_READ_CR)) {
+ ret = spi_nor_read_cr(nor, &sr_cr[1]);
+ if (ret)
+ return ret;
+ } else if (nor->flash.quad_enable) {
+ /*
+ * If the Status Register 2 Read command (35h) is not
+ * supported, we should at least be sure we don't
+ * change the value of the SR2 Quad Enable bit.
+ *
+ * We can safely assume that when the Quad Enable method is
+ * set, the value of the QE bit is one, as a consequence of the
+ * nor->flash.quad_enable() call.
+ *
+ * We can safely assume that the Quad Enable bit is present in
+ * the Status Register 2 at BIT(1). According to the JESD216
+ * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit
+ * Write Status (01h) command is available just for the cases
+ * in which the QE bit is described in SR2 at BIT(1).
+ */
+ sr_cr[1] = CR_QUAD_EN_SPAN;
+ } else {
+ sr_cr[1] = 0;
+ }
+
+ sr_cr[0] = status_new;
+
+ ret = spi_nor_write_sr(nor, sr_cr, 2);
+ if (ret)
+ return ret;
+
+ cr_written = sr_cr[1];
+
+ ret = spi_nor_read_sr(nor, &sr_cr[0]);
+ if (ret)
+ return ret;
+
+ if ((sr_cr[0] & mask) != (status_new & mask)) {
+ dev_err(nor->dev, "Read back test failed\n");
+ return -EIO;
+ }
+
+ if (nor->flags & SNOR_F_NO_READ_CR)
+ return 0;
+
+ ret = spi_nor_read_cr(nor, &sr_cr[1]);
+ if (ret)
+ return ret;
+
+ if (cr_written != sr_cr[1]) {
+ dev_err(nor->dev, "Read back test failed\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+/**
+ * spi_nor_write_sr_and_check() - Write the Status Register and ensure the bits
+ * in the mask match the written values.
+ * @nor: pointer to a 'struct spi_nor'.
+ * status_new: byte value to be written to the Status Register.
+ * mask: mask with which to check the written values.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 status_new,
+ u8 mask)
+{
+ if (nor->flags == SNOR_F_HAS_16BIT_SR)
+ return spi_nor_write_16bit_sr_and_check(nor, status_new, mask);
+
+ return spi_nor_write_sr1_and_check(nor, status_new, mask);
+}
+
static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
{
return mtd->priv;
@@ -1492,24 +1618,6 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
return ret;
}
-/* Write status register and ensure bits in mask match written values */
-static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
-{
- int ret;
-
- nor->bouncebuf[0] = status_new;
-
- ret = spi_nor_write_sr(nor, &nor->bouncebuf[0], 1);
- if (ret)
- return ret;
-
- ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
- if (ret)
- return ret;
-
- return ((nor->bouncebuf[0] & mask) != (status_new & mask)) ? -EIO : 0;
-}
-
static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
uint64_t *len)
{
@@ -1673,7 +1781,7 @@ static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
if ((status_new & mask) < (status_old & mask))
return -EINVAL;
- return write_sr_and_check(nor, status_new, mask);
+ return spi_nor_write_sr_and_check(nor, status_new, mask);
}
/*
@@ -1758,7 +1866,7 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
if ((status_new & mask) > (status_old & mask))
return -EINVAL;
- return write_sr_and_check(nor, status_new, mask);
+ return spi_nor_write_sr_and_check(nor, status_new, mask);
}
/*
@@ -3536,19 +3644,39 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
break;
case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
+ /*
+ * Writing only one byte to the Status Register has the
+ * side-effect of clearing Status Register 2.
+ */
+ /* fall through */
case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
+ nor->flags |= SNOR_F_HAS_16BIT_SR;
+ /*
+ * Read Configuration Register (35h) instruction is not
+ * supported.
+ */
+ nor->flags |= SNOR_F_NO_READ_CR;
flash->quad_enable = spansion_no_read_cr_quad_enable;
break;
case BFPT_DWORD15_QER_SR1_BIT6:
+ nor->flags &= ~SNOR_F_HAS_16BIT_SR;
flash->quad_enable = macronix_quad_enable;
break;
case BFPT_DWORD15_QER_SR2_BIT7:
+ nor->flags &= ~SNOR_F_HAS_16BIT_SR;
flash->quad_enable = sr2_bit7_quad_enable;
break;
case BFPT_DWORD15_QER_SR2_BIT1:
+ /*
+ * JESD216 rev B or later does not specify if writing only one
+ * byte to the Status Register clears or not the Status
+ * Register 2, so let's be cautious and keep the default
+ * assumption of a 16-bit Write Status (01h) command.
+ */
+ nor->flags |= SNOR_F_HAS_16BIT_SR;
flash->quad_enable = spansion_read_cr_quad_enable;
break;
@@ -4515,6 +4643,8 @@ static void spi_nor_info_init_flash_params(struct spi_nor *nor)
flash->quad_enable = spansion_read_cr_quad_enable;
flash->set_4byte = spansion_set_4byte;
flash->setup = spi_nor_default_setup;
+ /* Default to 16-bit Write Status (01h) Command */
+ nor->flags |= SNOR_F_HAS_16BIT_SR;
/* Set SPI NOR sizes. */
flash->size = (u64)info->sector_size * info->n_sectors;
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 12961b157743..fc3a8f5209f0 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -243,6 +243,8 @@ enum spi_nor_option_flags {
SNOR_F_4B_OPCODES = BIT(6),
SNOR_F_HAS_4BAIT = BIT(7),
SNOR_F_HAS_LOCK = BIT(8),
+ SNOR_F_HAS_16BIT_SR = BIT(9),
+ SNOR_F_NO_READ_CR = BIT(10),
};
/**
--
2.9.5
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http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH 17/23] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()
2019-09-17 15:55 ` [PATCH 17/23] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() Tudor.Ambarus
@ 2019-09-19 14:33 ` Vignesh Raghavendra
2019-09-19 15:54 ` Tudor.Ambarus
2019-09-20 5:23 ` Tudor.Ambarus
0 siblings, 2 replies; 31+ messages in thread
From: Vignesh Raghavendra @ 2019-09-19 14:33 UTC (permalink / raw)
To: Tudor.Ambarus, boris.brezillon, marek.vasut, miquel.raynal,
richard, linux-mtd
Cc: linux-aspeed, andrew, linux-kernel, vz, linux-mediatek, joel,
matthias.bgg, computersforpeace, dwmw2, linux-arm-kernel
Hi Tudor
[...]
On 17-Sep-19 9:25 PM, Tudor.Ambarus@microchip.com wrote:
> +static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 status_new,
> + u8 mask)
> +{
> + int ret;
> + u8 *sr_cr = nor->bouncebuf;
> + u8 cr_written;
> +
> + /* Make sure we don't overwrite the contents of Status Register 2. */
> + if (!(nor->flags & SNOR_F_NO_READ_CR)) {
Assuming SNOR_F_NO_READ_CR is not set...
> + ret = spi_nor_read_cr(nor, &sr_cr[1]);
> + if (ret)
> + return ret;
> + } else if (nor->flash.quad_enable) {
> + /*
> + * If the Status Register 2 Read command (35h) is not
> + * supported, we should at least be sure we don't
> + * change the value of the SR2 Quad Enable bit.
> + *
> + * We can safely assume that when the Quad Enable method is
> + * set, the value of the QE bit is one, as a consequence of the
> + * nor->flash.quad_enable() call.
> + *
> + * We can safely assume that the Quad Enable bit is present in
> + * the Status Register 2 at BIT(1). According to the JESD216
> + * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit
> + * Write Status (01h) command is available just for the cases
> + * in which the QE bit is described in SR2 at BIT(1).
> + */
> + sr_cr[1] = CR_QUAD_EN_SPAN;
> + } else {
> + sr_cr[1] = 0;
> + }
> +
CR_QUAD_EN_SPAN will not be in sr_cr[1] when we reach here. So code
won't enable quad mode.
> + sr_cr[0] = status_new;
> +
> + ret = spi_nor_write_sr(nor, sr_cr, 2);
> + if (ret)
> + return ret;
> +
> + cr_written = sr_cr[1];
> +
> + ret = spi_nor_read_sr(nor, &sr_cr[0]);
> + if (ret)
> + return ret;
> +
> + if ((sr_cr[0] & mask) != (status_new & mask)) {
> + dev_err(nor->dev, "Read back test failed\n");
> + return -EIO;
> + }
> +
> + if (nor->flags & SNOR_F_NO_READ_CR)
> + return 0;
> +
> + ret = spi_nor_read_cr(nor, &sr_cr[1]);
> + if (ret)
> + return ret;
> +
> + if (cr_written != sr_cr[1]) {
> + dev_err(nor->dev, "Read back test failed\n");
> + return -EIO;
> + }
> +
> + return 0;
> +}
> +
Regards
Vignesh
______________________________________________________
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^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH 17/23] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()
2019-09-19 14:33 ` Vignesh Raghavendra
@ 2019-09-19 15:54 ` Tudor.Ambarus
2019-09-20 5:23 ` Tudor.Ambarus
1 sibling, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-19 15:54 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, andrew, linux-kernel, vz, linux-mediatek, joel,
matthias.bgg, computersforpeace, dwmw2, linux-arm-kernel
On 09/19/2019 05:33 PM, Vignesh Raghavendra wrote:
> Hi Tudor
>
Hi, Vignesh,
> [...]
>
> On 17-Sep-19 9:25 PM, Tudor.Ambarus@microchip.com wrote:
>> +static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 status_new,
>> + u8 mask)
>> +{
>> + int ret;
>> + u8 *sr_cr = nor->bouncebuf;
>> + u8 cr_written;
>> +
>> + /* Make sure we don't overwrite the contents of Status Register 2. */
>> + if (!(nor->flags & SNOR_F_NO_READ_CR)) {
> Assuming SNOR_F_NO_READ_CR is not set...
>
when SNOR_F_NO_READ_CR is not set, I read the Status Register 2 on the next line:
>> + ret = spi_nor_read_cr(nor, &sr_cr[1]);
>> + if (ret)
>> + return ret;
>> + } else if (nor->flash.quad_enable) {
>> + /*
>> + * If the Status Register 2 Read command (35h) is not
>> + * supported, we should at least be sure we don't
>> + * change the value of the SR2 Quad Enable bit.
>> + *
>> + * We can safely assume that when the Quad Enable method is
>> + * set, the value of the QE bit is one, as a consequence of the
>> + * nor->flash.quad_enable() call.
>> + *
>> + * We can safely assume that the Quad Enable bit is present in
>> + * the Status Register 2 at BIT(1). According to the JESD216
>> + * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit
>> + * Write Status (01h) command is available just for the cases
>> + * in which the QE bit is described in SR2 at BIT(1).
>> + */
when SNOR_F_NO_READ_CR is set and nor->flash.quad_enable != NULL, Status
Register 2 (CR) is equal to CR_QUAD_EN_SPAN.
>> + sr_cr[1] = CR_QUAD_EN_SPAN;
>> + } else {
if SNOR_F_NO_READ_CR is set and nor->flash.quad_enable == NULL we don't need to
enable Quad Mode, so Status Register 2 is 0.
>> + sr_cr[1] = 0;
>> + }
>> +
> CR_QUAD_EN_SPAN will not be in sr_cr[1] when we reach here. So code
> won't enable quad mode.
>
>
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^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH 17/23] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()
2019-09-19 14:33 ` Vignesh Raghavendra
2019-09-19 15:54 ` Tudor.Ambarus
@ 2019-09-20 5:23 ` Tudor.Ambarus
1 sibling, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-20 5:23 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, andrew, linux-kernel, vz, linux-mediatek, joel,
matthias.bgg, computersforpeace, dwmw2, linux-arm-kernel
Hi, Vignesh,
On 09/19/2019 05:33 PM, Vignesh Raghavendra wrote:
> External E-Mail
>
>
> Hi Tudor
>
> [...]
>
> On 17-Sep-19 9:25 PM, Tudor.Ambarus@microchip.com wrote:
>> +static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 status_new,
>> + u8 mask)
>> +{
>> + int ret;
>> + u8 *sr_cr = nor->bouncebuf;
>> + u8 cr_written;
>> +
>> + /* Make sure we don't overwrite the contents of Status Register 2. */
>> + if (!(nor->flags & SNOR_F_NO_READ_CR)) {
>
> Assuming SNOR_F_NO_READ_CR is not set...
>
>> + ret = spi_nor_read_cr(nor, &sr_cr[1]);
>> + if (ret)
>> + return ret;
>> + } else if (nor->flash.quad_enable) {
>> + /*
>> + * If the Status Register 2 Read command (35h) is not
>> + * supported, we should at least be sure we don't
>> + * change the value of the SR2 Quad Enable bit.
>> + *
>> + * We can safely assume that when the Quad Enable method is
>> + * set, the value of the QE bit is one, as a consequence of the
>> + * nor->flash.quad_enable() call.
>> + *
>> + * We can safely assume that the Quad Enable bit is present in
>> + * the Status Register 2 at BIT(1). According to the JESD216
>> + * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit
>> + * Write Status (01h) command is available just for the cases
>> + * in which the QE bit is described in SR2 at BIT(1).
>> + */
>> + sr_cr[1] = CR_QUAD_EN_SPAN;
>> + } else {
>> + sr_cr[1] = 0;
>> + }
>> +
>
> CR_QUAD_EN_SPAN will not be in sr_cr[1] when we reach here. So code
> won't enable quad mode.
>
I get the problem now. spi_nor_write_16bit_sr_and_check() does not modify the
value of the QE bit, which is good in the lock/unlock() case. We want to
lock/unlock() without enabling or disabling the Quad Mode.
As you found, the problem comes later in spi_nor_sr2_bit1_quad_enable() because
I use there spi_nor_write_16bit_sr_and_check() which keeps the value of the QE
bit, without setting it to one, so the spi_nor_sr2_bit1_quad_enable() did not
enable the Quad Mode if not previously enabled.
What I'll do is to introduce a new argument to:
static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 status_new,
u8 mask, bool set_quad_enable)
and do a
if (set_quad_enable)
sr_cr[1] |= CR_QUAD_EN_SPAN;
after initializing sr_cr[1]
The lock/unlock() methods will call the function with set_quad_enable being
false (we don't want to modify the QE value), and the
spi_nor_sr2_bit1_quad_enable() will call it with set_quad_enable being true, we
want to set QE to one (we don't care of the QE bit previous value).
We'll avoid code duplication, lock/unlock() and spi_nor_sr2_bit1_quad_enable()
calling the same method.
Cheers,
ta
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^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 18/23] mtd: spi-nor: Rework macronix_quad_enable()
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
` (16 preceding siblings ...)
2019-09-17 15:55 ` [PATCH 17/23] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() Tudor.Ambarus
@ 2019-09-17 15:55 ` Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 19/23] mtd: spi-nor: Rework spansion(_no)_read_cr_quad_enable() Tudor.Ambarus
` (5 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-17 15:55 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, Tudor.Ambarus, andrew, linux-kernel, vz,
linux-mediatek, joel, matthias.bgg, computersforpeace, dwmw2,
linux-arm-kernel
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Rename method to a generic name: spi_nor_sr1_bit6_quad_enable().
Use spi_nor_write_sr1_and_check(). Now we check the validity of all
the eight bits of the Status Register, not just of the SR1_QUAD_EN_BIT6.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 34 ++++++++++------------------------
include/linux/mtd/spi-nor.h | 2 +-
2 files changed, 11 insertions(+), 25 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 4a513ed13807..2f79923e7db5 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1938,16 +1938,15 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
}
/**
- * macronix_quad_enable() - set QE bit in Status Register.
+ * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status
+ * Register 1.
* @nor: pointer to a 'struct spi_nor'
*
- * Set the Quad Enable (QE) bit in the Status Register.
- *
- * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
+ * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories.
*
* Return: 0 on success, -errno otherwise.
*/
-static int macronix_quad_enable(struct spi_nor *nor)
+static int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor)
{
int ret;
@@ -1955,25 +1954,12 @@ static int macronix_quad_enable(struct spi_nor *nor)
if (ret)
return ret;
- if (nor->bouncebuf[0] & SR_QUAD_EN_MX)
+ if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)
return 0;
- nor->bouncebuf[0] |= SR_QUAD_EN_MX;
+ nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6;
- ret = spi_nor_write_sr(nor, &nor->bouncebuf[0], 1);
- if (ret)
- return ret;
-
- ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
- if (ret)
- return ret;
-
- if (!(nor->bouncebuf[0] & SR_QUAD_EN_MX)) {
- dev_err(nor->dev, "Macronix Quad bit not set\n");
- return -EIO;
- }
-
- return 0;
+ return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0], 0xFF);
}
/**
@@ -2277,7 +2263,7 @@ static void gd25q256_default_init(struct spi_nor *nor)
* indicate the quad_enable method for this case, we need
* to set it in the default_init fixup hook.
*/
- nor->flash.quad_enable = macronix_quad_enable;
+ nor->flash.quad_enable = spi_nor_sr1_bit6_quad_enable;
}
static struct spi_nor_fixups gd25q256_fixups = {
@@ -3661,7 +3647,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
case BFPT_DWORD15_QER_SR1_BIT6:
nor->flags &= ~SNOR_F_HAS_16BIT_SR;
- flash->quad_enable = macronix_quad_enable;
+ flash->quad_enable = spi_nor_sr1_bit6_quad_enable;
break;
case BFPT_DWORD15_QER_SR2_BIT7:
@@ -4558,7 +4544,7 @@ static int spi_nor_setup(struct spi_nor *nor,
static void macronix_set_default_init(struct spi_nor *nor)
{
- nor->flash.quad_enable = macronix_quad_enable;
+ nor->flash.quad_enable = spi_nor_sr1_bit6_quad_enable;
nor->flash.set_4byte = macronix_set_4byte;
}
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index fc3a8f5209f0..3a835de90b6a 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -133,7 +133,7 @@
#define SR_E_ERR BIT(5)
#define SR_P_ERR BIT(6)
-#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
+#define SR1_QUAD_EN_BIT6 BIT(6)
/* Enhanced Volatile Configuration Register bits */
#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
--
2.9.5
______________________________________________________
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^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 19/23] mtd: spi-nor: Rework spansion(_no)_read_cr_quad_enable()
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
` (17 preceding siblings ...)
2019-09-17 15:55 ` [PATCH 18/23] mtd: spi-nor: Rework macronix_quad_enable() Tudor.Ambarus
@ 2019-09-17 15:55 ` Tudor.Ambarus
2019-09-19 17:34 ` Vignesh Raghavendra
2019-09-17 15:55 ` [PATCH 20/23] mtd: spi-nor: Update sr2_bit7_quad_enable() Tudor.Ambarus
` (4 subsequent siblings)
23 siblings, 1 reply; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-17 15:55 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, Tudor.Ambarus, andrew, linux-kernel, vz,
linux-mediatek, joel, matthias.bgg, computersforpeace, dwmw2,
linux-arm-kernel
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Merge:
spansion_no_read_cr_quad_enable()
spansion_read_cr_quad_enable()
in spi_nor_sr2_bit1_quad_enable().
Avoid duplication of code by using spi_nor_write_16bit_sr_and_check(),
the SNOR_F_NO_READ_CR case is treated there.
We now do the Read Back test even for the old
spansion_no_read_cr_quad_enable() case.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 89 ++++++++++---------------------------------
include/linux/mtd/spi-nor.h | 4 +-
2 files changed, 22 insertions(+), 71 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 2f79923e7db5..8648666fb9bd 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -907,7 +907,7 @@ static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 status_new,
* Write Status (01h) command is available just for the cases
* in which the QE bit is described in SR2 at BIT(1).
*/
- sr_cr[1] = CR_QUAD_EN_SPAN;
+ sr_cr[1] = SR2_QUAD_EN_BIT1;
} else {
sr_cr[1] = 0;
}
@@ -1963,81 +1963,34 @@ static int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor)
}
/**
- * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
+ * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status
+ * Register 2.
* @nor: pointer to a 'struct spi_nor'
*
- * Set the Quad Enable (QE) bit in the Configuration Register.
- * This function should be used with QSPI memories not supporting the Read
- * Configuration Register (35h) instruction.
- *
- * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
- * memories.
- *
- * Return: 0 on success, -errno otherwise.
- */
-static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
-{
- u8 *sr_cr = nor->bouncebuf;
- int ret;
-
- /* Keep the current value of the Status Register. */
- ret = spi_nor_read_sr(nor, &sr_cr[0]);
- if (ret)
- return ret;
-
- sr_cr[1] = CR_QUAD_EN_SPAN;
-
- return spi_nor_write_sr(nor, sr_cr, 2);
-}
-
-/**
- * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
- * @nor: pointer to a 'struct spi_nor'
- *
- * Set the Quad Enable (QE) bit in the Configuration Register.
- * This function should be used with QSPI memories supporting the Read
- * Configuration Register (35h) instruction.
- *
- * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
- * memories.
+ * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories.
*
* Return: 0 on success, -errno otherwise.
*/
-static int spansion_read_cr_quad_enable(struct spi_nor *nor)
+static int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
{
- u8 *sr_cr = nor->bouncebuf;
int ret;
- /* Check current Quad Enable bit value. */
- ret = spi_nor_read_cr(nor, &sr_cr[1]);
- if (ret)
- return ret;
-
- if (sr_cr[1] & CR_QUAD_EN_SPAN)
- return 0;
+ if (!(nor->flags & SNOR_F_NO_READ_CR)) {
+ /* Check current Quad Enable bit value. */
+ ret = spi_nor_read_cr(nor, &nor->bouncebuf[0]);
+ if (ret)
+ return ret;
- sr_cr[1] |= CR_QUAD_EN_SPAN;
+ if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1)
+ return 0;
+ }
/* Keep the current value of the Status Register. */
- ret = spi_nor_read_sr(nor, &sr_cr[0]);
- if (ret)
- return ret;
-
- ret = spi_nor_write_sr(nor, sr_cr, 2);
- if (ret)
- return ret;
-
- /* Read back and check it. */
- ret = spi_nor_read_cr(nor, &sr_cr[1]);
+ ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
if (ret)
return ret;
- if (!(sr_cr[1] & CR_QUAD_EN_SPAN)) {
- dev_err(nor->dev, "Spansion Quad bit not set\n");
- return -EIO;
- }
-
- return 0;
+ return spi_nor_write_16bit_sr_and_check(nor, nor->bouncebuf[0], 0xFF);
}
/**
@@ -2117,7 +2070,7 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor)
*
* Read-modify-write function that clears the Block Protection bits from the
* Status Register without affecting other bits. The function is tightly
- * coupled with the spansion_read_cr_quad_enable() function. Both assume that
+ * coupled with the spi_nor_sr2_bit1_quad_enable() function. Both assume that
* the Write Register with 16 bits, together with the Read Configuration
* Register (35h) instructions are supported.
*
@@ -2138,7 +2091,7 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor)
* When the configuration register Quad Enable bit is one, only the
* Write Status (01h) command with two data bytes may be used.
*/
- if (sr_cr[1] & CR_QUAD_EN_SPAN) {
+ if (sr_cr[1] & SR2_QUAD_EN_BIT1) {
ret = spi_nor_read_sr(nor, &sr_cr[0]);
if (ret)
return ret;
@@ -3642,7 +3595,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
* supported.
*/
nor->flags |= SNOR_F_NO_READ_CR;
- flash->quad_enable = spansion_no_read_cr_quad_enable;
+ flash->quad_enable = spi_nor_sr2_bit1_quad_enable;
break;
case BFPT_DWORD15_QER_SR1_BIT6:
@@ -3663,7 +3616,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
* assumption of a 16-bit Write Status (01h) command.
*/
nor->flags |= SNOR_F_HAS_16BIT_SR;
- flash->quad_enable = spansion_read_cr_quad_enable;
+ flash->quad_enable = spi_nor_sr2_bit1_quad_enable;
break;
default:
@@ -4626,7 +4579,7 @@ static void spi_nor_info_init_flash_params(struct spi_nor *nor)
u8 i, erase_mask;
/* Initialize legacy flash parameters and settings. */
- flash->quad_enable = spansion_read_cr_quad_enable;
+ flash->quad_enable = spi_nor_sr2_bit1_quad_enable;
flash->set_4byte = spansion_set_4byte;
flash->setup = spi_nor_default_setup;
/* Default to 16-bit Write Status (01h) Command */
@@ -4844,7 +4797,7 @@ static int spi_nor_init(struct spi_nor *nor)
int err;
if (nor->clear_sr_bp) {
- if (nor->flash.quad_enable == spansion_read_cr_quad_enable)
+ if (nor->flash.quad_enable == spi_nor_sr2_bit1_quad_enable)
nor->clear_sr_bp = spi_nor_spansion_clear_sr_bp;
err = nor->clear_sr_bp(nor);
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 3a835de90b6a..5590a36eb43e 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -144,10 +144,8 @@
#define FSR_P_ERR BIT(4) /* Program operation status */
#define FSR_PT_ERR BIT(1) /* Protection error bit */
-/* Configuration Register bits. */
-#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
-
/* Status Register 2 bits. */
+#define SR2_QUAD_EN_BIT1 BIT(1)
#define SR2_QUAD_EN_BIT7 BIT(7)
/* Supported SPI protocols */
--
2.9.5
______________________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH 19/23] mtd: spi-nor: Rework spansion(_no)_read_cr_quad_enable()
2019-09-17 15:55 ` [PATCH 19/23] mtd: spi-nor: Rework spansion(_no)_read_cr_quad_enable() Tudor.Ambarus
@ 2019-09-19 17:34 ` Vignesh Raghavendra
2019-09-20 4:42 ` Tudor.Ambarus
0 siblings, 1 reply; 31+ messages in thread
From: Vignesh Raghavendra @ 2019-09-19 17:34 UTC (permalink / raw)
To: Tudor.Ambarus, boris.brezillon, marek.vasut, miquel.raynal,
richard, linux-mtd
Cc: linux-aspeed, andrew, linux-kernel, vz, linux-mediatek, joel,
matthias.bgg, computersforpeace, dwmw2, linux-arm-kernel
On 17-Sep-19 9:25 PM, Tudor.Ambarus@microchip.com wrote:
> From: Tudor Ambarus <tudor.ambarus@microchip.com>
>
> Merge:
> spansion_no_read_cr_quad_enable()
> spansion_read_cr_quad_enable()
>
> in spi_nor_sr2_bit1_quad_enable().
>
> Avoid duplication of code by using spi_nor_write_16bit_sr_and_check(),
> the SNOR_F_NO_READ_CR case is treated there.
>
> We now do the Read Back test even for the old
> spansion_no_read_cr_quad_enable() case.
>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> ---
> drivers/mtd/spi-nor/spi-nor.c | 89 ++++++++++---------------------------------
> include/linux/mtd/spi-nor.h | 4 +-
> 2 files changed, 22 insertions(+), 71 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index 2f79923e7db5..8648666fb9bd 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -907,7 +907,7 @@ static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 status_new,
> * Write Status (01h) command is available just for the cases
> * in which the QE bit is described in SR2 at BIT(1).
> */
> - sr_cr[1] = CR_QUAD_EN_SPAN;
> + sr_cr[1] = SR2_QUAD_EN_BIT1;
> } else {
> sr_cr[1] = 0;
> }
> @@ -1963,81 +1963,34 @@ static int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor)
> }
>
> /**
> - * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
> + * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status
> + * Register 2.
> * @nor: pointer to a 'struct spi_nor'
> *
> - * Set the Quad Enable (QE) bit in the Configuration Register.
> - * This function should be used with QSPI memories not supporting the Read
> - * Configuration Register (35h) instruction.
> - *
> - * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
> - * memories.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
> -{
> - u8 *sr_cr = nor->bouncebuf;
> - int ret;
> -
> - /* Keep the current value of the Status Register. */
> - ret = spi_nor_read_sr(nor, &sr_cr[0]);
> - if (ret)
> - return ret;
> -
> - sr_cr[1] = CR_QUAD_EN_SPAN;
> -
> - return spi_nor_write_sr(nor, sr_cr, 2);
> -}
> -
> -/**
> - * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
> - * @nor: pointer to a 'struct spi_nor'
> - *
> - * Set the Quad Enable (QE) bit in the Configuration Register.
> - * This function should be used with QSPI memories supporting the Read
> - * Configuration Register (35h) instruction.
> - *
> - * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
> - * memories.
> + * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories.
> *
> * Return: 0 on success, -errno otherwise.
> */
> -static int spansion_read_cr_quad_enable(struct spi_nor *nor)
> +static int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
> {
> - u8 *sr_cr = nor->bouncebuf;
> int ret;
>
> - /* Check current Quad Enable bit value. */
> - ret = spi_nor_read_cr(nor, &sr_cr[1]);
> - if (ret)
> - return ret;
> -
> - if (sr_cr[1] & CR_QUAD_EN_SPAN)
> - return 0;
> + if (!(nor->flags & SNOR_F_NO_READ_CR)) {
> + /* Check current Quad Enable bit value. */
> + ret = spi_nor_read_cr(nor, &nor->bouncebuf[0]);
> + if (ret)
> + return ret;
>
> - sr_cr[1] |= CR_QUAD_EN_SPAN;
> + if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1)
> + return 0;
> + }
>
> /* Keep the current value of the Status Register. */
> - ret = spi_nor_read_sr(nor, &sr_cr[0]);
> - if (ret)
> - return ret;
> -
> - ret = spi_nor_write_sr(nor, sr_cr, 2);
> - if (ret)
> - return ret;
> -
> - /* Read back and check it. */
> - ret = spi_nor_read_cr(nor, &sr_cr[1]);
> + ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
> if (ret)
> return ret;
>
> - if (!(sr_cr[1] & CR_QUAD_EN_SPAN)) {
> - dev_err(nor->dev, "Spansion Quad bit not set\n");
> - return -EIO;
> - }
> -
> - return 0;
You need to set QE bit here before writing to CR register. This function
does not do that.
> + return spi_nor_write_16bit_sr_and_check(nor, nor->bouncebuf[0], 0xFF);
Neither does spi_nor_write_16bit_sr_and_check().
We need a function that allows to modify SR2/CR register content as well
so as to set QE bit right?
Regards
Vignesh
> }
>
> /**
> @@ -2117,7 +2070,7 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor)
> *
> * Read-modify-write function that clears the Block Protection bits from the
> * Status Register without affecting other bits. The function is tightly
> - * coupled with the spansion_read_cr_quad_enable() function. Both assume that
> + * coupled with the spi_nor_sr2_bit1_quad_enable() function. Both assume that
> * the Write Register with 16 bits, together with the Read Configuration
> * Register (35h) instructions are supported.
> *
> @@ -2138,7 +2091,7 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor)
> * When the configuration register Quad Enable bit is one, only the
> * Write Status (01h) command with two data bytes may be used.
> */
> - if (sr_cr[1] & CR_QUAD_EN_SPAN) {
> + if (sr_cr[1] & SR2_QUAD_EN_BIT1) {
> ret = spi_nor_read_sr(nor, &sr_cr[0]);
> if (ret)
> return ret;
> @@ -3642,7 +3595,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
> * supported.
> */
> nor->flags |= SNOR_F_NO_READ_CR;
> - flash->quad_enable = spansion_no_read_cr_quad_enable;
> + flash->quad_enable = spi_nor_sr2_bit1_quad_enable;
> break;
>
> case BFPT_DWORD15_QER_SR1_BIT6:
> @@ -3663,7 +3616,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
> * assumption of a 16-bit Write Status (01h) command.
> */
> nor->flags |= SNOR_F_HAS_16BIT_SR;
> - flash->quad_enable = spansion_read_cr_quad_enable;
> + flash->quad_enable = spi_nor_sr2_bit1_quad_enable;
> break;
>
> default:
> @@ -4626,7 +4579,7 @@ static void spi_nor_info_init_flash_params(struct spi_nor *nor)
> u8 i, erase_mask;
>
> /* Initialize legacy flash parameters and settings. */
> - flash->quad_enable = spansion_read_cr_quad_enable;
> + flash->quad_enable = spi_nor_sr2_bit1_quad_enable;
> flash->set_4byte = spansion_set_4byte;
> flash->setup = spi_nor_default_setup;
> /* Default to 16-bit Write Status (01h) Command */
> @@ -4844,7 +4797,7 @@ static int spi_nor_init(struct spi_nor *nor)
> int err;
>
> if (nor->clear_sr_bp) {
> - if (nor->flash.quad_enable == spansion_read_cr_quad_enable)
> + if (nor->flash.quad_enable == spi_nor_sr2_bit1_quad_enable)
> nor->clear_sr_bp = spi_nor_spansion_clear_sr_bp;
>
> err = nor->clear_sr_bp(nor);
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> index 3a835de90b6a..5590a36eb43e 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -144,10 +144,8 @@
> #define FSR_P_ERR BIT(4) /* Program operation status */
> #define FSR_PT_ERR BIT(1) /* Protection error bit */
>
> -/* Configuration Register bits. */
> -#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
> -
> /* Status Register 2 bits. */
> +#define SR2_QUAD_EN_BIT1 BIT(1)
> #define SR2_QUAD_EN_BIT7 BIT(7)
>
> /* Supported SPI protocols */
>
______________________________________________________
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^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH 19/23] mtd: spi-nor: Rework spansion(_no)_read_cr_quad_enable()
2019-09-19 17:34 ` Vignesh Raghavendra
@ 2019-09-20 4:42 ` Tudor.Ambarus
0 siblings, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-20 4:42 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, andrew, linux-kernel, vz, linux-mediatek, joel,
matthias.bgg, computersforpeace, dwmw2, linux-arm-kernel
On 09/19/2019 08:34 PM, Vignesh Raghavendra wrote:
>
>
> On 17-Sep-19 9:25 PM, Tudor.Ambarus@microchip.com wrote:
>> From: Tudor Ambarus <tudor.ambarus@microchip.com>
>>
>> Merge:
>> spansion_no_read_cr_quad_enable()
>> spansion_read_cr_quad_enable()
>>
>> in spi_nor_sr2_bit1_quad_enable().
>>
>> Avoid duplication of code by using spi_nor_write_16bit_sr_and_check(),
>> the SNOR_F_NO_READ_CR case is treated there.
>>
>> We now do the Read Back test even for the old
>> spansion_no_read_cr_quad_enable() case.
>>
>> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
>> ---
>> drivers/mtd/spi-nor/spi-nor.c | 89 ++++++++++---------------------------------
>> include/linux/mtd/spi-nor.h | 4 +-
>> 2 files changed, 22 insertions(+), 71 deletions(-)
>>
>> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
>> index 2f79923e7db5..8648666fb9bd 100644
>> --- a/drivers/mtd/spi-nor/spi-nor.c
>> +++ b/drivers/mtd/spi-nor/spi-nor.c
>> @@ -907,7 +907,7 @@ static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 status_new,
>> * Write Status (01h) command is available just for the cases
>> * in which the QE bit is described in SR2 at BIT(1).
>> */
>> - sr_cr[1] = CR_QUAD_EN_SPAN;
>> + sr_cr[1] = SR2_QUAD_EN_BIT1;
>> } else {
>> sr_cr[1] = 0;
>> }
>> @@ -1963,81 +1963,34 @@ static int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor)
>> }
>>
>> /**
>> - * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
>> + * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status
>> + * Register 2.
>> * @nor: pointer to a 'struct spi_nor'
>> *
>> - * Set the Quad Enable (QE) bit in the Configuration Register.
>> - * This function should be used with QSPI memories not supporting the Read
>> - * Configuration Register (35h) instruction.
>> - *
>> - * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
>> - * memories.
>> - *
>> - * Return: 0 on success, -errno otherwise.
>> - */
>> -static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
>> -{
>> - u8 *sr_cr = nor->bouncebuf;
>> - int ret;
>> -
>> - /* Keep the current value of the Status Register. */
>> - ret = spi_nor_read_sr(nor, &sr_cr[0]);
>> - if (ret)
>> - return ret;
>> -
>> - sr_cr[1] = CR_QUAD_EN_SPAN;
>> -
>> - return spi_nor_write_sr(nor, sr_cr, 2);
>> -}
>> -
>> -/**
>> - * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
>> - * @nor: pointer to a 'struct spi_nor'
>> - *
>> - * Set the Quad Enable (QE) bit in the Configuration Register.
>> - * This function should be used with QSPI memories supporting the Read
>> - * Configuration Register (35h) instruction.
>> - *
>> - * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
>> - * memories.
>> + * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories.
>> *
>> * Return: 0 on success, -errno otherwise.
>> */
>> -static int spansion_read_cr_quad_enable(struct spi_nor *nor)
>> +static int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
>> {
>> - u8 *sr_cr = nor->bouncebuf;
>> int ret;
>>
>> - /* Check current Quad Enable bit value. */
>> - ret = spi_nor_read_cr(nor, &sr_cr[1]);
>> - if (ret)
>> - return ret;
>> -
>> - if (sr_cr[1] & CR_QUAD_EN_SPAN)
>> - return 0;
>> + if (!(nor->flags & SNOR_F_NO_READ_CR)) {
>> + /* Check current Quad Enable bit value. */
>> + ret = spi_nor_read_cr(nor, &nor->bouncebuf[0]);
>> + if (ret)
>> + return ret;
>>
>> - sr_cr[1] |= CR_QUAD_EN_SPAN;
>> + if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1)
>> + return 0;
>> + }
>>
>> /* Keep the current value of the Status Register. */
>> - ret = spi_nor_read_sr(nor, &sr_cr[0]);
>> - if (ret)
>> - return ret;
>> -
>> - ret = spi_nor_write_sr(nor, sr_cr, 2);
>> - if (ret)
>> - return ret;
>> -
>> - /* Read back and check it. */
>> - ret = spi_nor_read_cr(nor, &sr_cr[1]);
>> + ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
>> if (ret)
>> return ret;
>>
>> - if (!(sr_cr[1] & CR_QUAD_EN_SPAN)) {
>> - dev_err(nor->dev, "Spansion Quad bit not set\n");
>> - return -EIO;
>> - }
>> -
>> - return 0;
>
> You need to set QE bit here before writing to CR register. This function
> does not do that.>
>> + return spi_nor_write_16bit_sr_and_check(nor, nor->bouncebuf[0], 0xFF);>
> Neither does spi_nor_write_16bit_sr_and_check().
pff, you're right, I thought I did set it in spi_nor_write_16bit_sr_and_check(),
but in spi_nor_write_16bit_sr_and_check() I just read the CR, without setting
the QE bit. Will respin the entire series, thanks for catching this!
> We need a function that allows to modify SR2/CR register content as well
> so as to set QE bit right?
>
> Regards
> Vignesh
>
>> }
>>
>> /**
>> @@ -2117,7 +2070,7 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor)
>> *
>> * Read-modify-write function that clears the Block Protection bits from the
>> * Status Register without affecting other bits. The function is tightly
>> - * coupled with the spansion_read_cr_quad_enable() function. Both assume that
>> + * coupled with the spi_nor_sr2_bit1_quad_enable() function. Both assume that
>> * the Write Register with 16 bits, together with the Read Configuration
>> * Register (35h) instructions are supported.
>> *
>> @@ -2138,7 +2091,7 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor)
>> * When the configuration register Quad Enable bit is one, only the
>> * Write Status (01h) command with two data bytes may be used.
>> */
>> - if (sr_cr[1] & CR_QUAD_EN_SPAN) {
>> + if (sr_cr[1] & SR2_QUAD_EN_BIT1) {
>> ret = spi_nor_read_sr(nor, &sr_cr[0]);
>> if (ret)
>> return ret;
>> @@ -3642,7 +3595,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
>> * supported.
>> */
>> nor->flags |= SNOR_F_NO_READ_CR;
>> - flash->quad_enable = spansion_no_read_cr_quad_enable;
>> + flash->quad_enable = spi_nor_sr2_bit1_quad_enable;
>> break;
>>
>> case BFPT_DWORD15_QER_SR1_BIT6:
>> @@ -3663,7 +3616,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
>> * assumption of a 16-bit Write Status (01h) command.
>> */
>> nor->flags |= SNOR_F_HAS_16BIT_SR;
>> - flash->quad_enable = spansion_read_cr_quad_enable;
>> + flash->quad_enable = spi_nor_sr2_bit1_quad_enable;
>> break;
>>
>> default:
>> @@ -4626,7 +4579,7 @@ static void spi_nor_info_init_flash_params(struct spi_nor *nor)
>> u8 i, erase_mask;
>>
>> /* Initialize legacy flash parameters and settings. */
>> - flash->quad_enable = spansion_read_cr_quad_enable;
>> + flash->quad_enable = spi_nor_sr2_bit1_quad_enable;
>> flash->set_4byte = spansion_set_4byte;
>> flash->setup = spi_nor_default_setup;
>> /* Default to 16-bit Write Status (01h) Command */
>> @@ -4844,7 +4797,7 @@ static int spi_nor_init(struct spi_nor *nor)
>> int err;
>>
>> if (nor->clear_sr_bp) {
>> - if (nor->flash.quad_enable == spansion_read_cr_quad_enable)
>> + if (nor->flash.quad_enable == spi_nor_sr2_bit1_quad_enable)
>> nor->clear_sr_bp = spi_nor_spansion_clear_sr_bp;
>>
>> err = nor->clear_sr_bp(nor);
>> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
>> index 3a835de90b6a..5590a36eb43e 100644
>> --- a/include/linux/mtd/spi-nor.h
>> +++ b/include/linux/mtd/spi-nor.h
>> @@ -144,10 +144,8 @@
>> #define FSR_P_ERR BIT(4) /* Program operation status */
>> #define FSR_PT_ERR BIT(1) /* Protection error bit */
>>
>> -/* Configuration Register bits. */
>> -#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
>> -
>> /* Status Register 2 bits. */
>> +#define SR2_QUAD_EN_BIT1 BIT(1)
>> #define SR2_QUAD_EN_BIT7 BIT(7)
>>
>> /* Supported SPI protocols */
>>
>
______________________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 20/23] mtd: spi-nor: Update sr2_bit7_quad_enable()
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
` (18 preceding siblings ...)
2019-09-17 15:55 ` [PATCH 19/23] mtd: spi-nor: Rework spansion(_no)_read_cr_quad_enable() Tudor.Ambarus
@ 2019-09-17 15:55 ` Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 21/23] mtd: spi-nor: Rework the disabling of block write protection Tudor.Ambarus
` (3 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-17 15:55 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, Tudor.Ambarus, andrew, linux-kernel, vz,
linux-mediatek, joel, matthias.bgg, computersforpeace, dwmw2,
linux-arm-kernel
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Rename the method to spi_nor_sr2_bit7_quad_enable(). Do the
read back test on all the eight bits of the Status Register,
not just the QE one.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 8648666fb9bd..a9cdb6dbc25c 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1994,7 +1994,7 @@ static int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
}
/**
- * sr2_bit7_quad_enable() - set QE bit in Status Register 2.
+ * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2.
* @nor: pointer to a 'struct spi_nor'
*
* Set the Quad Enable (QE) bit in the Status Register 2.
@@ -2005,10 +2005,11 @@ static int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
*
* Return: 0 on success, -errno otherwise.
*/
-static int sr2_bit7_quad_enable(struct spi_nor *nor)
+static int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
{
u8 *sr2 = nor->bouncebuf;
int ret;
+ u8 sr2_written;
/* Check current Quad Enable bit value. */
ret = spi_nor_read_sr2(nor, sr2);
@@ -2025,13 +2026,15 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor)
if (ret)
return ret;
+ sr2_written = *sr2;
+
/* Read back and check it. */
ret = spi_nor_read_sr2(nor, sr2);
if (ret)
return ret;
- if (!(*sr2 & SR2_QUAD_EN_BIT7)) {
- dev_err(nor->dev, "SR2 Quad bit not set\n");
+ if (*sr2 != sr2_written) {
+ dev_err(nor->dev, "Read back test failed\n");
return -EIO;
}
@@ -3605,7 +3608,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
case BFPT_DWORD15_QER_SR2_BIT7:
nor->flags &= ~SNOR_F_HAS_16BIT_SR;
- flash->quad_enable = sr2_bit7_quad_enable;
+ flash->quad_enable = spi_nor_sr2_bit7_quad_enable;
break;
case BFPT_DWORD15_QER_SR2_BIT1:
--
2.9.5
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^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 21/23] mtd: spi-nor: Rework the disabling of block write protection
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
` (19 preceding siblings ...)
2019-09-17 15:55 ` [PATCH 20/23] mtd: spi-nor: Update sr2_bit7_quad_enable() Tudor.Ambarus
@ 2019-09-17 15:55 ` Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 22/23] mtd: spi-nor: Add Global Block Unlock support Tudor.Ambarus
` (2 subsequent siblings)
23 siblings, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-17 15:55 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, Tudor.Ambarus, andrew, linux-kernel, vz,
linux-mediatek, joel, matthias.bgg, computersforpeace, dwmw2,
linux-arm-kernel
From: Tudor Ambarus <tudor.ambarus@microchip.com>
spi_nor_unlock() unlocks blocks of memory or the entire flash memory
array, if requested. clear_sr_bp() unlocks the entire flash memory
array at boot time. This calls for some unification, clear_sr_bp() is
just an optimization for the case when the unlock request covers the
entire flash size.
Get rid of clear_sr_bp() and introduce spi_nor_unlock_all(), which is
just a call to spi_nor_unlock() for the entire flash memory array.
This fixes a bug that was present in spi_nor_spansion_clear_sr_bp().
When the QE bit was zero, we used the Write Status (01h) command with
one data byte, which might cleared the Status Register 2. We now always
use the Write Status (01h) command with two data bytes when
SNOR_F_HAS_16BIT_SR is set, to avoid clearing the Status Register 2.
Get rid of the MFR handling and implement specific manufacturer
default_init() fixup hooks.
Note that this changes a bit the logic for the SNOR_MFR_ATMEL,
SNOR_MFR_INTEL and SNOR_MFR_SST cases. Before this patch, the Atmel,
Intel and SST chips did not set the locking ops, but unlocked the entire
flash at boot time, while now they are setting the locking ops to
stm_locking_ops. This should work, since the the disable of the block
protection at the boot time used the same Status Register bits to unlock
the flash, as in the stm_locking_ops case.
Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 142 +++++++++++++++---------------------------
include/linux/mtd/spi-nor.h | 3 -
2 files changed, 49 insertions(+), 96 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index a9cdb6dbc25c..700b1700a7a1 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -2041,79 +2041,6 @@ static int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
return 0;
}
-/**
- * spi_nor_clear_sr_bp() - clear the Status Register Block Protection bits.
- * @nor: pointer to a 'struct spi_nor'
- *
- * Read-modify-write function that clears the Block Protection bits from the
- * Status Register without affecting other bits.
- *
- * Return: 0 on success, -errno otherwise.
- */
-static int spi_nor_clear_sr_bp(struct spi_nor *nor)
-{
- int ret;
- u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
-
- ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
- if (ret)
- return ret;
-
- nor->bouncebuf[0] &= mask;
-
- ret = spi_nor_write_sr(nor, &nor->bouncebuf[0], 1);
-
- return ret;
-}
-
-/**
- * spi_nor_spansion_clear_sr_bp() - clear the Status Register Block Protection
- * bits on spansion flashes.
- * @nor: pointer to a 'struct spi_nor'
- *
- * Read-modify-write function that clears the Block Protection bits from the
- * Status Register without affecting other bits. The function is tightly
- * coupled with the spi_nor_sr2_bit1_quad_enable() function. Both assume that
- * the Write Register with 16 bits, together with the Read Configuration
- * Register (35h) instructions are supported.
- *
- * Return: 0 on success, -errno otherwise.
- */
-static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor)
-{
- int ret;
- u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
- u8 *sr_cr = nor->bouncebuf;
-
- /* Check current Quad Enable bit value. */
- ret = spi_nor_read_cr(nor, &sr_cr[1]);
- if (ret)
- return ret;
-
- /*
- * When the configuration register Quad Enable bit is one, only the
- * Write Status (01h) command with two data bytes may be used.
- */
- if (sr_cr[1] & SR2_QUAD_EN_BIT1) {
- ret = spi_nor_read_sr(nor, &sr_cr[0]);
- if (ret)
- return ret;
-
- sr_cr[0] &= ~mask;
-
- ret = spi_nor_write_sr(nor, sr_cr, 2);
- if (ret)
- dev_err(nor->dev, "16-bit write register failed\n");
- return ret;
- }
-
- /*
- * If the Quad Enable bit is zero, use the Write Status (01h) command
- * with one data byte.
- */
- return spi_nor_clear_sr_bp(nor);
-}
-
/* Used when the "_ext_id" is two bytes at most */
#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
.id = { \
@@ -4498,6 +4425,16 @@ static int spi_nor_setup(struct spi_nor *nor,
return nor->flash.setup(nor, hwcaps);
}
+static void atmel_set_default_init(struct spi_nor *nor)
+{
+ nor->flags |= SNOR_F_HAS_LOCK;
+}
+
+static void intel_set_default_init(struct spi_nor *nor)
+{
+ nor->flags |= SNOR_F_HAS_LOCK;
+}
+
static void macronix_set_default_init(struct spi_nor *nor)
{
nor->flash.quad_enable = spi_nor_sr1_bit6_quad_enable;
@@ -4511,6 +4448,11 @@ static void st_micron_set_default_init(struct spi_nor *nor)
nor->flash.set_4byte = st_micron_set_4byte;
}
+static void sst_set_default_init(struct spi_nor *nor)
+{
+ nor->flags |= SNOR_F_HAS_LOCK;
+}
+
static void winbond_set_default_init(struct spi_nor *nor)
{
nor->flash.set_4byte = winbond_set_4byte;
@@ -4525,6 +4467,14 @@ static void spi_nor_manufacturer_init_flash_params(struct spi_nor *nor)
{
/* Init flash parameters based on MFR */
switch (JEDEC_MFR(nor->info)) {
+ case SNOR_MFR_ATMEL:
+ atmel_set_default_init(nor);
+ break;
+
+ case SNOR_MFR_INTEL:
+ intel_set_default_init(nor);
+ break;
+
case SNOR_MFR_MACRONIX:
macronix_set_default_init(nor);
break;
@@ -4534,6 +4484,10 @@ static void spi_nor_manufacturer_init_flash_params(struct spi_nor *nor)
st_micron_set_default_init(nor);
break;
+ case SNOR_MFR_SST:
+ sst_set_default_init(nor);
+ break;
+
case SNOR_MFR_WINBOND:
winbond_set_default_init(nor);
break;
@@ -4795,20 +4749,32 @@ static int spi_nor_quad_enable(struct spi_nor *nor)
return nor->flash.quad_enable(nor);
}
+/**
+ * spi_nor_unlock_all() - Unlocks the entire flash memory array.
+ * @nor: pointer to a 'struct spi_nor'
+ *
+ * Some SPI NOR flashes are write protected by default after a power-on reset
+ * cycle, in order to avoid inadvertent writes during power-up. Backward
+ * compatibility imposes to unlock the entire flash memory array at power-up
+ * by default.
+ */
+static int spi_nor_unlock_all(struct spi_nor *nor)
+{
+ if (nor->flags & SNOR_F_HAS_LOCK)
+ return spi_nor_unlock(&nor->mtd, 0, nor->flash.size);
+
+ return 0;
+}
+
static int spi_nor_init(struct spi_nor *nor)
{
int err;
- if (nor->clear_sr_bp) {
- if (nor->flash.quad_enable == spi_nor_sr2_bit1_quad_enable)
- nor->clear_sr_bp = spi_nor_spansion_clear_sr_bp;
-
- err = nor->clear_sr_bp(nor);
- if (err) {
- dev_err(nor->dev,
- "fail to clear block protection bits\n");
- return err;
- }
+ err = spi_nor_unlock_all(nor);
+ if (err) {
+ dev_err(nor->dev,
+ "Failed to unlock the entire flash memory array\n");
+ return err;
}
err = spi_nor_quad_enable(nor);
@@ -4999,16 +4965,6 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
if (info->flags & SPI_NOR_HAS_LOCK)
nor->flags |= SNOR_F_HAS_LOCK;
- /*
- * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
- * with the software protection bits set.
- */
- if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
- JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
- JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
- nor->info->flags & SPI_NOR_HAS_LOCK)
- nor->clear_sr_bp = spi_nor_clear_sr_bp;
-
/* Init flash parameters based on flash_info struct and SFDP */
spi_nor_init_flash_params(nor);
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 5590a36eb43e..ca650f895903 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -578,8 +578,6 @@ struct flash_info;
* @write_proto: the SPI protocol for write operations
* @reg_proto the SPI protocol for read_reg/write_reg/erase operations
* @controller_ops: SPI NOR controller driver specific operations.
- * @clear_sr_bp: [FLASH-SPECIFIC] clears the Block Protection Bits from
- * the SPI NOR Status Register.
* @flash: SPI-NOR flash parameters and settings. The structure
* includes default flash parameters and settings that can
* be overwritten by the spi_nor_fixups hooks, or
@@ -608,7 +606,6 @@ struct spi_nor {
const struct spi_nor_controller_ops *controller_ops;
- int (*clear_sr_bp)(struct spi_nor *nor);
struct spi_nor_flash_parameter flash;
void *priv;
--
2.9.5
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^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 22/23] mtd: spi-nor: Add Global Block Unlock support
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
` (20 preceding siblings ...)
2019-09-17 15:55 ` [PATCH 21/23] mtd: spi-nor: Rework the disabling of block write protection Tudor.Ambarus
@ 2019-09-17 15:55 ` Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 23/23] mtd: spi-nor: Unlock global block protection on sst26vf064b Tudor.Ambarus
2019-09-19 14:37 ` [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Vignesh Raghavendra
23 siblings, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-17 15:55 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, Tudor.Ambarus, andrew, linux-kernel, vz,
linux-mediatek, joel, matthias.bgg, computersforpeace, dwmw2,
linux-arm-kernel
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Add Global Block Unlock support as an optimization for unlocking the
entire memory array. A Global Block-Protection Unlock command offers
a single command cycle that unlocks the entire memory array.
Status Register Block Protection support does not imply the support for
the Global Block Unlock Command. Microchip's SST26VF064B does support
the 98h command, but use dedicated registers for the individual block
protection, and not the Status Register, as in the stm_lock/unlock case.
Call spi_nor_unlock_global_block_protection() in spi_nor_unlock() as an
optimization for unlocking the entire memory array.
Note that the Global Block Unlock command has different names depending
on the manufacturer, but always the same command value: 98h. Macronix's
MX25U12835F names it Gang Block Unlock, Winbound's W25Q128FV names it
Global Block Unlock and Microchip's SST26VF064B names it Global Block
Protection Unlock.
We can't determine this support purely by manufacturer type and it's
not autodetectable by anything like SFDP, so make a new flag for it:
UNLOCK_GLOBAL_BLOCK. This flag can be set just at per-chip level, we
don't need a SNOR_F_ correspondent.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 47 +++++++++++++++++++++++++++++++++++++++++--
include/linux/mtd/spi-nor.h | 1 +
2 files changed, 46 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 700b1700a7a1..19556a9dd3fa 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -196,7 +196,7 @@ struct flash_info {
u16 page_size;
u16 addr_width;
- u16 flags;
+ u32 flags;
#define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
#define SST_WRITE BIT(2) /* use SST byte programming */
@@ -233,6 +233,7 @@ struct flash_info {
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
+#define UNLOCK_GLOBAL_BLOCK BIT(16) /* Unlock global block protection */
/* Part specific fixup hooks. */
const struct spi_nor_fixups *fixups;
@@ -837,6 +838,44 @@ static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
}
/**
+ * spi_nor_unlock_global_block_protection() - Unlock the Global Block Protection
+ * @nor: pointer to a 'struct spi_nor'
+ *
+ * The Global Block-Protection Unlock command offers a single command cycle
+ * that unlocks the entire memory array.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_unlock_global_block_protection(struct spi_nor *nor)
+{
+ int ret;
+
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
+
+ if (nor->spimem) {
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_ULBPR, 1),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_NO_DATA);
+
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ } else {
+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_ULBPR,
+ NULL, 0);
+ }
+
+ if (ret < 0) {
+ dev_err(nor->dev, "error %d on ULBPR\n", ret);
+ return ret;
+ }
+
+ return spi_nor_wait_till_ready(nor);
+}
+
+/**
* spi_nor_write_sr1_and_check() - Write one byte to the Status Register and
* ensure the bits in the mask match the written value.
* @nor: pointer to a 'struct spi_nor'.
@@ -1916,7 +1955,11 @@ static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
if (ret)
return ret;
- ret = nor->flash.locking_ops->unlock(nor, ofs, len);
+ if (nor->info->flags & UNLOCK_GLOBAL_BLOCK &&
+ !ofs && len == nor->flash.size)
+ ret = spi_nor_unlock_global_block_protection(nor);
+ else
+ ret = nor->flash.locking_ops->unlock(nor, ofs, len);
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
return ret;
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index ca650f895903..6812416ab013 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -66,6 +66,7 @@
#define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
#define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
#define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
+#define SPINOR_OP_ULBPR 0x98 /* Global Block Unlock Protection */
/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
#define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
--
2.9.5
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^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 23/23] mtd: spi-nor: Unlock global block protection on sst26vf064b
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
` (21 preceding siblings ...)
2019-09-17 15:55 ` [PATCH 22/23] mtd: spi-nor: Add Global Block Unlock support Tudor.Ambarus
@ 2019-09-17 15:55 ` Tudor.Ambarus
2019-09-19 14:37 ` [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Vignesh Raghavendra
23 siblings, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-17 15:55 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, Tudor.Ambarus, andrew, linux-kernel, vz,
linux-mediatek, joel, matthias.bgg, computersforpeace, dwmw2,
linux-arm-kernel
From: Tudor Ambarus <tudor.ambarus@microchip.com>
To avoid inadvertent writes during power-up, sst26vf064b is
write-protected by default after a power-on reset cycle.
Unlock the serial flash memory by using the Global Block Protection
Unlock command - it offers a single command cycle that unlocks
the entire memory array.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 19556a9dd3fa..19919c9c1bd8 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -2442,7 +2442,9 @@ static const struct flash_info spi_nor_ids[] = {
{ "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
{ "sst26wf016b", INFO(0xbf2651, 0, 64 * 1024, 32, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ UNLOCK_GLOBAL_BLOCK) },
/* ST Microelectronics -- newer production may have feature updates */
{ "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
--
2.9.5
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^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
` (22 preceding siblings ...)
2019-09-17 15:55 ` [PATCH 23/23] mtd: spi-nor: Unlock global block protection on sst26vf064b Tudor.Ambarus
@ 2019-09-19 14:37 ` Vignesh Raghavendra
2019-09-19 16:07 ` Tudor.Ambarus
23 siblings, 1 reply; 31+ messages in thread
From: Vignesh Raghavendra @ 2019-09-19 14:37 UTC (permalink / raw)
To: Tudor.Ambarus, boris.brezillon, marek.vasut, miquel.raynal,
richard, linux-mtd
Cc: linux-aspeed, andrew, linux-kernel, vz, linux-mediatek, joel,
matthias.bgg, computersforpeace, dwmw2, linux-arm-kernel
Hi,
On 17-Sep-19 9:24 PM, Tudor.Ambarus@microchip.com wrote:
> From: Tudor Ambarus <tudor.ambarus@microchip.com>
>
[...]
> Tudor Ambarus (23):
> mtd: spi-nor: hisi-sfc: Drop nor->erase NULL assignment
> mtd: spi-nor: Introduce 'struct spi_nor_controller_ops'
> mtd: spi-nor: cadence-quadspi: Fix cqspi_command_read() definition
> mtd: spi-nor: Rename nor->params to nor->flash
> mtd: spi-nor: Rework read_sr()
> mtd: spi-nor: Rework read_fsr()
> mtd: spi-nor: Rework read_cr()
> mtd: spi-nor: Rework write_enable/disable()
> mtd: spi-nor: Fix retlen handling in sst_write()
> mtd: spi-nor: Rework write_sr()
> mtd: spi-nor: Rework spi_nor_read/write_sr2()
> mtd: spi-nor: Report error in spi_nor_xread_sr()
> mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr()
> mtd: spi-nor: Drop duplicated new line
> mtd: spi-nor: Drop spansion_quad_enable()
> mtd: spi-nor: Fix errno on quad_enable methods
> mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()
> mtd: spi-nor: Rework macronix_quad_enable()
> mtd: spi-nor: Rework spansion(_no)_read_cr_quad_enable()
> mtd: spi-nor: Update sr2_bit7_quad_enable()
> mtd: spi-nor: Rework the disabling of block write protection
> mtd: spi-nor: Add Global Block Unlock support
> mtd: spi-nor: Unlock global block protection on sst26vf064b
With whole series applied, I see:
drivers/mtd/spi-nor/spi-nor.c:520: warning: Function parameter or member 'cr' not described in 'spi_nor_read_cr'
drivers/mtd/spi-nor/spi-nor.c:520: warning: Excess function parameter 'fsr' description in 'spi_nor_read_cr'
drivers/mtd/spi-nor/spi-nor.c:742: warning: Function parameter or member 'len' not described in 'spi_nor_write_sr'
drivers/mtd/spi-nor/spi-nor.c:889: warning: Function parameter or member 'status_new' not described in 'spi_nor_write_sr1_and_check'
drivers/mtd/spi-nor/spi-nor.c:889: warning: Function parameter or member 'mask' not described in 'spi_nor_write_sr1_and_check'
drivers/mtd/spi-nor/spi-nor.c:923: warning: Function parameter or member 'status_new' not described in 'spi_nor_write_16bit_sr_and_check'
drivers/mtd/spi-nor/spi-nor.c:923: warning: Function parameter or member 'mask' not described in 'spi_nor_write_16bit_sr_and_check'
drivers/mtd/spi-nor/spi-nor.c:997: warning: Function parameter or member 'status_new' not described in 'spi_nor_write_sr_and_check'
drivers/mtd/spi-nor/spi-nor.c:997: warning: Function parameter or member 'mask' not described in 'spi_nor_write_sr_and_check'
Could you please fix up docs next time around?
Regards
Vignesh
>
> drivers/mtd/spi-nor/aspeed-smc.c | 23 +-
> drivers/mtd/spi-nor/cadence-quadspi.c | 54 +-
> drivers/mtd/spi-nor/hisi-sfc.c | 23 +-
> drivers/mtd/spi-nor/intel-spi.c | 24 +-
> drivers/mtd/spi-nor/mtk-quadspi.c | 25 +-
> drivers/mtd/spi-nor/nxp-spifi.c | 23 +-
> drivers/mtd/spi-nor/spi-nor.c | 1697 ++++++++++++++++++---------------
> include/linux/mtd/spi-nor.h | 75 +-
> 8 files changed, 1050 insertions(+), 894 deletions(-)
>
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^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods
2019-09-19 14:37 ` [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Vignesh Raghavendra
@ 2019-09-19 16:07 ` Tudor.Ambarus
0 siblings, 0 replies; 31+ messages in thread
From: Tudor.Ambarus @ 2019-09-19 16:07 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, miquel.raynal, richard,
linux-mtd
Cc: linux-aspeed, andrew, linux-kernel, vz, linux-mediatek, joel,
matthias.bgg, computersforpeace, dwmw2, linux-arm-kernel
On 09/19/2019 05:37 PM, Vignesh Raghavendra wrote:
> External E-Mail
>
>
> Hi,
Hi, thanks for reviewing!
>
> On 17-Sep-19 9:24 PM, Tudor.Ambarus@microchip.com wrote:
>> From: Tudor Ambarus <tudor.ambarus@microchip.com>
>>
> [...]
>> Tudor Ambarus (23):
>> mtd: spi-nor: hisi-sfc: Drop nor->erase NULL assignment
>> mtd: spi-nor: Introduce 'struct spi_nor_controller_ops'
>> mtd: spi-nor: cadence-quadspi: Fix cqspi_command_read() definition
>> mtd: spi-nor: Rename nor->params to nor->flash
>> mtd: spi-nor: Rework read_sr()
>> mtd: spi-nor: Rework read_fsr()
>> mtd: spi-nor: Rework read_cr()
>> mtd: spi-nor: Rework write_enable/disable()
>> mtd: spi-nor: Fix retlen handling in sst_write()
>> mtd: spi-nor: Rework write_sr()
>> mtd: spi-nor: Rework spi_nor_read/write_sr2()
>> mtd: spi-nor: Report error in spi_nor_xread_sr()
>> mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr()
>> mtd: spi-nor: Drop duplicated new line
>> mtd: spi-nor: Drop spansion_quad_enable()
>> mtd: spi-nor: Fix errno on quad_enable methods
>> mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()
>> mtd: spi-nor: Rework macronix_quad_enable()
>> mtd: spi-nor: Rework spansion(_no)_read_cr_quad_enable()
>> mtd: spi-nor: Update sr2_bit7_quad_enable()
>> mtd: spi-nor: Rework the disabling of block write protection
>> mtd: spi-nor: Add Global Block Unlock support
>> mtd: spi-nor: Unlock global block protection on sst26vf064b
>
> With whole series applied, I see:
>
> drivers/mtd/spi-nor/spi-nor.c:520: warning: Function parameter or member 'cr' not described in 'spi_nor_read_cr'
> drivers/mtd/spi-nor/spi-nor.c:520: warning: Excess function parameter 'fsr' description in 'spi_nor_read_cr'
> drivers/mtd/spi-nor/spi-nor.c:742: warning: Function parameter or member 'len' not described in 'spi_nor_write_sr'
> drivers/mtd/spi-nor/spi-nor.c:889: warning: Function parameter or member 'status_new' not described in 'spi_nor_write_sr1_and_check'
> drivers/mtd/spi-nor/spi-nor.c:889: warning: Function parameter or member 'mask' not described in 'spi_nor_write_sr1_and_check'
> drivers/mtd/spi-nor/spi-nor.c:923: warning: Function parameter or member 'status_new' not described in 'spi_nor_write_16bit_sr_and_check'
> drivers/mtd/spi-nor/spi-nor.c:923: warning: Function parameter or member 'mask' not described in 'spi_nor_write_16bit_sr_and_check'
> drivers/mtd/spi-nor/spi-nor.c:997: warning: Function parameter or member 'status_new' not described in 'spi_nor_write_sr_and_check'
> drivers/mtd/spi-nor/spi-nor.c:997: warning: Function parameter or member 'mask' not described in 'spi_nor_write_sr_and_check'
>
> Could you please fix up docs next time around?
I'll fix these, thanks!
I've just compiled the code and I can't see the warnings. What should I do to
get these warnings?
Thanks,
ta
>
> Regards
> Vignesh
>>
>> drivers/mtd/spi-nor/aspeed-smc.c | 23 +-
>> drivers/mtd/spi-nor/cadence-quadspi.c | 54 +-
>> drivers/mtd/spi-nor/hisi-sfc.c | 23 +-
>> drivers/mtd/spi-nor/intel-spi.c | 24 +-
>> drivers/mtd/spi-nor/mtk-quadspi.c | 25 +-
>> drivers/mtd/spi-nor/nxp-spifi.c | 23 +-
>> drivers/mtd/spi-nor/spi-nor.c | 1697 ++++++++++++++++++---------------
>> include/linux/mtd/spi-nor.h | 75 +-
>> 8 files changed, 1050 insertions(+), 894 deletions(-)
>>
>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
>
>
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^ permalink raw reply [flat|nested] 31+ messages in thread