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From: <Tudor.Ambarus@microchip.com>
To: <john.garry@huawei.com>, <linux-mtd@lists.infradead.org>
Cc: broonie@kernel.org, chenxiang66@hisilicon.com
Subject: Re: flash_lock issue for n25q 128mb spi nor part
Date: Tue, 3 Dec 2019 12:05:06 +0000	[thread overview]
Message-ID: <f60b2b0a-f3c4-e55c-2087-30b17e81c40a@microchip.com> (raw)
In-Reply-To: <36c733b3-acac-4779-480d-7f0ae1db710e@huawei.com>



On 12/3/19 1:44 PM, John Garry wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 03/12/2019 11:07, Tudor.Ambarus@microchip.com wrote:
>>>> +               bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK);
>>>> +
>>>>           /* Quad Enable Requirements. */
>>>>           switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
>>>>           c
> 
> Hi Tudor,
> 
> ase BFPT_DWORD15_QER_NONE:
>>>>
>>> john@ubuntu:~$ dmesg | grep spi
>>> [   14.935740] spi-nor spi-PRP0001:00: bfpt.dwords[0] = fff920e5
>>> [   14.941480] spi-nor spi-PRP0001:00: bfpt.dwords[1] = 07ffffff
>>> [   14.947215] spi-nor spi-PRP0001:00: bfpt.dwords[2] = 6b27eb29
>>> [   14.952949] spi-nor spi-PRP0001:00: bfpt.dwords[3] = bb273b27
>>> [   14.958683] spi-nor spi-PRP0001:00: bfpt.dwords[4] = ffffffff
>>> [   14.964417] spi-nor spi-PRP0001:00: bfpt.dwords[5] = bb27ffff
>>> [   14.970150] spi-nor spi-PRP0001:00: bfpt.dwords[6] = eb29ffff
>>> [   14.975884] spi-nor spi-PRP0001:00: bfpt.dwords[7] = d810200c
>>> [   14.981618] spi-nor spi-PRP0001:00: bfpt.dwords[8] = 0000520f
>>> [   14.987351] spi-nor spi-PRP0001:00: bfpt.dwords[9] = 00994a24
>>> [   14.993085] spi-nor spi-PRP0001:00: bfpt.dwords[10] = c9038e8b
>>> [   14.998906] spi-nor spi-PRP0001:00: bfpt.dwords[11] = 382701ac
>>> [   15.004726] spi-nor spi-PRP0001:00: bfpt.dwords[12] = 757a757a
>>> [   15.010547] spi-nor spi-PRP0001:00: bfpt.dwords[13] = 5cd5bdfb
>>> [   15.016367] spi-nor spi-PRP0001:00: bfpt.dwords[14] = ff820f4a
>>> [   15.022187] spi-nor spi-PRP0001:00: bfpt.dwords[15] = 00003d81
>>>
>> This falls into the BFPT_DWORD15_QER_NONE case. If there's a correspondence
>> between the BFPT_DWORD15_QER_NONE and no 16-bit Write SR support, we can clear
>> the flag there, but JESD216D does not specify this:(.
>>
>> Please enable CONFIG_DEBUG on top of the file to see dev_dbg messages. I'll try
>> to find a micron flash in the meantime.
>>
> 
> From what you say, the spec seems to be in conflict/unspecified with
> this micron part in terms of using a 16b SR, so I am not sure what a log
> can reveal.
> 
> Anyway here's what I got:
> 
> john@ubuntu:~$ dmesg | grep spi
> [   14.934354] spi-nor spi-PRP0001:00: bfpt.dwords[0] = fff920e5
> [   14.940094] spi-nor spi-PRP0001:00: bfpt.dwords[1] = 07ffffff
> [   14.945828] spi-nor spi-PRP0001:00: bfpt.dwords[2] = 6b27eb29
> [   14.951563] spi-nor spi-PRP0001:00: bfpt.dwords[3] = bb273b27
> [   14.957297] spi-nor spi-PRP0001:00: bfpt.dwords[4] = ffffffff
> [   14.963030] spi-nor spi-PRP0001:00: bfpt.dwords[5] = bb27ffff
> [   14.968764] spi-nor spi-PRP0001:00: bfpt.dwords[6] = eb29ffff
> [   14.974498] spi-nor spi-PRP0001:00: bfpt.dwords[7] = d810200c
> [   14.980231] spi-nor spi-PRP0001:00: bfpt.dwords[8] = 0000520f
> [   14.985965] spi-nor spi-PRP0001:00: bfpt.dwords[9] = 00994a24
> [   14.991699] spi-nor spi-PRP0001:00: bfpt.dwords[10] = c9038e8b
> [   14.997520] spi-nor spi-PRP0001:00: bfpt.dwords[11] = 382701ac
> [   15.003340] spi-nor spi-PRP0001:00: bfpt.dwords[12] = 757a757a
> [   15.009161] spi-nor spi-PRP0001:00: bfpt.dwords[13] = 5cd5bdfb
> [   15.014981] spi-nor spi-PRP0001:00: bfpt.dwords[14] = ff820f4a
> [   15.020801] spi-nor spi-PRP0001:00: bfpt.dwords[15] = 00003d81
> [   15.026624] spi-nor spi-PRP0001:00: bfpt.dwords[BFPT_DWORD(15)] &
> BFPT_DWORD15_QER_MASK =00000000
> [   15.035515] spi-nor spi-PRP0001:00: n25q128a11 (16384 Kbytes)
> [   15.041250] spi-nor spi-PRP0001:00: mtd .name = spi-PRP0001:00, .size
> = 0x1000000 (16MiB), .erasesize = 0x00001000 (4KiB) .numeraseregions = 0
> [   23.338259] spi-nor spi-PRP0001:00: from 0x00ff0000, len 512
> [   23.338380] spi-nor spi-PRP0001:00: from 0x00ff0200, len 512
> [   23.338497] spi-nor spi-PRP0001:00: from 0x00ff0400, len 512
> [   23.338612] spi-nor spi-PRP0001:00: from 0x00ff0600, len 512
> [   23.338728] spi-nor spi-PRP0001:00: from 0x00ff0800, len 512
> [   23.338844] spi-nor spi-PRP0001:00: from 0x00ff0a00, len 512
> [   23.338959] spi-nor spi-PRP0001:00: from 0x00ff0c00, len 512
> [   23.339075] spi-nor spi-PRP0001:00: from 0x00ff0e00, len 512
> [   23.339237] spi-nor spi-PRP0001:00: from 0x00ffe000, len 512
> [   23.339359] spi-nor spi-PRP0001:00: from 0x00ffe200, len 512
> [   23.339474] spi-nor spi-PRP0001:00: from 0x00ffe400, len 512
> [   23.339589] spi-nor spi-PRP0001:00: from 0x00ffe600, len 512
> [   23.339704] spi-nor spi-PRP0001:00: from 0x00ffe800, len 512
> [   23.339818] spi-nor spi-PRP0001:00: from 0x00ffea00, len 512
> [   23.339933] spi-nor spi-PRP0001:00: from 0x00ffec00, len 512
> [   23.340047] spi-nor spi-PRP0001:00: from 0x00ffee00, len 512
> [   23.340188] spi-nor spi-PRP0001:00: from 0x00000000, len 512
> [   23.340306] spi-nor spi-PRP0001:00: from 0x00000200, len 512
> [   23.340422] spi-nor spi-PRP0001:00: from 0x00000400, len 512
> [   23.340539] spi-nor spi-PRP0001:00: from 0x00000600, len 512
> [   23.3401:00: from 0x00000c00, len 512
> [   23.340999] spi-nor spi-PRP0001:00: from 0x00000e00, len 512
> [   23.341139] spi-nor spi-PRP0001:00: from 0x00001000, len 512
> [   23.341257] spi-nor spi-PRP0001:00: from 0x00001200, len 512
> 
> [snip]
> 
> [   23.410270] spi-nor spi-PRP0001:00: from 0x0003ce00, len 512
> [   23.410386] spi-nor spi-PRP0001:00: from 0x0003d000, len 512
> [   23.410502] spi-nor spi-PRP0001:00: from 0x0003d200, len 512
> [   23.410617] spi-nor spi-PRP0001:00: from 0x0003d400, len 512
> [   23.410733] spi-nor spi-PRP0001:00: from 0x0003d600, len 512
> [   23.410849] spi-nor spi-PRP0001:00: from 0x0003d800, len 512
> [   23.410964] spi-nor spi-PRP0001:00: from 0x0003da00, len 512
> [   23.411080] spi-nor spi-PRP0001:00: from 0x0003dc00, len 512
> [   23.411196] spi-nor spi-PRP0001:00: from 0x0003de00, len 512
> [   23.411312] spi-nor spi-PRP0001:00: from 0x0003e000, len 512
> [   23.411428] spi-nor spi-PRP0001:00: from 0x0003e200, len 512
> [   23.411543] spi-nor spi-PRP0001:00: from 0x0003e400, len 512
> [   23.411659] spi-nor spi-PRP0001:00: from 0x0003e600, len 512
> [   23.411775] spi-nor spi-PRP0001:00: from 0x0003e800, len 512
> [   23.411891] spi-nor spi-PRP0001:00: from 0x0003ea00, len 512
> [   23.412007] spi-nor spi-PRP0001:00: from 0x0003ec00, len 512
> [   23.412122] spi-nor spi-PRP0001:00: from 0x0003ee00, len 512
> [   23.412239] spi-nor spi-PRP0001:00: from 0x0003f000, len 512
> [   23.412354] spi-nor spi-PRP0001:00: from 0x0003f200, len 512
> [   23.412470] spi-nor spi-PRP0001:00: from 0x0003f400, len 512
> [   23.412587] spi-nor spi-PRP0001:00: from 0x0003f600, len 512
> [   23.412704] spi-nor spi-PRP0001:00: from 0x0003f800, len 512
> [   23.412819] spi-nor spi-PRP0001:00: from 0x0003fa00, len 512
> [   23.412935] spi-nor spi-PRP00 512
> [   23.413257] spi-nor spi-PRP0001:00: from 0x00040000, len 512
> [   23.413375] spi-nor spi-PRP0001:00: from 0x00040200, len 512
> [   23.413490] spi-nor spi-PRP0001:00: from 0x00040400, len 512
> [   23.413605] spi-nor spi-PRP0001:00: from 0x00040600, len 512
> [   23.413720] spi-nor spi-PRP0001:00: from 0x00040800, len 512
> [   23.413835] spi-nor spi-PRP0001:00: from 0x00040a00, len 512
> [   23.413950] spi-nor spi-PRP0001:00: from 0x00040c00, len 512
> [   23.414065] spi-nor spi-PRP0001:00: from 0x00040e00, len 512
> [   23.414210] spi-nor spi-PRP0001:00: from 0x00200000, len 512
> [   23.414328] spi-nor spi-PRP0001:00: from 0x00200200, len 512
> [   23.414444] spi-nor spi-PRP0001:00: from 0x00200400, len 512
> [   23.414560] spi-nor spi-PRP0001:00: from 0x00200600, len 512
> [   23.414676] spi-nor spi-PRP0001:00: from 0x00200800, len 512
> [   23.414792] spi-nor spi-PRP0001:00: from 0x00200a00, len 512
> [   23.414908] spi-nor spi-PRP0001:00: from 0x00200c00, len 512
> [   23.415024] spi-nor spi-PRP0001:00: from 0x00200e00, len 512
> john@ubuntu:~$
> john@ubuntu:~$
> john@ubuntu:~$
> john@ubuntu:~$ sudo su
> [sudo] password for john:
> root@ubuntu:/home/john# flash_lock -i /dev/mtd0
> Device: /dev/mtd0
> Start: 0
> Len: 0x1000000
> Lock status: unlocked
> Return code: 0
> root@ubuntu:/home/john# flash_lock -l /dev/mtd0 0x800000 0x800000
> root@ubuntu:/home/john# flash_lock -i /dev/mtd0
> Device: /dev/mtd0
> Start: 0
> Len: 0x1000000
> Lock status: unlocked
> Return code: 0
> root@ubuntu:/home/john#
> 

this should reveal what happens after a lock, with the 16 bit status reg write:

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index f4afe123e9dc..f1490c7b5cb9 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1033,10 +1033,19 @@ static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)
 
        sr_cr[0] = sr1;
 
+       dev_err(nor->dev, "before write: sr_cr[0] = %02x, sr_cr[1] = %02x\n",
+               sr_cr[0], sr_cr[1]);
+
        ret = spi_nor_write_sr(nor, sr_cr, 2);
        if (ret)
                return ret;
 
+       ret = spi_nor_read_sr(nor, &sr_cr[0]);
+       if (ret)
+               return ret;
+
+       dev_err(nor->dev, "read back sr1: sr_cr[0] = %02x\n", sr_cr[0]);
+
        if (nor->flags & SNOR_F_NO_READ_CR)
                return 0;
 
@@ -1046,6 +1055,8 @@ static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)
        if (ret)
                return ret;
 
+       dev_err(nor->dev, "read back sr2: sr_cr[1] = %02x\n", sr_cr[1]);
+
        if (cr_written != sr_cr[1]) {
                dev_dbg(nor->dev, "CR: read back test failed\n");
                return -EIO;

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  reply	other threads:[~2019-12-03 12:08 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-02 17:28 flash_lock issue for n25q 128mb spi nor part John Garry
2019-12-03  9:45 ` Tudor.Ambarus
2019-12-03 10:31   ` John Garry
2019-12-03 11:07     ` Tudor.Ambarus
2019-12-03 11:44       ` John Garry
2019-12-03 12:05         ` Tudor.Ambarus [this message]
2019-12-03 12:27           ` Tudor.Ambarus
2019-12-03 12:35             ` John Garry
2019-12-03 13:57               ` John Garry
2019-12-03 14:44                 ` Tudor.Ambarus
2019-12-03 15:29                   ` John Garry
2019-12-04 11:10                     ` John Garry
2019-12-16 18:09                       ` Tudor.Ambarus
2019-12-17  8:57                         ` Vignesh Raghavendra
2019-12-17 10:09                           ` John Garry
2020-01-09 10:36                           ` John Garry
2020-01-10 11:51                             ` Tudor.Ambarus
2020-01-10 11:56                               ` John Garry
2020-01-15  9:28                                 ` John Garry
2020-03-09 10:15                               ` [RESEND PATCH 1/2] mtd: spi-nor: Clear WEL bit when erase or program errors occur Tudor.Ambarus
2020-03-09 10:15                                 ` [RESEND PATCH 2/2] mtd: spi-nor: Fix description of the sr_ready() return value Tudor.Ambarus
2020-03-09 15:04                                 ` [RESEND PATCH 1/2] mtd: spi-nor: Clear WEL bit when erase or program errors occur John Garry
2020-03-23 17:58                                   ` Tudor.Ambarus
2019-12-03 14:16               ` [PATCH] mtd: spi-nor: Fix the write Status Register on micron flashes Tudor.Ambarus
2019-12-03 14:50                 ` [PATCH v2] mtd: spi-nor: Fix the writing of the " Tudor.Ambarus
2019-12-04 10:18                   ` John Garry
2020-01-09 19:14                   ` Miquel Raynal

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