From: Stephen Rothwell <sfr@canb.auug.org.au>
To: Dave Airlie <airlied@linux.ie>
Cc: linux-next@vger.kernel.org, linux-kernel@vger.kernel.org,
Daniel Vetter <daniel.vetter@ffwll.ch>,
Jani Nikula <jani.nikula@intel.com>
Subject: linux-next: manual merge of the drm tree with the drm-intel-fixes tree
Date: Wed, 7 May 2014 13:24:48 +1000 [thread overview]
Message-ID: <20140507132448.d1f892070fa01733ff10b933@canb.auug.org.au> (raw)
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Hi Dave,
Today's linux-next merge of the drm tree got a conflict in
drivers/gpu/drm/i915/i915_gem_gtt.c between commit cfa7c862982b
("drm/i915: Sanitize the enable_ppgtt module option once") from the
drm-intel-fixes tree and commit 5db6c735ead5 ("drm/i915: dmesg output for
VT-d testing") from the drm tree.
I fixed it up (see below) and can carry the fix as necessary (no action
is required).
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
diff --cc drivers/gpu/drm/i915/i915_gem_gtt.c
index 154b0f8bb88d,0d514ff9b94c..000000000000
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@@ -62,62 -48,13 +62,9 @@@ static int sanitize_enable_ppgtt(struc
}
#endif
- /* Full ppgtt disabled by default for now due to issues. */
- if (full)
- return HAS_PPGTT(dev) && (i915.enable_ppgtt == 2);
- else
- return HAS_ALIASING_PPGTT(dev);
+ return HAS_ALIASING_PPGTT(dev) ? 1 : 0;
}
- #define GEN6_PPGTT_PD_ENTRIES 512
- #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
- typedef uint64_t gen8_gtt_pte_t;
- typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
-
- /* PPGTT stuff */
- #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
- #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
-
- #define GEN6_PDE_VALID (1 << 0)
- /* gen6+ has bit 11-4 for physical addr bit 39-32 */
- #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
-
- #define GEN6_PTE_VALID (1 << 0)
- #define GEN6_PTE_UNCACHED (1 << 1)
- #define HSW_PTE_UNCACHED (0)
- #define GEN6_PTE_CACHE_LLC (2 << 1)
- #define GEN7_PTE_CACHE_L3_LLC (3 << 1)
- #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
- #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
-
- /* Cacheability Control is a 4-bit value. The low three bits are stored in *
- * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
- */
- #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
- (((bits) & 0x8) << (11 - 3)))
- #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
- #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
- #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
- #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
- #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
- #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
-
- #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t))
- #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
-
- /* GEN8 legacy style addressis defined as a 3 level page table:
- * 31:30 | 29:21 | 20:12 | 11:0
- * PDPE | PDE | PTE | offset
- * The difference as compared to normal x86 3 level page table is the PDPEs are
- * programmed via register.
- */
- #define GEN8_PDPE_SHIFT 30
- #define GEN8_PDPE_MASK 0x3
- #define GEN8_PDE_SHIFT 21
- #define GEN8_PDE_MASK 0x1ff
- #define GEN8_PTE_SHIFT 12
- #define GEN8_PTE_MASK 0x1ff
-
- #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD)
- #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */
- #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */
- #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */
static void ppgtt_bind_vma(struct i915_vma *vma,
enum i915_cache_level cache_level,
@@@ -2041,15 -1962,11 +1972,20 @@@ int i915_gem_gtt_init(struct drm_devic
gtt->base.total >> 20);
DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
+ /*
+ * i915.enable_ppgtt is read-only, so do an early pass to validate the
+ * user's requested state against the hardware/driver capabilities. We
+ * do this now so that we can print out any log messages once rather
+ * than every time we check intel_enable_ppgtt().
+ */
+ i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
+ DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
+
+ #ifdef CONFIG_INTEL_IOMMU
+ if (intel_iommu_gfx_mapped)
+ DRM_INFO("VT-d active for gfx access\n");
+ #endif
+
return 0;
}
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next reply other threads:[~2014-05-07 3:24 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-07 3:24 Stephen Rothwell [this message]
-- strict thread matches above, loose matches on Subject: below --
2024-03-07 2:10 linux-next: manual merge of the drm tree with the drm-intel-fixes tree Stephen Rothwell
2024-03-07 8:27 ` Joonas Lahtinen
2023-04-17 14:39 broonie
2022-05-17 1:26 Stephen Rothwell
2022-02-25 16:14 broonie
2022-02-22 17:03 broonie
2020-05-08 3:50 Stephen Rothwell
2020-05-07 2:43 Stephen Rothwell
2020-01-22 0:37 Stephen Rothwell
2020-01-08 1:15 Stephen Rothwell
2020-01-08 1:10 Stephen Rothwell
2020-01-08 1:04 Stephen Rothwell
2020-01-08 2:28 ` Stephen Rothwell
2019-10-31 0:33 Stephen Rothwell
2019-11-08 0:42 ` Stephen Rothwell
2018-01-05 1:00 Stephen Rothwell
2017-07-21 1:26 Stephen Rothwell
2017-06-14 0:56 Stephen Rothwell
2017-06-14 0:50 Stephen Rothwell
2017-06-09 2:26 Stephen Rothwell
2017-06-08 2:53 Stephen Rothwell
2017-03-30 1:14 Stephen Rothwell
2017-03-30 1:08 Stephen Rothwell
2017-03-22 0:00 Stephen Rothwell
2017-03-27 17:14 ` Paul McKenney
2017-03-21 23:57 Stephen Rothwell
2017-03-21 0:28 Stephen Rothwell
2016-06-14 2:10 Stephen Rothwell
2015-12-22 23:06 Stephen Rothwell
2015-12-09 2:35 Stephen Rothwell
2015-12-03 14:51 Mark Brown
2015-12-03 15:49 ` Jani Nikula
2015-12-03 14:47 Mark Brown
2015-12-03 14:52 ` Imre Deak
2015-08-17 3:23 Stephen Rothwell
2015-06-05 5:46 mpe@ellerman.id.au
2015-06-05 8:03 ` Jani Nikula
2015-06-09 1:58 ` Stephen Rothwell
2015-03-16 2:30 Stephen Rothwell
2015-03-16 13:43 ` Xi Ruoyao
2015-03-16 15:04 ` Jani Nikula
2014-12-03 2:27 Stephen Rothwell
2014-12-03 8:24 ` Jani Nikula
2014-12-03 8:28 ` Stephen Rothwell
2014-11-17 3:04 Stephen Rothwell
2014-07-23 2:38 Stephen Rothwell
2014-07-09 4:06 Stephen Rothwell
2014-05-22 5:44 Stephen Rothwell
2014-05-22 5:40 Stephen Rothwell
2013-10-28 5:46 Stephen Rothwell
2013-10-28 6:12 ` Stephen Rothwell
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