From: "H. Nikolaus Schaller" <hns@goldelico.com>
To: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Sebastian Reichel <sre@kernel.org>,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
Nikhil Devshatwar <nikhil.nd@ti.com>,
Linux-OMAP <linux-omap@vger.kernel.org>,
dri-devel <dri-devel@lists.freedesktop.org>,
Sekhar Nori <nsekhar@ti.com>, Tony Lindgren <tony@atomide.com>,
Discussions about the Letux Kernel
<letux-kernel@openphoenux.org>
Subject: Re: [PATCH v3 00/56] Convert DSI code to use drm_mipi_dsi and drm_panel
Date: Mon, 16 Nov 2020 10:16:18 +0100 [thread overview]
Message-ID: <A74325A5-90CC-44C8-8824-7D551B53B314@goldelico.com> (raw)
In-Reply-To: <27cfb13a-62e3-0a53-153f-92641c437cee@ti.com>
[-- Attachment #1: Type: text/plain, Size: 2962 bytes --]
Hi Tomi,
I hope you had a good weekend.
And I have added back the CC: list because I think we have progress after our internal discussion and only one issue remaining.
> Am 13.11.2020 um 15:49 schrieb Tomi Valkeinen <tomi.valkeinen@ti.com>:
>
> On 13/11/2020 16:41, H. Nikolaus Schaller wrote:
>> Hi Tomi,
>>
>>> Am 13.11.2020 um 14:38 schrieb Tomi Valkeinen <tomi.valkeinen@ti.com>:
>>>
>>> On 13/11/2020 15:35, H. Nikolaus Schaller wrote:
>>>
>>>> So I'd say dsi_vc_send_short() fails if dsi_vc_enable_hs(0, 0) and not dsi_vc_enable_hs(0, 1)
>>>
>>> Oh, forgot to mention this: remove MIPI_DSI_MODE_LPM from the panel driver.
>>
>> Yes! This makes sending the init sequence work.
>>
>> I just have failures from w677l_read() but that may be the panel driver wrapper code.
>
> Ok, great! It would be good to have reads working too.
I have fixed it. The call to mipi_dsi_dcs_read() was wrong.
> That way we can know for sure if the commands
> go back and forth correctly (e.g. verify the panel version ID).
I can now read registers. Panel version ID is nonsense but I know that it was before.
Maybe they did not flash it during production since I only read 0x40,0x00,0x00.
But we can read it.
>
>> If I remove all read commands (they are not necessary for operation), there are no error
>> messages and everything succeeds. I have a /dev/fb0.
>>
>> But I have no picture yet.
>>
>> Initially I thought that it was just the missing code to handle an external PWM backlight.
>> But even with (and backlight working), I have just a framebuffer with black screen.
>>
>> Anyways, I think we are very close. And this is a great step forwards so that I need a
>> break...
>>
>> Maybe I manage to consolidate the panel driver code before v5.10-rc4 arrives. This
>> would give a freshly merged letux tree.
>
> Usually backlight glow is visible even if there's no picture.
Well, it did not turn the PWM on at all. Now this works as well.
Still I have no picture. But the readout of the register 0x45 (scan line) shows varying
values. Therefore I think the vsync is running and incrementing the scan line counter.
> But a comparison between the old, working driver, with dsi debugs enabled, may give some hints. A
> DISPC & DSI reg dump for both cases may also give hints.
I have a script to mount debugfs and dump registers. Results are attached.
Significant difference seem to be in:
DISPC_TIMING_H(LCD)
DSI_CLK_CTRL
DSI_VM_TIMING1
DSI_VM_TIMING6
DSI_VC_CTRL(0)
DSI_VC_CTRL(1)
DSI_DSIPHY_CFG2
The consolidated panel driver code is here:
https://git.goldelico.com/?p=letux-kernel.git;a=shortlog;h=refs/heads/letux/boe-w677-dsi-panel-v2
Well, not yet clean for upstreaming but functionally much better than before.
What I have hacked is to mask out MIPI_DSI_MODE_LPM in mipi_dsi_attach(). This
can/will be replaced if your series can handle it.
BR,
Nikolaus
[-- Attachment #2: dsi-new.txt --]
[-- Type: text/plain, Size: 22233 bytes --]
root@letux:~# ./debugdsi
- DSS -
FCK = 192000000
- DISPC -
dispc fclk source = FCK
fck 192000000
- DISPC-CORE-CLK -
lck 192000000 lck div 1
- LCD -
LCD clk source = PLL1:1
lck 153600000 lck div 1
pck 76800000 pck div 2
- LCD2 -
LCD2 clk source = FCK
lck 48000000 lck div 4
pck 48000000 pck div 1
- LCD3 -
LCD3 clk source = FCK
lck 48000000 lck div 4
pck 48000000 pck div 1
DISPC_REVISION 00000051
DISPC_SYSCONFIG 00002015
DISPC_SYSSTATUS 00000001
DISPC_IRQSTATUS 000000a2
DISPC_IRQENABLE 0812d640
DISPC_CONTROL 00018309
DISPC_CONFIG 0000020c
DISPC_CAPABLE 00000000
DISPC_LINE_STATUS 000003e3
DISPC_LINE_NUMBER 00000000
DISPC_GLOBAL_ALPHA ffffffff
DISPC_CONTROL2 00000000
DISPC_CONFIG2 00000000
DISPC_CONTROL3 00000000
DISPC_CONFIG3 00000000
DISPC_GLOBAL_MFLAG_ATTRIBUTE 00000001
DISPC_DEFAULT_COLOR(LCD) 00000000
DISPC_TRANS_COLOR(LCD) 00000000
DISPC_SIZE_MGR(LCD) 04ff02cf
DISPC_TIMING_H(LCD) 0040a100
DISPC_TIMING_V(LCD) 0320323b
DISPC_POL_FREQ(LCD) 00060000
DISPC_DIVISORo(LCD) 00010002
DISPC_DATA_CYCLE1(LCD) 00000000
DISPC_DATA_CYCLE2(LCD) 00000000
DISPC_DATA_CYCLE3(LCD) 00000000
DISPC_CPR_COEF_R(LCD) 00000000
DISPC_CPR_COEF_G(LCD) 00000000
DISPC_CPR_COEF_B(LCD) 00000000
DISPC_DEFAULT_COLOR(TV) 00000000
DISPC_TRANS_COLOR(TV) 00000000
DISPC_SIZE_MGR(TV) 00000000
DISPC_DEFAULT_COLOR(LCD2) 00000000
DISPC_TRANS_COLOR(LCD2) 00000000
DISPC_SIZE_MGR(LCD2) 00000000
DISPC_TIMING_H(LCD2) 00000000
DISPC_TIMING_V(LCD2) 00000000
DISPC_POL_FREQ(LCD2) 00000000
DISPC_DIVISORo(LCD2) 00040001
DISPC_DATA_CYCLE1(LCD2) 00000000
DISPC_DATA_CYCLE2(LCD2) 00000000
DISPC_DATA_CYCLE3(LCD2) 00000000
DISPC_CPR_COEF_R(LCD2) 00000000
DISPC_CPR_COEF_G(LCD2) 00000000
DISPC_CPR_COEF_B(LCD2) 00000000
DISPC_DEFAULT_COLOR(LCD3) 00000000
DISPC_TRANS_COLOR(LCD3) 00000000
DISPC_SIZE_MGR(LCD3) 00000000
DISPC_TIMING_H(LCD3) 00000000
DISPC_TIMING_V(LCD3) 00000000
DISPC_POL_FREQ(LCD3) 00000000
DISPC_DIVISORo(LCD3) 00040001
DISPC_DATA_CYCLE1(LCD3) 00000000
DISPC_DATA_CYCLE2(LCD3) 00000000
DISPC_DATA_CYCLE3(LCD3) 00000000
DISPC_CPR_COEF_R(LCD3) 00000000
DISPC_CPR_COEF_G(LCD3) 00000000
DISPC_CPR_COEF_B(LCD3) 00000000
DISPC_OVL_BA0(GFX) 10100000
DISPC_OVL_BA1(GFX) 10100000
DISPC_OVL_POSITION(GFX) 00000000
DISPC_OVL_SIZE(GFX) 04ff02cf
DISPC_OVL_ATTRIBUTES(GFX) 320040b1
DISPC_OVL_FIFO_THRESHOLD(GFX) 07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(GFX) 00000500
DISPC_OVL_ROW_INC(GFX) 000074c1
DISPC_OVL_PIXEL_INC(GFX) 00000001
DISPC_OVL_PRELOAD(GFX) 000007ff
DISPC_OVL_MFLAG_THRESHOLD(GFX) 05000400
DISPC_OVL_WINDOW_SKIP(GFX) 00000000
DISPC_OVL_TABLE_BA(GFX) 00000000
DISPC_OVL_BA0(VID1) 00000000
DISPC_OVL_BA1(VID1) 00000000
DISPC_OVL_POSITION(VID1) 00000000
DISPC_OVL_SIZE(VID1) 00000000
DISPC_OVL_ATTRIBUTES(VID1) 02808400
DISPC_OVL_FIFO_THRESHOLD(VID1) 07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(VID1) 00000800
DISPC_OVL_ROW_INC(VID1) 00000001
DISPC_OVL_PIXEL_INC(VID1) 00000001
DISPC_OVL_PRELOAD(VID1) 000007ff
DISPC_OVL_MFLAG_THRESHOLD(VID1) 05000400
DISPC_OVL_FIR(VID1) 04000400
DISPC_OVL_PICTURE_SIZE(VID1) 00000000
DISPC_OVL_ACCU0(VID1) 00000000
DISPC_OVL_ACCU1(VID1) 00000000
DISPC_OVL_BA0_UV(VID1) 00000000
DISPC_OVL_BA1_UV(VID1) 00000000
DISPC_OVL_FIR2(VID1) 04000400
DISPC_OVL_ACCU2_0(VID1) 00000000
DISPC_OVL_ACCU2_1(VID1) 00000000
DISPC_OVL_ATTRIBUTES2(VID1) 00000000
DISPC_OVL_BA0(VID2) 00000000
DISPC_OVL_BA1(VID2) 00000000
DISPC_OVL_POSITION(VID2) 00000000
DISPC_OVL_SIZE(VID2) 00000000
DISPC_OVL_ATTRIBUTES(VID2) 02808400
DISPC_OVL_FIFO_THRESHOLD(VID2) 07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(VID2) 00000800
DISPC_OVL_ROW_INC(VID2) 00000001
DISPC_OVL_PIXEL_INC(VID2) 00000001
DISPC_OVL_PRELOAD(VID2) 000007ff
DISPC_OVL_MFLAG_THRESHOLD(VID2) 05000400
DISPC_OVL_FIR(VID2) 04000400
DISPC_OVL_PICTURE_SIZE(VID2) 00000000
DISPC_OVL_ACCU0(VID2) 00000000
DISPC_OVL_ACCU1(VID2) 00000000
DISPC_OVL_BA0_UV(VID2) 00000000
DISPC_OVL_BA1_UV(VID2) 00000000
DISPC_OVL_FIR2(VID2) 04000400
DISPC_OVL_ACCU2_0(VID2) 00000000
DISPC_OVL_ACCU2_1(VID2) 00000000
DISPC_OVL_ATTRIBUTES2(VID2) 00000000
DISPC_OVL_BA0(VID3) 00000000
DISPC_OVL_BA1(VID3) 00000000
DISPC_OVL_POSITION(VID3) 00000000
DISPC_OVL_SIZE(VID3) 00000000
DISPC_OVL_ATTRIBUTES(VID3) 02808400
DISPC_OVL_FIFO_THRESHOLD(VID3) 07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(VID3) 00000800
DISPC_OVL_ROW_INC(VID3) 00000001
DISPC_OVL_PIXEL_INC(VID3) 00000001
DISPC_OVL_PRELOAD(VID3) 000007ff
DISPC_OVL_MFLAG_THRESHOLD(VID3) 05000400
DISPC_OVL_FIR(VID3) 04000400
DISPC_OVL_PICTURE_SIZE(VID3) 00000000
DISPC_OVL_ACCU0(VID3) 00000000
DISPC_OVL_ACCU1(VID3) 00000000
DISPC_OVL_BA0_UV(VID3) 00000000
DISPC_OVL_BA1_UV(VID3) 00000000
DISPC_OVL_FIR2(VID3) 04000400
DISPC_OVL_ACCU2_0(VID3) 00000000
DISPC_OVL_ACCU2_1(VID3) 00000000
DISPC_OVL_ATTRIBUTES2(VID3) 00000000
DISPC_OVL_BA0(WB) 00000000
DISPC_OVL_BA1(WB) 00000000
DISPC_OVL_SIZE(WB) 00000000
DISPC_OVL_ATTRIBUTES(WB) 00808000
DISPC_OVL_FIFO_THRESHOLD(WB) 00080000
DISPC_OVL_FIFO_SIZE_STATUS(WB) 00000800
DISPC_OVL_ROW_INC(WB) 00000001
DISPC_OVL_PIXEL_INC(WB) 00000001
DISPC_OVL_MFLAG_THRESHOLD(WB) 03200280
DISPC_OVL_FIR(WB) 04000400
DISPC_OVL_PICTURE_SIZE(WB) 00000000
DISPC_OVL_ACCU0(WB) 00000000
DISPC_OVL_ACCU1(WB) 00000000
DISPC_OVL_BA0_UV(WB) 00000000
DISPC_OVL_BA1_UV(WB) 00000000
DISPC_OVL_FIR2(WB) 04000400
DISPC_OVL_ACCU2_0(WB) 00000000
DISPC_OVL_ACCU2_1(WB) 00000000
DISPC_OVL_ATTRIBUTES2(WB) 00000000
DISPC_OVL_FIR_COEF_H_0(VID1) 00000000
DISPC_OVL_FIR_COEF_H_1(VID1) 00000000
DISPC_OVL_FIR_COEF_H_2(VID1) 00000000
DISPC_OVL_FIR_COEF_H_3(VID1) 00000000
DISPC_OVL_FIR_COEF_H_4(VID1) 00000000
DISPC_OVL_FIR_COEF_H_5(VID1) 00000000
DISPC_OVL_FIR_COEF_H_6(VID1) 00000000
DISPC_OVL_FIR_COEF_H_7(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_0(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_1(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_2(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_3(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_4(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_5(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_6(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_7(VID1) 00000000
DISPC_OVL_CONV_COEF_0(VID1) 0199012a
DISPC_OVL_CONV_COEF_1(VID1) 012a0000
DISPC_OVL_CONV_COEF_2(VID1) 079c0730
DISPC_OVL_CONV_COEF_3(VID1) 0000012a
DISPC_OVL_CONV_COEF_4(VID1) 00000204
DISPC_OVL_FIR_COEF_V_0(VID1) 00000000
DISPC_OVL_FIR_COEF_V_1(VID1) 00000000
DISPC_OVL_FIR_COEF_V_2(VID1) 00000000
DISPC_OVL_FIR_COEF_V_3(VID1) 00000000
DISPC_OVL_FIR_COEF_V_4(VID1) 00000000
DISPC_OVL_FIR_COEF_V_5(VID1) 00000000
DISPC_OVL_FIR_COEF_V_6(VID1) 00000000
DISPC_OVL_FIR_COEF_V_7(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_0(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_1(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_2(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_3(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_4(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_5(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_6(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_7(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_0(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_1(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_2(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_3(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_4(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_5(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_6(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_7(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_0(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_1(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_2(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_3(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_4(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_5(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_6(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_7(VID1) 00000000
DISPC_OVL_FIR_COEF_H_0(VID2) 00000000
DISPC_OVL_FIR_COEF_H_1(VID2) 00000000
DISPC_OVL_FIR_COEF_H_2(VID2) 00000000
DISPC_OVL_FIR_COEF_H_3(VID2) 00000000
DISPC_OVL_FIR_COEF_H_4(VID2) 00000000
DISPC_OVL_FIR_COEF_H_5(VID2) 00000000
DISPC_OVL_FIR_COEF_H_6(VID2) 00000000
DISPC_OVL_FIR_COEF_H_7(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_0(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_1(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_2(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_3(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_4(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_5(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_6(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_7(VID2) 00000000
DISPC_OVL_CONV_COEF_0(VID2) 0199012a
DISPC_OVL_CONV_COEF_1(VID2) 012a0000
DISPC_OVL_CONV_COEF_2(VID2) 079c0730
DISPC_OVL_CONV_COEF_3(VID2) 0000012a
DISPC_OVL_CONV_COEF_4(VID2) 00000204
DISPC_OVL_FIR_COEF_V_0(VID2) 00000000
DISPC_OVL_FIR_COEF_V_1(VID2) 00000000
DISPC_OVL_FIR_COEF_V_2(VID2) 00000000
DISPC_OVL_FIR_COEF_V_3(VID2) 00000000
DISPC_OVL_FIR_COEF_V_4(VID2) 00000000
DISPC_OVL_FIR_COEF_V_5(VID2) 00000000
DISPC_OVL_FIR_COEF_V_6(VID2) 00000000
DISPC_OVL_FIR_COEF_V_7(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_0(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_1(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_2(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_3(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_4(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_5(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_6(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_7(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_0(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_1(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_2(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_3(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_4(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_5(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_6(VID2) 00000000
[ 117.525871] DSI: dsi_runtime_get
[ 117.532527] DSI: dsi_runtime_put
DISPC_OVL_FIR_COEF_HV2_7(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_0(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_1(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_2(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_3(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_4(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_5(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_6(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_7(VID2) 00000000
DISPC_OVL_FIR_COEF_H_0(VID3) 00000000
DISPC_OVL_FIR_COEF_H_1(VID3) 00000000
DISPC_OVL_FIR_COEF_H_2(VID3) 00000000
DISPC_OVL_FIR_COEF_H_3(VID3) 00000000
DISPC_OVL_FIR_COEF_H_4(VID3) 00000000
DISPC_OVL_FIR_COEF_H_5(VID3) 00000000
DISPC_OVL_FIR_COEF_H_6(VID3) 00000000
DISPC_OVL_FIR_COEF_H_7(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_0(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_1(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_2(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_3(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_4(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_5(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_6(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_7(VID3) 00000000
DISPC_OVL_CONV_COEF_0(VID3) 0199012a
DISPC_OVL_CONV_COEF_1(VID3) 012a0000
DISPC_OVL_CONV_COEF_2(VID3) 079c0730
DISPC_OVL_CONV_COEF_3(VID3) 0000012a
DISPC_OVL_CONV_COEF_4(VID3) 00000204
DISPC_OVL_FIR_COEF_V_0(VID3) 00000000
DISPC_OVL_FIR_COEF_V_1(VID3) 00000000
DISPC_OVL_FIR_COEF_V_2(VID3) 00000000
DISPC_OVL_FIR_COEF_V_3(VID3) 00000000
DISPC_OVL_FIR_COEF_V_4(VID3) 00000000
DISPC_OVL_FIR_COEF_V_5(VID3) 00000000
DISPC_OVL_FIR_COEF_V_6(VID3) 00000000
DISPC_OVL_FIR_COEF_V_7(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_0(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_1(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_2(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_3(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_4(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_5(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_6(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_7(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_0(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_1(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_2(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_3(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_4(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_5(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_6(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_7(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_0(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_1(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_2(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_3(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_4(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_5(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_6(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_7(VID3) 00000000
cat: /sys/kernel/debug/omapdss/dsi1_irqs: No such file or directory
DSI_REVISION 00000040
DSI_SYSCONFIG 00000015
DSI_SYSSTATUS 00000001
DSI_IRQSTATUS 00000000
DSI_IRQENABLE 0015c000
DSI_CTRL 00eaee9f
DSI_COMPLEXIO_CFG1 2a0dcba9
DSI_COMPLEXIO_IRQ_STATUS 00000000
DSI_COMPLEXIO_IRQ_ENABLE 3ff07fff
DSI_CLK_CTRL a030400b
DSI_TIMING1 ffff1000
DSI_TIMING2 ffffffff
DSI_VM_TIMING1 00078003
DSI_VM_TIMING2 043c3232
DSI_VM_TIMING3 029a0500
DSI_CLK_TIMING 00001b10
DSI_TX_FIFO_VC_SIZE 13121110
DSI_RX_FIFO_VC_SIZE 13121110
DSI_COMPLEXIO_CFG2 00030000
DSI_RX_FIFO_VC_FULLNESS 00000000
DSI_VM_TIMING4 00000000
DSI_TX_FIFO_VC_EMPTINESS 1f1f1e1f
DSI_VM_TIMING5 00000000
DSI_VM_TIMING6 01000007
DSI_VM_TIMING7 00100010
DSI_STOPCLK_TIMING 00000080
DSI_VC_CTRL(0) 20808f81
DSI_VC_TE(0) 00000000
DSI_VC_LONG_PACKET_HEADER(0) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(0) 00000000
DSI_VC_SHORT_PACKET_HEADER(0) 00000000
DSI_VC_IRQSTATUS(0) 00000000
DSI_VC_IRQENABLE(0) 000000db
DSI_VC_CTRL(1) 20808fb1
DSI_VC_TE(1) 00000000
DSI_VC_LONG_PACKET_HEADER(1) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(1) 00000000
DSI_VC_SHORT_PACKET_HEADER(1) 00000000
DSI_VC_IRQSTATUS(1) 00000000
DSI_VC_IRQENABLE(1) 000000db
DSI_VC_CTRL(2) 20808d81
DSI_VC_TE(2) 00000000
DSI_VC_LONG_PACKET_HEADER(2) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(2) 00000000
DSI_VC_SHORT_PACKET_HEADER(2) 00000000
DSI_VC_IRQSTATUS(2) 00000000
DSI_VC_IRQENABLE(2) 000000db
DSI_VC_CTRL(3) 20808d81
DSI_VC_TE(3) 00000000
DSI_VC_LONG_PACKET_HEADER(3) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(3) 00000000
DSI_VC_SHORT_PACKET_HEADER(3) 00000000
DSI_VC_IRQSTATUS(3) 00000000
DSI_VC_IRQENABLE(3) 000000db
DSI_DSIPHY_CFG0 132b1322
DSI_DSIPHY_CFG1 42c6103c
DSI_DSIPHY_CFG2 b83e000f
DSI_DSIPHY_CFG5 ff000000
DSI_PLL_CONTROL 00000018
DSI_PLL_STATUS 00006383
DSI_PLL_GO 00000000
DSI_PLL_CONFIGURATION1 10a03000
DSI_PLL_CONFIGURATION2 00656004
root@letux:~#
[-- Attachment #3: dsi-oldi.txt --]
[-- Type: text/plain, Size: 22161 bytes --]
root@letux:~# ./debugdsi
- DSS -
FCK = 192000000
- DISPC -
dispc fclk source = FCK
fck 192000000
- DISPC-CORE-CLK -
lck 192000000 lck div 1
- LCD -
LCD clk source = PLL1:1
lck 153600000 lck div 1
pck 76800000 pck div 2
- LCD2 -
LCD2 clk source = FCK
lck 48000000 lck div 4
pck 48000000 pck div 1
- LCD3 -
LCD3 clk source = FCK
lck 48000000 lck div 4
pck 48000000 pck div 1
DISPC_REVISION 00000051
DISPC_SYSCONFIG 00002015
DISPC_SYSSTATUS 00000001
DISPC_IRQSTATUS 000000a2
DISPC_IRQENABLE 0812d640
DISPC_CONTROL 00018309
DISPC_CONFIG 0000020c
DISPC_CAPABLE 00000000
DISPC_LINE_STATUS 000001af
DISPC_LINE_NUMBER 00000000
DISPC_GLOBAL_ALPHA ffffffff
DISPC_CONTROL2 00000000
DISPC_CONFIG2 00000000
DISPC_CONTROL3 00000000
DISPC_CONFIG3 00000000
DISPC_GLOBAL_MFLAG_ATTRIBUTE 00000001
DISPC_DEFAULT_COLOR(LCD) 00000000
DISPC_TRANS_COLOR(LCD) 00000000
DISPC_SIZE_MGR(LCD) 04ff02cf
DISPC_TIMING_H(LCD) 09d00800
DISPC_TIMING_V(LCD) 0320323b
DISPC_POL_FREQ(LCD) 00060000
DISPC_DIVISORo(LCD) 00010002
DISPC_DATA_CYCLE1(LCD) 00000000
DISPC_DATA_CYCLE2(LCD) 00000000
DISPC_DATA_CYCLE3(LCD) 00000000
DISPC_CPR_COEF_R(LCD) 00000000
DISPC_CPR_COEF_G(LCD) 00000000
DISPC_CPR_COEF_B(LCD) 00000000
DISPC_DEFAULT_COLOR(TV) 00000000
DISPC_TRANS_COLOR(TV) 00000000
DISPC_SIZE_MGR(TV) 00000000
DISPC_DEFAULT_COLOR(LCD2) 00000000
DISPC_TRANS_COLOR(LCD2) 00000000
DISPC_SIZE_MGR(LCD2) 00000000
DISPC_TIMING_H(LCD2) 00000000
DISPC_TIMING_V(LCD2) 00000000
DISPC_POL_FREQ(LCD2) 00000000
DISPC_DIVISORo(LCD2) 00040001
DISPC_DATA_CYCLE1(LCD2) 00000000
DISPC_DATA_CYCLE2(LCD2) 00000000
DISPC_DATA_CYCLE3(LCD2) 00000000
DISPC_CPR_COEF_R(LCD2) 00000000
DISPC_CPR_COEF_G(LCD2) 00000000
DISPC_CPR_COEF_B(LCD2) 00000000
DISPC_DEFAULT_COLOR(LCD3) 00000000
DISPC_TRANS_COLOR(LCD3) 00000000
DISPC_SIZE_MGR(LCD3) 00000000
DISPC_TIMING_H(LCD3) 00000000
DISPC_TIMING_V(LCD3) 00000000
DISPC_POL_FREQ(LCD3) 00000000
DISPC_DIVISORo(LCD3) 00040001
DISPC_DATA_CYCLE1(LCD3) 00000000
DISPC_DATA_CYCLE2(LCD3) 00000000
DISPC_DATA_CYCLE3(LCD3) 00000000
DISPC_CPR_COEF_R(LCD3) 00000000
DISPC_CPR_COEF_G(LCD3) 00000000
DISPC_CPR_COEF_B(LCD3) 00000000
DISPC_OVL_BA0(GFX) d0003440
DISPC_OVL_BA1(GFX) d0003440
DISPC_OVL_POSITION(GFX) 00000000
DISPC_OVL_SIZE(GFX) 04ff02cf
DISPC_OVL_ATTRIBUTES(GFX) 320040b1
DISPC_OVL_FIFO_THRESHOLD(GFX) 07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(GFX) 00000500
DISPC_OVL_ROW_INC(GFX) 000034c1
DISPC_OVL_PIXEL_INC(GFX) 00000001
DISPC_OVL_PRELOAD(GFX) 000007ff
DISPC_OVL_MFLAG_THRESHOLD(GFX) 05000400
DISPC_OVL_WINDOW_SKIP(GFX) 00000000
DISPC_OVL_TABLE_BA(GFX) 00000000
DISPC_OVL_BA0(VID1) 00000000
DISPC_OVL_BA1(VID1) 00000000
DISPC_OVL_POSITION(VID1) 00000000
DISPC_OVL_SIZE(VID1) 00000000
DISPC_OVL_ATTRIBUTES(VID1) 02808400
DISPC_OVL_FIFO_THRESHOLD(VID1) 07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(VID1) 00000800
DISPC_OVL_ROW_INC(VID1) 00000001
DISPC_OVL_PIXEL_INC(VID1) 00000001
DISPC_OVL_PRELOAD(VID1) 000007ff
DISPC_OVL_MFLAG_THRESHOLD(VID1) 05000400
DISPC_OVL_FIR(VID1) 04000400
DISPC_OVL_PICTURE_SIZE(VID1) 00000000
DISPC_OVL_ACCU0(VID1) 00000000
DISPC_OVL_ACCU1(VID1) 00000000
DISPC_OVL_BA0_UV(VID1) 00000000
DISPC_OVL_BA1_UV(VID1) 00000000
DISPC_OVL_FIR2(VID1) 04000400
DISPC_OVL_ACCU2_0(VID1) 00000000
DISPC_OVL_ACCU2_1(VID1) 00000000
DISPC_OVL_ATTRIBUTES2(VID1) 00000000
DISPC_OVL_BA0(VID2) 00000000
DISPC_OVL_BA1(VID2) 00000000
DISPC_OVL_POSITION(VID2) 00000000
DISPC_OVL_SIZE(VID2) 00000000
DISPC_OVL_ATTRIBUTES(VID2) 02808400
DISPC_OVL_FIFO_THRESHOLD(VID2) 07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(VID2) 00000800
DISPC_OVL_ROW_INC(VID2) 00000001
DISPC_OVL_PIXEL_INC(VID2) 00000001
DISPC_OVL_PRELOAD(VID2) 000007ff
DISPC_OVL_MFLAG_THRESHOLD(VID2) 05000400
DISPC_OVL_FIR(VID2) 04000400
DISPC_OVL_PICTURE_SIZE(VID2) 00000000
DISPC_OVL_ACCU0(VID2) 00000000
DISPC_OVL_ACCU1(VID2) 00000000
DISPC_OVL_BA0_UV(VID2) 00000000
DISPC_OVL_BA1_UV(VID2) 00000000
DISPC_OVL_FIR2(VID2) 04000400
DISPC_OVL_ACCU2_0(VID2) 00000000
DISPC_OVL_ACCU2_1(VID2) 00000000
DISPC_OVL_ATTRIBUTES2(VID2) 00000000
DISPC_OVL_BA0(VID3) 00000000
DISPC_OVL_BA1(VID3) 00000000
DISPC_OVL_POSITION(VID3) 00000000
DISPC_OVL_SIZE(VID3) 00000000
DISPC_OVL_ATTRIBUTES(VID3) 02808400
DISPC_OVL_FIFO_THRESHOLD(VID3) 07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(VID3) 00000800
DISPC_OVL_ROW_INC(VID3) 00000001
DISPC_OVL_PIXEL_INC(VID3) 00000001
DISPC_OVL_PRELOAD(VID3) 000007ff
DISPC_OVL_MFLAG_THRESHOLD(VID3) 05000400
DISPC_OVL_FIR(VID3) 04000400
DISPC_OVL_PICTURE_SIZE(VID3) 00000000
DISPC_OVL_ACCU0(VID3) 00000000
DISPC_OVL_ACCU1(VID3) 00000000
DISPC_OVL_BA0_UV(VID3) 00000000
DISPC_OVL_BA1_UV(VID3) 00000000
DISPC_OVL_FIR2(VID3) 04000400
DISPC_OVL_ACCU2_0(VID3) 00000000
DISPC_OVL_ACCU2_1(VID3) 00000000
DISPC_OVL_ATTRIBUTES2(VID3) 00000000
DISPC_OVL_BA0(WB) 00000000
DISPC_OVL_BA1(WB) 00000000
DISPC_OVL_SIZE(WB) 00000000
DISPC_OVL_ATTRIBUTES(WB) 00808000
DISPC_OVL_FIFO_THRESHOLD(WB) 00080000
DISPC_OVL_FIFO_SIZE_STATUS(WB) 00000800
DISPC_OVL_ROW_INC(WB) 00000001
DISPC_OVL_PIXEL_INC(WB) 00000001
DISPC_OVL_MFLAG_THRESHOLD(WB) 03200280
DISPC_OVL_FIR(WB) 04000400
DISPC_OVL_PICTURE_SIZE(WB) 00000000
DISPC_OVL_ACCU0(WB) 00000000
DISPC_OVL_ACCU1(WB) 00000000
DISPC_OVL_BA0_UV(WB) 00000000
DISPC_OVL_BA1_UV(WB) 00000000
DISPC_OVL_FIR2(WB) 04000400
DISPC_OVL_ACCU2_0(WB) 00000000
DISPC_OVL_ACCU2_1(WB) 00000000
DISPC_OVL_ATTRIBUTES2(WB) 00000000
DISPC_OVL_FIR_COEF_H_0(VID1) 00000000
DISPC_OVL_FIR_COEF_H_1(VID1) 00000000
DISPC_OVL_FIR_COEF_H_2(VID1) 00000000
DISPC_OVL_FIR_COEF_H_3(VID1) 00000000
DISPC_OVL_FIR_COEF_H_4(VID1) 00000000
DISPC_OVL_FIR_COEF_H_5(VID1) 00000000
DISPC_OVL_FIR_COEF_H_6(VID1) 00000000
DISPC_OVL_FIR_COEF_H_7(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_0(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_1(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_2(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_3(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_4(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_5(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_6(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_7(VID1) 00000000
DISPC_OVL_CONV_COEF_0(VID1) 0199012a
DISPC_OVL_CONV_COEF_1(VID1) 012a0000
DISPC_OVL_CONV_COEF_2(VID1) 079c0730
DISPC_OVL_CONV_COEF_3(VID1) 0000012a
DISPC_OVL_CONV_COEF_4(VID1) 00000204
DISPC_OVL_FIR_COEF_V_0(VID1) 00000000
DISPC_OVL_FIR_COEF_V_1(VID1) 00000000
DISPC_OVL_FIR_COEF_V_2(VID1) 00000000
DISPC_OVL_FIR_COEF_V_3(VID1) 00000000
DISPC_OVL_FIR_COEF_V_4(VID1) 00000000
DISPC_OVL_FIR_COEF_V_5(VID1) 00000000
DISPC_OVL_FIR_COEF_V_6(VID1) 00000000
DISPC_OVL_FIR_COEF_V_7(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_0(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_1(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_2(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_3(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_4(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_5(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_6(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_7(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_0(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_1(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_2(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_3(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_4(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_5(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_6(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_7(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_0(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_1(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_2(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_3(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_4(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_5(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_6(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_7(VID1) 00000000
DISPC_OVL_FIR_COEF_H_0(VID2) 00000000
DISPC_OVL_FIR_COEF_H_1(VID2) 00000000
DISPC_OVL_FIR_COEF_H_2(VID2) 00000000
DISPC_OVL_FIR_COEF_H_3(VID2) 00000000
DISPC_OVL_FIR_COEF_H_4(VID2) 00000000
DISPC_OVL_FIR_COEF_H_5(VID2) 00000000
DISPC_OVL_FIR_COEF_H_6(VID2) 00000000
DISPC_OVL_FIR_COEF_H_7(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_0(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_1(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_2(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_3(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_4(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_5(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_6(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_7(VID2) 00000000
DISPC_OVL_CONV_COEF_0(VID2) 0199012a
DISPC_OVL_CONV_COEF_1(VID2) 012a0000
DISPC_OVL_CONV_COEF_2(VID2) 079c0730
DISPC_OVL_CONV_COEF_3(VID2) 0000012a
DISPC_OVL_CONV_COEF_4(VID2) 00000204
DISPC_OVL_FIR_COEF_V_0(VID2) 00000000
DISPC_OVL_FIR_COEF_V_1(VID2) 00000000
DISPC_OVL_FIR_COEF_V_2(VID2) 00000000
DISPC_OVL_FIR_COEF_V_3(VID2) 00000000
DISPC_OVL_FIR_COEF_V_4(VID2) 00000000
DISPC_OVL_FIR_COEF_V_5(VID2) 00000000
DISPC_OVL_FIR_COEF_V_6(VID2) 00000000
DISPC_OVL_FIR_COEF_V_7(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_0(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_1(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_2(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_3(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_4(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_5(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_6(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_7(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_0(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_1(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_2(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_3(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_4(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_5(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_6(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_7(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_0(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_1(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_2(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_3(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_4(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_5(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_6(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_7(VID2) 00000000
DISPC_OVL_FIR_COEF_H_0(VID3) 00000000
DISPC_OVL_FIR_COEF_H_1(VID3) 00000000
DISPC_OVL_FIR_COEF_H_2(VID3) 00000000
DISPC_OVL_FIR_COEF_H_3(VID3) 00000000
DISPC_OVL_FIR_COEF_H_4(VID3) 00000000
DISPC_OVL_FIR_COEF_H_5(VID3) 00000000
DISPC_OVL_FIR_COEF_H_6(VID3) 00000000
DISPC_OVL_FIR_COEF_H_7(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_0(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_1(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_2(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_3(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_4(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_5(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_6(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_7(VID3) 00000000
DISPC_OVL_CONV_COEF_0(VID3) 0199012a
DISPC_OVL_CONV_COEF_1(VID3) 012a0000
DISPC_OVL_CONV_COEF_2(VID3) 079c0730
DISPC_OVL_CONV_COEF_3(VID3) 0000012a
DISPC_OVL_CONV_COEF_4(VID3) 00000204
DISPC_OVL_FIR_COEF_V_0(VID3) 00000000
DISPC_OVL_FIR_COEF_V_1(VID3) 00000000
DISPC_OVL_FIR_COEF_V_2(VID3) 00000000
DISPC_OVL_FIR_COEF_V_3(VID3) 00000000
DISPC_OVL_FIR_COEF_V_4(VID3) 00000000
DISPC_OVL_FIR_COEF_V_5(VID3) 00000000
DISPC_OVL_FIR_COEF_V_6(VID3) 00000000
DISPC_OVL_FIR_COEF_V_7(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_0(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_1(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_2(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_3(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_4(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_5(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_6(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_7(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_0(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_1(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_2(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_3(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_4(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_5(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_6(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_7(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_0(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_1(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_2(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_3(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_4(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_5(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_6(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_7(VID3) 00000000
cat: /sys/kernel/debug/omapdss/dsi1_irqs: No such file or directory
DSI_REVISION 00000040
DSI_SYSCONFIG 00000015
DSI_SYSSTATUS 00000001
DSI_IRQSTATUS 00000000
DSI_IRQENABLE 0015c000
DSI_CTRL 00eaee9f
DSI_COMPLEXIO_CFG1 2a0dcba9
DSI_COMPLEXIO_IRQ_STATUS 00000000
DSI_COMPLEXIO_IRQ_ENABLE 3ff07fff
DSI_CLK_CTRL a030600b
DSI_TIMING1 ffff1000
DSI_TIMING2 ffffffff
DSI_VM_TIMING1 00005076
DSI_VM_TIMING2 043c3232
DSI_VM_TIMING3 029a0500
DSI_CLK_TIMING 00001b10
DSI_TX_FIFO_VC_SIZE 13121110
DSI_RX_FIFO_VC_SIZE 13121110
DSI_COMPLEXIO_CFG2 00030000
DSI_RX_FIFO_VC_FULLNESS 00000000
DSI_VM_TIMING4 00000000
DSI_TX_FIFO_VC_EMPTINESS 1f1f1f1f
DSI_VM_TIMING5 00000000
DSI_VM_TIMING6 01340007
DSI_VM_TIMING7 00100010
DSI_STOPCLK_TIMING 00000080
DSI_VC_CTRL(0) 20808f91
DSI_VC_TE(0) 00000000
DSI_VC_LONG_PACKET_HEADER(0) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(0) 00000000
DSI_VC_SHORT_PACKET_HEADER(0) 00000000
DSI_VC_IRQSTATUS(0) 00000004
DSI_VC_IRQENABLE(0) 000000db
DSI_VC_CTRL(1) 20808d81
DSI_VC_TE(1) 00000000
DSI_VC_LONG_PACKET_HEADER(1) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(1) 00000000
DSI_VC_SHORT_PACKET_HEADER(1) 00000000
DSI_VC_IRQSTATUS(1) 00000004
DSI_VC_IRQENABLE(1) 000000db
DSI_VC_CTRL(2) 20808d81
DSI_VC_TE(2) 00000000
DSI_VC_LONG_PACKET_HEADER(2) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(2) 00000000
DSI_VC_SHORT_PACKET_HEADER(2) 00000000
DSI_VC_IRQSTATUS(2) 00000000
DSI_VC_IRQENABLE(2) 000000db
DSI_VC_CTRL(3) 20808d81
DSI_VC_TE(3) 00000000
DSI_VC_LONG_PACKET_HEADER(3) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(3) 00000000
DSI_VC_SHORT_PACKET_HEADER(3) 00000000
DSI_VC_IRQSTATUS(3) 00000000
DSI_VC_IRQENABLE(3) 000000db
DSI_DSIPHY_CFG0 132b1322
DSI_DSIPHY_CFG1 42c6103c
DSI_DSIPHY_CFG2 b800000f
DSI_DSIPHY_CFG5 ff000000
DSI_PLL_CONTROL 00000018
DSI_PLL_STATUS 00006383
DSI_PLL_GO 00000000
DSI_PLL_CONFIGURATION1 10a03000
DSI_PLL_CONFIGURATION2 00656004
root@letux:~#
[-- Attachment #4: Type: text/plain, Size: 2 bytes --]
prev parent reply other threads:[~2020-11-16 9:54 UTC|newest]
Thread overview: 164+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-05 12:02 [PATCH v3 00/56] Convert DSI code to use drm_mipi_dsi and drm_panel Tomi Valkeinen
2020-11-05 12:02 ` [PATCH v3 01/56] drm/dsi: add MIPI_DSI_MODE_ULPS_IDLE Tomi Valkeinen
2020-11-06 4:41 ` Laurent Pinchart
2020-11-05 12:02 ` [PATCH v3 02/56] Revert "drm/omap: dss: Remove unused omap_dss_device operations" Tomi Valkeinen
2020-11-05 21:27 ` Sam Ravnborg
2020-11-06 4:50 ` Laurent Pinchart
2020-11-05 12:02 ` [PATCH v3 03/56] drm/omap: drop unused dsi.configure_pins Tomi Valkeinen
2020-11-06 4:50 ` Laurent Pinchart
2020-11-05 12:02 ` [PATCH v3 04/56] drm/omap: dsi: use MIPI_DSI_FMT_* instead of OMAP_DSS_DSI_FMT_* Tomi Valkeinen
2020-11-06 4:56 ` Laurent Pinchart
2020-11-05 12:02 ` [PATCH v3 05/56] drm/omap: constify write buffers Tomi Valkeinen
2020-11-06 4:57 ` Laurent Pinchart
2020-11-05 12:02 ` [PATCH v3 06/56] drm/omap: dsi: add generic transfer function Tomi Valkeinen
2020-11-06 5:05 ` Laurent Pinchart
2020-11-05 12:02 ` [PATCH v3 07/56] drm/omap: panel-dsi-cm: convert to transfer API Tomi Valkeinen
2020-11-06 5:08 ` Laurent Pinchart
2020-11-05 12:02 ` [PATCH v3 08/56] drm/omap: dsi: unexport specific data transfer functions Tomi Valkeinen
2020-11-09 8:10 ` Laurent Pinchart
2020-11-05 12:02 ` [PATCH v3 09/56] drm/omap: dsi: drop virtual channel logic Tomi Valkeinen
2020-11-09 8:14 ` Laurent Pinchart
2020-11-09 8:20 ` Tomi Valkeinen
2020-11-09 8:18 ` Tomi Valkeinen
2020-11-05 12:02 ` [PATCH v3 10/56] drm/omap: dsi: simplify write function Tomi Valkeinen
2020-11-09 8:21 ` Laurent Pinchart
2020-11-05 12:02 ` [PATCH v3 11/56] drm/omap: dsi: simplify read functions Tomi Valkeinen
2020-11-09 8:28 ` Laurent Pinchart
2020-11-05 12:02 ` [PATCH v3 12/56] drm/omap: dsi: switch dsi_vc_send_long/short to mipi_dsi_msg Tomi Valkeinen
2020-11-09 8:33 ` Laurent Pinchart
2020-11-05 12:02 ` [PATCH v3 13/56] drm/omap: dsi: introduce mipi_dsi_host Tomi Valkeinen
2020-11-09 8:38 ` Laurent Pinchart
2020-11-05 12:02 ` [PATCH v3 14/56] drm/omap: panel-dsi-cm: use DSI helpers Tomi Valkeinen
2020-11-09 8:40 ` Laurent Pinchart
2020-11-05 12:02 ` [PATCH v3 15/56] drm/omap: dsi: request VC via mipi_dsi_attach Tomi Valkeinen
2020-11-09 8:42 ` Laurent Pinchart
2020-11-09 11:16 ` Tomi Valkeinen
2020-11-05 12:02 ` [PATCH v3 16/56] drm/omap: panel-dsi-cm: drop hardcoded VC Tomi Valkeinen
2020-11-09 8:43 ` Laurent Pinchart
2020-11-05 12:02 ` [PATCH v3 17/56] drm/omap: panel-dsi-cm: use common MIPI DCS 1.3 defines Tomi Valkeinen
2020-11-09 8:44 ` Laurent Pinchart
2020-11-05 12:02 ` [PATCH v3 18/56] drm/omap: dsi: drop unused memory_read() Tomi Valkeinen
2020-11-09 8:45 ` Laurent Pinchart
2020-11-05 12:02 ` [PATCH v3 19/56] drm/omap: dsi: drop unused get_te() Tomi Valkeinen
2020-11-09 8:45 ` Laurent Pinchart
2020-11-09 9:49 ` Tomi Valkeinen
2020-11-05 12:02 ` [PATCH v3 20/56] drm/omap: dsi: drop unused enable_te() Tomi Valkeinen
2020-11-09 8:46 ` Laurent Pinchart
2020-11-05 12:02 ` [PATCH v3 21/56] drm/omap: dsi: drop useless sync() Tomi Valkeinen
2020-11-09 8:46 ` Laurent Pinchart
2020-11-05 12:02 ` [PATCH v3 22/56] drm/omap: dsi: use pixel-format and mode from attach Tomi Valkeinen
2020-11-09 8:49 ` Laurent Pinchart
2020-11-09 9:45 ` Tomi Valkeinen
2020-11-05 12:03 ` [PATCH v3 23/56] drm/omap: panel-dsi-cm: use bulk regulator API Tomi Valkeinen
2020-11-09 8:51 ` Laurent Pinchart
2020-11-05 12:03 ` [PATCH v3 24/56] drm/omap: dsi: lp/hs switching support for transfer() Tomi Valkeinen
2020-11-09 8:53 ` Laurent Pinchart
2020-11-05 12:03 ` [PATCH v3 25/56] drm/omap: dsi: move TE GPIO handling into core Tomi Valkeinen
2020-11-09 9:19 ` Laurent Pinchart
2020-11-11 13:26 ` Tomi Valkeinen
2020-11-05 12:03 ` [PATCH v3 26/56] drm/omap: dsi: drop custom enable_te() API Tomi Valkeinen
2020-11-09 9:32 ` Laurent Pinchart
2020-11-05 12:03 ` [PATCH v3 27/56] drm/omap: dsi: do bus locking in host driver Tomi Valkeinen
2020-11-09 9:52 ` Laurent Pinchart
2020-11-09 10:08 ` Tomi Valkeinen
2020-11-09 13:27 ` Sebastian Reichel
2020-11-09 14:25 ` Tomi Valkeinen
2020-11-11 13:35 ` Tomi Valkeinen
2020-11-05 12:03 ` [PATCH v3 28/56] drm/omap: dsi: untangle ulps ops from enable/disable Tomi Valkeinen
2020-11-09 9:57 ` Laurent Pinchart
2020-11-11 14:05 ` Tomi Valkeinen
2020-11-05 12:03 ` [PATCH v3 29/56] drm/omap: dsi: do ULPS in host driver Tomi Valkeinen
2020-11-09 10:03 ` Laurent Pinchart
2020-11-11 15:29 ` Tomi Valkeinen
2020-11-05 12:03 ` [PATCH v3 30/56] drm/omap: dsi: move panel refresh function to host Tomi Valkeinen
2020-11-09 10:10 ` Laurent Pinchart
2020-11-11 15:34 ` Tomi Valkeinen
2020-11-11 15:58 ` Laurent Pinchart
2020-11-12 8:08 ` Tomi Valkeinen
2020-11-16 9:22 ` Laurent Pinchart
2020-11-17 10:04 ` Sebastian Reichel
2020-11-05 12:03 ` [PATCH v3 31/56] drm/omap: dsi: Reverse direction of the DSS device enable/disable operations Tomi Valkeinen
2020-11-09 10:17 ` Laurent Pinchart
2020-11-05 12:03 ` [PATCH v3 32/56] drm/omap: dsi: drop custom panel capability support Tomi Valkeinen
2020-11-09 10:20 ` Laurent Pinchart
2020-11-05 12:03 ` [PATCH v3 33/56] drm/omap: dsi: convert to drm_panel Tomi Valkeinen
2020-11-09 10:39 ` Laurent Pinchart
2020-11-11 15:54 ` Tomi Valkeinen
2020-11-05 12:03 ` [PATCH v3 34/56] drm/omap: drop omapdss-boot-init Tomi Valkeinen
2020-11-09 10:40 ` Laurent Pinchart
2020-11-05 12:03 ` [PATCH v3 35/56] drm/omap: dsi: implement check timings Tomi Valkeinen
2020-11-09 10:47 ` Laurent Pinchart
2020-11-11 12:36 ` Tomi Valkeinen
2020-11-05 12:03 ` [PATCH v3 36/56] drm/omap: panel-dsi-cm: use DEVICE_ATTR_RO Tomi Valkeinen
2020-11-09 10:48 ` Laurent Pinchart
2020-11-05 12:03 ` [PATCH v3 37/56] drm/omap: panel-dsi-cm: support unbinding Tomi Valkeinen
2020-11-09 10:49 ` Laurent Pinchart
2020-11-11 12:03 ` Tomi Valkeinen
2020-11-05 12:03 ` [PATCH v3 38/56] drm/omap: panel-dsi-cm: fix remove() Tomi Valkeinen
2020-11-09 10:50 ` Laurent Pinchart
2020-11-05 12:03 ` [PATCH v3 39/56] drm/omap: remove global dss_device variable Tomi Valkeinen
2020-11-09 10:51 ` Laurent Pinchart
2020-11-05 12:03 ` [PATCH v3 40/56] drm/panel: Move OMAP's DSI command mode panel driver Tomi Valkeinen
2020-11-05 15:16 ` Sam Ravnborg
2020-11-05 15:27 ` Tomi Valkeinen
2020-11-09 10:53 ` Laurent Pinchart
2020-11-05 12:03 ` [PATCH v3 41/56] drm/omap: dsi: Register a drm_bridge Tomi Valkeinen
2020-11-09 10:54 ` Laurent Pinchart
2020-11-05 12:03 ` [PATCH v3 42/56] drm/omap: remove legacy DSS device operations Tomi Valkeinen
2020-11-09 11:01 ` Laurent Pinchart
2020-11-05 12:03 ` [PATCH v3 43/56] drm/omap: remove unused omap_connector Tomi Valkeinen
2020-11-09 11:02 ` Laurent Pinchart
2020-11-05 12:03 ` [PATCH v3 44/56] drm/omap: simplify omap_display_id Tomi Valkeinen
2020-11-09 11:03 ` Laurent Pinchart
2020-11-05 12:03 ` [PATCH v3 45/56] drm/omap: drop unused DSS next pointer Tomi Valkeinen
2020-11-09 11:04 ` Laurent Pinchart
2020-11-05 12:03 ` [PATCH v3 46/56] drm/omap: drop empty omap_encoder helper functions Tomi Valkeinen
2020-11-09 11:05 ` Laurent Pinchart
2020-11-05 12:03 ` [PATCH v3 47/56] drm/omap: drop DSS ops_flags Tomi Valkeinen
2020-11-09 11:05 ` Laurent Pinchart
2020-11-05 12:03 ` [PATCH v3 48/56] drm/omap: drop dssdev display field Tomi Valkeinen
2020-11-09 11:06 ` Laurent Pinchart
2020-11-05 12:03 ` [PATCH v3 49/56] drm/omap: simplify DSI manual update code Tomi Valkeinen
2020-11-09 11:07 ` Laurent Pinchart
2020-11-05 12:03 ` [PATCH v3 50/56] drm/omap: dsi: simplify pin config Tomi Valkeinen
2020-11-09 11:09 ` Laurent Pinchart
2020-11-11 12:24 ` Tomi Valkeinen
2020-11-05 12:03 ` [PATCH v3 51/56] ARM: omap2plus_defconfig: Update for moved DSI command mode panel Tomi Valkeinen
2020-11-09 11:10 ` Laurent Pinchart
2020-11-05 12:03 ` [PATCH v3 52/56] drm/omap: squash omapdrm sub-modules into one Tomi Valkeinen
2020-11-09 11:15 ` Laurent Pinchart
2020-11-05 12:03 ` [PATCH v3 53/56] drm/omap: remove unused display.c Tomi Valkeinen
2020-11-09 11:16 ` Laurent Pinchart
2020-11-05 12:03 ` [PATCH v3 54/56] drm/omap: drop unused owner field Tomi Valkeinen
2020-11-09 11:16 ` Laurent Pinchart
2020-11-05 12:03 ` [PATCH v3 55/56] drm/omap: remove dispc_ops Tomi Valkeinen
2020-11-09 11:17 ` Laurent Pinchart
2020-11-05 12:03 ` [PATCH v3 56/56] drm/omap: remove dss_mgr_ops Tomi Valkeinen
2020-11-09 11:18 ` Laurent Pinchart
2020-11-05 17:15 ` [PATCH v3 00/56] Convert DSI code to use drm_mipi_dsi and drm_panel H. Nikolaus Schaller
2020-11-05 17:36 ` Tomi Valkeinen
2020-11-05 18:14 ` H. Nikolaus Schaller
2020-11-05 18:28 ` Tomi Valkeinen
2020-11-05 18:56 ` H. Nikolaus Schaller
2020-11-06 14:37 ` Tomi Valkeinen
2020-11-06 15:04 ` Tomi Valkeinen
2020-11-07 12:19 ` H. Nikolaus Schaller
2020-11-09 8:04 ` Tomi Valkeinen
2020-11-09 9:30 ` H. Nikolaus Schaller
2020-11-09 10:22 ` Tomi Valkeinen
2020-11-09 10:31 ` H. Nikolaus Schaller
2020-11-09 10:34 ` Tomi Valkeinen
2020-11-09 11:09 ` H. Nikolaus Schaller
2020-11-09 11:33 ` Tomi Valkeinen
2020-11-10 13:49 ` H. Nikolaus Schaller
2020-11-10 15:25 ` Tomi Valkeinen
2020-11-10 16:49 ` H. Nikolaus Schaller
2020-11-10 16:52 ` Tomi Valkeinen
2020-11-10 21:04 ` H. Nikolaus Schaller
2020-11-11 6:40 ` Tomi Valkeinen
2020-11-11 7:48 ` H. Nikolaus Schaller
2020-11-11 10:11 ` Tomi Valkeinen
2020-11-11 19:27 ` H. Nikolaus Schaller
2020-11-05 21:31 ` Sam Ravnborg
2020-11-08 16:33 ` Nikhil Devshatwar
[not found] ` <BAFBC885-9BBE-46D1-B4C4-79910705864A@goldelico.com>
[not found] ` <74abbdc4-cc1e-9caf-d4ee-0a5cdb557643@ti.com>
[not found] ` <b0677958-02ad-1d2f-d755-! 25a9d384eddc@ti.com>
[not found] ` <1A09B4DA-F726-4F37-8CF4-BC192C659950@goldelico.com>
[not found] ` <9a4e373e-9092-6d82-937a-bc663d2376b4@ti.com>
[not found] ` <09ebc3e3-72c7-41fb-fb21-bf28c! f883d3f@ti.com>
[not found] ` <E738362A-8ECE-4ED5-8057-2ABB6F5C3056@goldelico.com>
[not found] ` <9a21b475-eff0-9882-8d65-d1f! dd2139dc4@ti.com>
[not found] ` <A1DEB54D-FEC0-493A-858C-E5C0DB24B35E@goldelico.com>
[not found] ` <1150ba22-1ae2-39f3-0924-7! a1f1b468597@ti.com>
[not found] ` <2999ED77-B9F7-4197-81B8-F1AFF329A1E9@goldelico.com>
[not found] ` <cbc147d2-af41-2bed-5670-530d45cfb24e@ti.com>
[not found] ` <106bfbee-c472-c04c-0f7b-db108a090a63@ti.com>
[not found] ` <420b81bd-fc95-e294-fcbe-f34db1ef! f9e7@ti.c om>
[not found] ` <B2FBCAE4-FAD9-4C0D-9C75-63A701215886@goldelico.com>
[not found] ` <826B2E97-8B77-412A-8093-753BF7A65EE1@goldelico.com>
[not found] ` <acad2006-53a2-6587-b8e6-787e358! 8932a@ti.com>
[not found] ` <AF87C7B4-DCD2-4207-A300-567DB65B08ED@goldelico.com>
[not found] ` <27cfb13a-62e3-0a53-153f-92641c437cee@ti. com>
[not found] ` <27cfb13a-62e3-0a53-153f-92641c437cee@ti.com>
2020-11-16 9:16 ` H. Nikolaus Schaller [this message]
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