From: "Jingoo Han" <jingoohan1@gmail.com>
To: "'Gustavo Pimentel'" <gustavo.pimentel@synopsys.com>,
<bhelgaas@google.com>, <lorenzo.pieralisi@arm.com>,
<Joao.Pinto@synopsys.com>, <kishon@ti.com>, <robh+dt@kernel.org>,
<mark.rutland@arm.com>
Cc: <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>
Subject: Re: [PATCH v7 6/9] PCI: dwc: Define maximum number of vectors
Date: Tue, 24 Apr 2018 10:39:20 -0400 [thread overview]
Message-ID: <000001d3dbda$0a135930$1e3a0b90$@gmail.com> (raw)
In-Reply-To: <6b2c7ec1835cf422af5703aa14c99dbad8c6ffb8.1524577064.git.gustavo.pimentel@synopsys.com>
On Tuesday, April 24, 2018 9:45 AM, Gustavo Pimentel wrote:
>
> Adds a callback that defines the maximum number of vectors that can be use
> by the Root Complex.
>
> Since this is a parameter associated to each SoC IP setting, makes sense
> to
> be configurable and easily visible to future modifications.
>
> The designware IP supports a maximum of 256 vectors.
>
> Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> Acked-by: Joao Pinto <jpinto@synopsys.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Best regards,
Jingoo Han
> ---
> Change v1->v2:
> - Nothing changed, just to follow the patch set version.
> Change v2->v3:
> - Nothing changed, just to follow the patch set version.
> Changes v3->v4:
> - Nothing changed, just to follow the patch set version.
> Changes v4->v5:
> - Nothing changed, just to follow the patch set version.
> Changes v5->v6:
> - Nothing changed, just to follow the patch set version.
> Changes v6->v7:
> - Nothing changed, just to follow the patch set version.
>
> drivers/pci/dwc/pcie-designware-plat.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/pci/dwc/pcie-designware-plat.c
> b/drivers/pci/dwc/pcie-designware-plat.c
> index efc315c..5937fed 100644
> --- a/drivers/pci/dwc/pcie-designware-plat.c
> +++ b/drivers/pci/dwc/pcie-designware-plat.c
> @@ -48,8 +48,14 @@ static int dw_plat_pcie_host_init(struct pcie_port *pp)
> return 0;
> }
>
> +static void dw_plat_set_num_vectors(struct pcie_port *pp)
> +{
> + pp->num_vectors = MAX_MSI_IRQS;
> +}
> +
> static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = {
> .host_init = dw_plat_pcie_host_init,
> + .set_num_vectors = dw_plat_set_num_vectors,
> };
>
> static int dw_plat_pcie_establish_link(struct dw_pcie *pci)
> --
> 2.7.4
>
next prev parent reply other threads:[~2018-04-24 14:39 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-24 13:44 [PATCH v7 0/9] Designware EP support and code clean up Gustavo Pimentel
2018-04-24 13:44 ` [PATCH v7 1/9] bindings: PCI: designware: Example update Gustavo Pimentel
2018-04-24 13:44 ` [PATCH v7 2/9] PCI: dwc: Add support for endpoint mode Gustavo Pimentel
2018-04-24 13:44 ` [PATCH v7 3/9] PCI: endpoint: functions/pci-epf-test: Add second entry Gustavo Pimentel
2018-04-26 16:56 ` Lorenzo Pieralisi
2018-04-30 17:32 ` Gustavo Pimentel
2018-05-01 10:07 ` Kishon Vijay Abraham I
2018-05-01 11:54 ` Lorenzo Pieralisi
2018-05-01 12:23 ` Kishon Vijay Abraham I
2018-05-01 14:26 ` Lorenzo Pieralisi
2018-05-02 10:39 ` Gustavo Pimentel
2018-05-02 16:51 ` Lorenzo Pieralisi
2018-05-03 6:33 ` Kishon Vijay Abraham I
2018-05-03 14:16 ` Lorenzo Pieralisi
2018-05-04 5:58 ` Kishon Vijay Abraham I
2018-05-04 11:18 ` Lorenzo Pieralisi
2018-05-03 15:21 ` Gustavo Pimentel
2018-04-24 13:44 ` [PATCH v7 4/9] bindings: PCI: designware: Add support for the EP in Designware driver Gustavo Pimentel
2018-04-24 13:44 ` [PATCH v7 5/9] misc: pci_endpoint_test: Add designware EP entry Gustavo Pimentel
2018-04-24 13:44 ` [PATCH v7 6/9] PCI: dwc: Define maximum number of vectors Gustavo Pimentel
2018-04-24 14:39 ` Jingoo Han [this message]
2018-04-24 13:44 ` [PATCH v7 7/9] PCI: dwc: Replace lower into upper case characters Gustavo Pimentel
2018-04-24 13:44 ` [PATCH v7 8/9] PCI: dwc: Small computation improvement Gustavo Pimentel
2018-04-24 13:44 ` [PATCH v7 9/9] PCI: dwc: Replace magic number by defines Gustavo Pimentel
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