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From: Marek Vasut <>
To: Lorenzo Pieralisi <>,
	Bjorn Helgaas <>
Cc:, Bjorn Helgaas <>,
	Geert Uytterhoeven <>,
	Wolfram Sang <>,
	Yoshihiro Shimoda <>,
Subject: Re: [PATCH] PCI: rcar: Add L1 link state fix into data abort hook
Date: Sun, 29 Nov 2020 14:02:42 +0100	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <>

On 11/19/20 5:25 PM, Lorenzo Pieralisi wrote:
>>> The R-Car PCIe controller is capable of handling L0s/L1 link states.
>>> While the controller can enter and exit L0s link state, and exit L1
>>> link state, without any additional action from the driver, to enter
>>> L1 link state, the driver must complete the link state transition by
>>> issuing additional commands to the controller.
>> So IIUC an R-Car Root Port can't enter L1 without help from the
>> driver?  That *sounds* like a hardware defect, since ASPM is supposed
>> to be "hardware-autonomous" once configured.
> Sorry for the late feedback, starting to queue patches for v5.11.

Same here.

> Is this issue ASPM related (ie is it supported by the host controller) ?
> *Or* it is related to kernel driven device D-{1,2,3} L1 entry ?
> I am asking because if it is only related to D-{1,2,3} device state
> entry we could intercept the PMCSR write and move the quirk in config
> space accessors.

I don't think you can always intercept the entry into L1 state (e.g. if 
userspace triggers it), but you should be able to recover from such a 
state (this controller does permit you to do so), so I would say this is 
a third option.

  reply	other threads:[~2020-11-29 13:06 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-12 21:18 marek.vasut
2020-09-13 17:22 ` Bjorn Helgaas
2020-09-14  1:36   ` Marek Vasut
2020-09-14  4:01     ` Bjorn Helgaas
2020-09-16 13:50       ` Marek Vasut
2020-11-19 16:25   ` Lorenzo Pieralisi
2020-11-29 13:02     ` Marek Vasut [this message]
2020-09-14  9:29 ` Geert Uytterhoeven
2020-09-14 10:11   ` Geert Uytterhoeven

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