[PATCH 0/2] x86: intel-mid-pci: fix to get eMMC detected

[PATCH 0/2] x86: intel-mid-pci: fix to get eMMC detected

[Andy Shevchenko]

On Intel Edison we have a nice implementation of x86 platform without legacy
PIC and with specific PCI. There are devices which are not using interrupt by
some reasons, but have them as IRQ0 in the PCI configuration. Suprisingly the
first eMMC host controller is the actual user for IRQ0. Since we have serial
driver implemented that enumerates unused serial IP (one of four) which has
IRQ0 assigned we, in case it gets it first by pci_enable_device(), lost a
possibility to probe eMMC. 

So, this series provides a workaround (patch 2) and small fix of error code
(patch 1).

I wonder if this can go to v4.2. What do you think?

Andy Shevchenko (2):
  x86: intel_mid_pci: propagate actual return code
  x86: intel_mid_pci: work around for IRQ0 assignment

 arch/x86/pci/intel_mid_pci.c | 27 ++++++++++++++++++++++++---
 1 file changed, 24 insertions(+), 3 deletions(-)

-- 
2.1.4

[PATCH 1/2] x86: intel_mid_pci: propagate actual return code

[Andy Shevchenko]

mp_map_gsi_to_irq() returns different codes if it fails.
intel_mid_pci_irq_enable() hides this under -EBUSY. The patch replaces it by
what is actually returned.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 arch/x86/pci/intel_mid_pci.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c
index 2706230..0af2e78 100644
--- a/arch/x86/pci/intel_mid_pci.c
+++ b/arch/x86/pci/intel_mid_pci.c
@@ -210,10 +210,12 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
 {
 	struct irq_alloc_info info;
 	int polarity;
+	int ret;
 
 	if (dev->irq_managed && dev->irq > 0)
 		return 0;
 
+	/* Set IRQ polarity */
 	if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)
 		polarity = 0; /* active high */
 	else
@@ -224,8 +226,9 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
 	 * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
 	 * IOAPIC RTE entries, so we just enable RTE for the device.
 	 */
-	if (mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info) < 0)
-		return -EBUSY;
+	ret = mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info);
+	if (ret < 0)
+		return ret;
 
 	dev->irq_managed = 1;
 
-- 
2.1.4

[PATCH 2/2] x86: intel_mid_pci: work around for IRQ0 assignment

[Andy Shevchenko]

A few devices on Intel Edison board (Intel Tangier) has IRQ0 as an IRQ line in
the PCI configuration. The actual one which is using that is a first eMMC host
controller.

In case we compile sdhci-pci as a module and leave serial driver built-in,
first serial device not in use and has IRQ0 assigned as well, the latter takes
the interrupt allocation. The result of such behaviour is impossibility to
allocate the interrupt by sdhci-pci driver.

This patch introduces a quirk inside intel_mid_pci_irq_enable() to avoid
described behaviour.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 arch/x86/pci/intel_mid_pci.c | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c
index 0af2e78..66e215d 100644
--- a/arch/x86/pci/intel_mid_pci.c
+++ b/arch/x86/pci/intel_mid_pci.c
@@ -206,15 +206,33 @@ static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
 			       where, size, value);
 }
 
+#define PCI_DEVICE_ID_INTEL_MRFL_MMC	0x1190
+
 static int intel_mid_pci_irq_enable(struct pci_dev *dev)
 {
 	struct irq_alloc_info info;
 	int polarity;
 	int ret;
 
-	if (dev->irq_managed && dev->irq > 0)
+	if (dev->irq_managed && dev->irq >= 0)
 		return 0;
 
+	/* Special treatment for IRQ0 */
+	if (dev->irq == 0) {
+		switch (intel_mid_identify_cpu()) {
+		case INTEL_MID_CPU_CHIP_TANGIER:
+			/*
+			 * TNG has IRQ0 assigned to eMMC controller. This makes
+			 * it happy to get an interrupt.
+			 */
+			if (dev->device != PCI_DEVICE_ID_INTEL_MRFL_MMC)
+				return -EBUSY;
+			break;
+		default:
+			break;
+		}
+	}
+
 	/* Set IRQ polarity */
 	if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)
 		polarity = 0; /* active high */
-- 
2.1.4

Re: [PATCH 0/2] x86: intel-mid-pci: fix to get eMMC detected

[Andy Shevchenko]

On Wed, 2015-06-17 at 22:03 +0300, Andy Shevchenko wrote:
> On Intel Edison we have a nice implementation of x86 platform without 
> legacy
> PIC and with specific PCI. There are devices which are not using 
> interrupt by
> some reasons, but have them as IRQ0 in the PCI configuration. 
> Suprisingly the
> first eMMC host controller is the actual user for IRQ0. Since we have 
> serial
> driver implemented that enumerates unused serial IP (one of four) 
> which has
> IRQ0 assigned we, in case it gets it first by pci_enable_device(), 
> lost a
> possibility to probe eMMC. 

Any comments on that?

> 
> So, this series provides a workaround (patch 2) and small fix of 
> error code
> (patch 1).
> 
> I wonder if this can go to v4.2. What do you think?
> 
> Andy Shevchenko (2):
>   x86: intel_mid_pci: propagate actual return code
>   x86: intel_mid_pci: work around for IRQ0 assignment
> 
>  arch/x86/pci/intel_mid_pci.c | 27 ++++++++++++++++++++++++---
>  1 file changed, 24 insertions(+), 3 deletions(-)
> 

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy