From: Trent Piepho <tpiepho@impinj.com>
To: "marc.zyngier@arm.com" <marc.zyngier@arm.com>
Cc: "jingoohan1@gmail.com" <jingoohan1@gmail.com>,
"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
"gustavo.pimentel@synopsys.com" <gustavo.pimentel@synopsys.com>,
"faiz_abbas@ti.com" <faiz_abbas@ti.com>,
"Joao.Pinto@synopsys.com" <Joao.Pinto@synopsys.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"helgaas@google.com" <helgaas@google.com>,
"vigneshr@ti.com" <vigneshr@ti.com>
Subject: Re: [PATCH 0/3] PCI: designware: Fixing MSI handling flow
Date: Wed, 14 Nov 2018 22:50:09 +0000 [thread overview]
Message-ID: <1542235808.30311.504.camel@impinj.com> (raw)
In-Reply-To: <86r2fn48jt.wl-marc.zyngier@arm.com>
On Wed, 2018-11-14 at 22:07 +0000, Marc Zyngier wrote:
> On Wed, 14 Nov 2018 18:28:05 +0000,
> Trent Piepho <tpiepho@impinj.com> wrote:
> >
> >
> > The new domain stuff does not appear to integrate into the existing irq
> > framework perfectly. My interrupt has changed from MSI #1 to MSI
> > #524288. Not the most user friendly number.
>
> It is not supposed to be user friendly. It is not even supposed to be
> interpreted by anyone. And if you print it in hex, you'll find that it
> *is* actually useful.
The GPCv2 values match those in the datasheet. This is very handy!
domain: :soc:aips-bus@30800000:pcie@33800000-3
hwirq: 0x80000
chip: PCI-MSI
flags: 0x20
IRQCHIP_ONESHOT_SAFE
parent:
domain: :soc:aips-bus@30800000:pcie@33800000
hwirq: 0x1
chip: DWPCI-MSI
flags: 0x0
It's not clear to me what these two domains are for. Perhaps if I had
multiple busses or multiple ports it would be. I'm assuming the offset
is based on 2048 MSI-Xs per function, 8 functions per device, and 32
devices per bus. So perhaps this means this is MSI 0 on bus 1 of the
controller.
next prev parent reply other threads:[~2018-11-14 22:50 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-13 22:57 [PATCH 0/3] PCI: designware: Fixing MSI handling flow Marc Zyngier
2018-11-13 22:57 ` [PATCH 1/3] PCI: designware: Use interrupt masking instead of disabling Marc Zyngier
2018-12-03 18:02 ` [1/3] " Niklas Cassel
2018-12-04 9:41 ` [PATCH 1/3] " Gustavo Pimentel
2018-11-13 22:57 ` [PATCH 2/3] PCI: designware: Take lock when ACKing an interrupt Marc Zyngier
2018-11-14 19:08 ` Trent Piepho
2018-12-03 18:02 ` [2/3] " Niklas Cassel
2018-12-04 9:41 ` [PATCH 2/3] " Gustavo Pimentel
2018-11-13 22:57 ` [PATCH 3/3] PCI: designware: Move interrupt acking into the proper callback Marc Zyngier
2018-11-14 19:01 ` Trent Piepho
2018-12-03 18:02 ` [3/3] " Niklas Cassel
2018-12-04 9:41 ` [PATCH 3/3] " Gustavo Pimentel
2018-12-04 10:20 ` Kishon Vijay Abraham I
2018-12-04 13:45 ` Marc Zyngier
2018-12-07 8:12 ` Kishon Vijay Abraham I
2018-12-07 9:45 ` Marc Zyngier
2018-12-07 10:13 ` Kishon Vijay Abraham I
2018-12-11 12:35 ` Lorenzo Pieralisi
2018-12-12 5:54 ` Kishon Vijay Abraham I
2018-11-13 23:16 ` [PATCH 0/3] PCI: designware: Fixing MSI handling flow Gustavo Pimentel
2018-11-14 9:54 ` Marc Zyngier
2018-11-14 19:19 ` Trent Piepho
2018-11-14 22:01 ` Marc Zyngier
2018-11-14 22:25 ` Trent Piepho
2018-11-14 22:44 ` Marc Zyngier
2018-11-14 23:23 ` Trent Piepho
2018-11-19 20:37 ` Trent Piepho
2018-11-22 12:03 ` Gustavo Pimentel
2018-11-22 16:07 ` Gustavo Pimentel
2018-11-22 16:26 ` Lorenzo Pieralisi
2018-11-22 16:38 ` Marc Zyngier
2018-11-22 17:40 ` Gustavo Pimentel
2018-11-26 16:06 ` Trent Piepho
2018-11-27 7:51 ` Marc Zyngier
2018-11-27 17:23 ` Trent Piepho
2018-11-22 17:49 ` Gustavo Pimentel
2018-11-26 15:52 ` Trent Piepho
2018-11-27 7:50 ` Marc Zyngier
2018-11-27 18:12 ` Trent Piepho
2018-12-07 16:16 ` Gustavo Pimentel
2018-11-14 18:28 ` Trent Piepho
2018-11-14 22:07 ` Marc Zyngier
2018-11-14 22:50 ` Trent Piepho [this message]
2018-11-15 15:22 ` Gustavo Pimentel
2018-11-15 18:37 ` Trent Piepho
2018-11-15 19:29 ` Marc Zyngier
2018-11-19 20:14 ` Trent Piepho
2018-11-21 17:24 ` Stanimir Varbanov
2018-12-01 23:50 ` Niklas Cassel
2018-12-02 11:28 ` Stanimir Varbanov
2018-12-03 10:42 ` Lorenzo Pieralisi
2018-12-03 13:09 ` Niklas Cassel
2018-12-03 17:42 ` Lorenzo Pieralisi
2018-12-03 20:31 ` Trent Piepho
2018-12-10 16:17 ` Lorenzo Pieralisi
2018-12-10 16:30 ` Marc Zyngier
2018-12-10 18:15 ` Trent Piepho
2018-12-10 18:31 ` Marc Zyngier
2018-12-10 20:34 ` Trent Piepho
2018-12-12 9:10 ` Gustavo Pimentel
2018-12-12 8:55 ` Gustavo Pimentel
2018-12-11 11:43 ` Lorenzo Pieralisi
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