From: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
To: Marc Zyngier <marc.zyngier@arm.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <helgaas@google.com>
Cc: Trent Piepho <tpiepho@impinj.com>,
Jingoo Han <jingoohan1@gmail.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
"faiz_abbas@ti.com" <faiz_abbas@ti.com>,
Joao Pinto <Joao.Pinto@synopsys.com>, Vignesh R <vigneshr@ti.com>
Subject: Re: [PATCH 1/3] PCI: designware: Use interrupt masking instead of disabling
Date: Tue, 4 Dec 2018 09:41:01 +0000 [thread overview]
Message-ID: <97c5b213-3280-1049-7c2f-2306b4b9e454@synopsys.com> (raw)
In-Reply-To: <20181113225734.8026-2-marc.zyngier@arm.com>
Hi,
On 13/11/2018 22:57, Marc Zyngier wrote:
> The dwc driver is showing an interesting level of brokeness, as it
> insists on using the "enable" register to mask/unmask MSIs, meaning
> that an MSIs being generated while the interrupt is in that "disabled"
> state will simply be lost.
>
> Let's move to the MASK register, which offers the expected semantics.
>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
> drivers/pci/controller/dwc/pcie-designware-host.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 29a05759a294..c3aa8b5fb51d 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -168,7 +168,7 @@ static void dw_pci_bottom_mask(struct irq_data *data)
> bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL;
>
> pp->irq_status[ctrl] &= ~(1 << bit);
> - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4,
> + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
> pp->irq_status[ctrl]);
> }
>
> @@ -191,7 +191,7 @@ static void dw_pci_bottom_unmask(struct irq_data *data)
> bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL;
>
> pp->irq_status[ctrl] |= 1 << bit;
> - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4,
> + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
> pp->irq_status[ctrl]);
> }
>
>
I've tested this patch with the fix-up [1] some time ago, it worked fine under
stress tests with a NVMe EP (MSI-X).
[1] https://marc.info/?l=linux-pci&m=154218928401960&w=2
Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
next prev parent reply other threads:[~2018-12-04 9:45 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-13 22:57 [PATCH 0/3] PCI: designware: Fixing MSI handling flow Marc Zyngier
2018-11-13 22:57 ` [PATCH 1/3] PCI: designware: Use interrupt masking instead of disabling Marc Zyngier
2018-12-03 18:02 ` [1/3] " Niklas Cassel
2018-12-04 9:41 ` Gustavo Pimentel [this message]
2018-11-13 22:57 ` [PATCH 2/3] PCI: designware: Take lock when ACKing an interrupt Marc Zyngier
2018-11-14 19:08 ` Trent Piepho
2018-12-03 18:02 ` [2/3] " Niklas Cassel
2018-12-04 9:41 ` [PATCH 2/3] " Gustavo Pimentel
2018-11-13 22:57 ` [PATCH 3/3] PCI: designware: Move interrupt acking into the proper callback Marc Zyngier
2018-11-14 19:01 ` Trent Piepho
2018-12-03 18:02 ` [3/3] " Niklas Cassel
2018-12-04 9:41 ` [PATCH 3/3] " Gustavo Pimentel
2018-12-04 10:20 ` Kishon Vijay Abraham I
2018-12-04 13:45 ` Marc Zyngier
2018-12-07 8:12 ` Kishon Vijay Abraham I
2018-12-07 9:45 ` Marc Zyngier
2018-12-07 10:13 ` Kishon Vijay Abraham I
2018-12-11 12:35 ` Lorenzo Pieralisi
2018-12-12 5:54 ` Kishon Vijay Abraham I
2018-11-13 23:16 ` [PATCH 0/3] PCI: designware: Fixing MSI handling flow Gustavo Pimentel
2018-11-14 9:54 ` Marc Zyngier
2018-11-14 19:19 ` Trent Piepho
2018-11-14 22:01 ` Marc Zyngier
2018-11-14 22:25 ` Trent Piepho
2018-11-14 22:44 ` Marc Zyngier
2018-11-14 23:23 ` Trent Piepho
2018-11-19 20:37 ` Trent Piepho
2018-11-22 12:03 ` Gustavo Pimentel
2018-11-22 16:07 ` Gustavo Pimentel
2018-11-22 16:26 ` Lorenzo Pieralisi
2018-11-22 16:38 ` Marc Zyngier
2018-11-22 17:40 ` Gustavo Pimentel
2018-11-26 16:06 ` Trent Piepho
2018-11-27 7:51 ` Marc Zyngier
2018-11-27 17:23 ` Trent Piepho
2018-11-22 17:49 ` Gustavo Pimentel
2018-11-26 15:52 ` Trent Piepho
2018-11-27 7:50 ` Marc Zyngier
2018-11-27 18:12 ` Trent Piepho
2018-12-07 16:16 ` Gustavo Pimentel
2018-11-14 18:28 ` Trent Piepho
2018-11-14 22:07 ` Marc Zyngier
2018-11-14 22:50 ` Trent Piepho
2018-11-15 15:22 ` Gustavo Pimentel
2018-11-15 18:37 ` Trent Piepho
2018-11-15 19:29 ` Marc Zyngier
2018-11-19 20:14 ` Trent Piepho
2018-11-21 17:24 ` Stanimir Varbanov
2018-12-01 23:50 ` Niklas Cassel
2018-12-02 11:28 ` Stanimir Varbanov
2018-12-03 10:42 ` Lorenzo Pieralisi
2018-12-03 13:09 ` Niklas Cassel
2018-12-03 17:42 ` Lorenzo Pieralisi
2018-12-03 20:31 ` Trent Piepho
2018-12-10 16:17 ` Lorenzo Pieralisi
2018-12-10 16:30 ` Marc Zyngier
2018-12-10 18:15 ` Trent Piepho
2018-12-10 18:31 ` Marc Zyngier
2018-12-10 20:34 ` Trent Piepho
2018-12-12 9:10 ` Gustavo Pimentel
2018-12-12 8:55 ` Gustavo Pimentel
2018-12-11 11:43 ` Lorenzo Pieralisi
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