From: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
To: Marc Zyngier <marc.zyngier@arm.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <helgaas@google.com>,
Trent Piepho <tpiepho@impinj.com>,
Jingoo Han <jingoohan1@gmail.com>,
"faiz_abbas@ti.com" <faiz_abbas@ti.com>,
Joao Pinto <Joao.Pinto@synopsys.com>, Vignesh R <vigneshr@ti.com>
Subject: Re: [PATCH 0/3] PCI: designware: Fixing MSI handling flow
Date: Thu, 22 Nov 2018 12:03:25 +0000 [thread overview]
Message-ID: <9b63c20b-f928-7c40-2734-00ed783625f5@synopsys.com> (raw)
In-Reply-To: <86a7mcdlwg.wl-marc.zyngier@arm.com>
Hi all,
>
> I just realised (at 1am!) that the first patch is awfully buggy:
> - ENABLE and MASK have opposite polarities
> - There is nothing initialising the ENABLE and MASK registers
>
> I've stashed the following fix-up on top of the existing series:
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index f06e67c60593..0fa9e8fdce66 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -166,7 +166,7 @@ static void dw_pci_bottom_mask(struct irq_data *data)
(snip)
I used your patch and made it more perceptible in my opinion, (basically I
transformed the variable irq_mask (previous irq_status) into a mirror of MASK
registers, which removed the need for the *NOT* operation and forced the mask
operation swap in the callbacks)
Lorenzo can you apply this fix-up in your branch test/pci-dwc-msi? Maybe merging
with eca44651920c ("PCI: designware: Move interrupt acking into the proper
callback"), perhaps.
I've tested Marc's patch series (with and without my fix-up and both) with a
NVme EP that generates a burst of 19 MSI-X interrupts. Both approaches are
working fine.
Just a couple of suggestions Lorenzo, maybe you could exchange the *designware*
by *dwc* on all patch series titles and on eca44651920c("PCI: designware: Move
interrupt acking into the proper callback") replace *acking* by *ACKing* like
previous patch has.
Marc thanks for this patch fix! :)
Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c
b/drivers/pci/controller/dwc/pcie-designware-host.c
index 0fa9e8f..a5132b3 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -164,9 +164,9 @@ static void dw_pci_bottom_mask(struct irq_data *data)
res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL;
- pp->irq_status[ctrl] &= ~(1 << bit);
+ pp->irq_mask[ctrl] |= BIT(bit);
dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
- ~pp->irq_status[ctrl]);
+ pp->irq_mask[ctrl]);
}
raw_spin_unlock_irqrestore(&pp->lock, flags);
@@ -187,30 +187,30 @@ static void dw_pci_bottom_unmask(struct irq_data *data)
res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL;
- pp->irq_status[ctrl] |= 1 << bit;
+ pp->irq_mask[ctrl] &= ~BIT(bit);
dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
- ~pp->irq_status[ctrl]);
+ pp->irq_mask[ctrl]);
}
raw_spin_unlock_irqrestore(&pp->lock, flags);
}
-static void dw_pci_bottom_ack(struct irq_data *d)
+static void dw_pci_bottom_ack(struct irq_data *data)
{
- struct pcie_port *pp = irq_data_get_irq_chip_data(d);
+ struct pcie_port *pp = irq_data_get_irq_chip_data(data);
unsigned int res, bit, ctrl;
unsigned long flags;
- ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
+ ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL;
res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
- bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
+ bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL;
raw_spin_lock_irqsave(&pp->lock, flags);
- dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, 1 << bit);
+ dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, BIT(bit));
if (pp->ops->msi_irq_ack)
- pp->ops->msi_irq_ack(d->hwirq, pp);
+ pp->ops->msi_irq_ack(data->hwirq, pp);
raw_spin_unlock_irqrestore(&pp->lock, flags);
}
@@ -665,13 +665,13 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
/* Initialize IRQ Status array */
for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
+ pp->irq_mask[ctrl] = ~0;
dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK +
(ctrl * MSI_REG_CTRL_BLOCK_SIZE),
- 4, ~0);
+ 4, pp->irq_mask[ctrl]);
dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE +
(ctrl * MSI_REG_CTRL_BLOCK_SIZE),
4, ~0);
- pp->irq_status[ctrl] = 0;
}
/* Setup RC BARs */
diff --git a/drivers/pci/controller/dwc/pcie-designware.h
b/drivers/pci/controller/dwc/pcie-designware.h
index 0989d88..9d1614a 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -169,7 +169,7 @@ struct pcie_port {
struct irq_domain *msi_domain;
dma_addr_t msi_data;
u32 num_vectors;
- u32 irq_status[MAX_MSI_CTRLS];
+ u32 irq_mask[MAX_MSI_CTRLS];
raw_spinlock_t lock;
DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
};
next prev parent reply other threads:[~2018-11-22 12:07 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-13 22:57 [PATCH 0/3] PCI: designware: Fixing MSI handling flow Marc Zyngier
2018-11-13 22:57 ` [PATCH 1/3] PCI: designware: Use interrupt masking instead of disabling Marc Zyngier
2018-12-03 18:02 ` [1/3] " Niklas Cassel
2018-12-04 9:41 ` [PATCH 1/3] " Gustavo Pimentel
2018-11-13 22:57 ` [PATCH 2/3] PCI: designware: Take lock when ACKing an interrupt Marc Zyngier
2018-11-14 19:08 ` Trent Piepho
2018-12-03 18:02 ` [2/3] " Niklas Cassel
2018-12-04 9:41 ` [PATCH 2/3] " Gustavo Pimentel
2018-11-13 22:57 ` [PATCH 3/3] PCI: designware: Move interrupt acking into the proper callback Marc Zyngier
2018-11-14 19:01 ` Trent Piepho
2018-12-03 18:02 ` [3/3] " Niklas Cassel
2018-12-04 9:41 ` [PATCH 3/3] " Gustavo Pimentel
2018-12-04 10:20 ` Kishon Vijay Abraham I
2018-12-04 13:45 ` Marc Zyngier
2018-12-07 8:12 ` Kishon Vijay Abraham I
2018-12-07 9:45 ` Marc Zyngier
2018-12-07 10:13 ` Kishon Vijay Abraham I
2018-12-11 12:35 ` Lorenzo Pieralisi
2018-12-12 5:54 ` Kishon Vijay Abraham I
2018-11-13 23:16 ` [PATCH 0/3] PCI: designware: Fixing MSI handling flow Gustavo Pimentel
2018-11-14 9:54 ` Marc Zyngier
2018-11-14 19:19 ` Trent Piepho
2018-11-14 22:01 ` Marc Zyngier
2018-11-14 22:25 ` Trent Piepho
2018-11-14 22:44 ` Marc Zyngier
2018-11-14 23:23 ` Trent Piepho
2018-11-19 20:37 ` Trent Piepho
2018-11-22 12:03 ` Gustavo Pimentel [this message]
2018-11-22 16:07 ` Gustavo Pimentel
2018-11-22 16:26 ` Lorenzo Pieralisi
2018-11-22 16:38 ` Marc Zyngier
2018-11-22 17:40 ` Gustavo Pimentel
2018-11-26 16:06 ` Trent Piepho
2018-11-27 7:51 ` Marc Zyngier
2018-11-27 17:23 ` Trent Piepho
2018-11-22 17:49 ` Gustavo Pimentel
2018-11-26 15:52 ` Trent Piepho
2018-11-27 7:50 ` Marc Zyngier
2018-11-27 18:12 ` Trent Piepho
2018-12-07 16:16 ` Gustavo Pimentel
2018-11-14 18:28 ` Trent Piepho
2018-11-14 22:07 ` Marc Zyngier
2018-11-14 22:50 ` Trent Piepho
2018-11-15 15:22 ` Gustavo Pimentel
2018-11-15 18:37 ` Trent Piepho
2018-11-15 19:29 ` Marc Zyngier
2018-11-19 20:14 ` Trent Piepho
2018-11-21 17:24 ` Stanimir Varbanov
2018-12-01 23:50 ` Niklas Cassel
2018-12-02 11:28 ` Stanimir Varbanov
2018-12-03 10:42 ` Lorenzo Pieralisi
2018-12-03 13:09 ` Niklas Cassel
2018-12-03 17:42 ` Lorenzo Pieralisi
2018-12-03 20:31 ` Trent Piepho
2018-12-10 16:17 ` Lorenzo Pieralisi
2018-12-10 16:30 ` Marc Zyngier
2018-12-10 18:15 ` Trent Piepho
2018-12-10 18:31 ` Marc Zyngier
2018-12-10 20:34 ` Trent Piepho
2018-12-12 9:10 ` Gustavo Pimentel
2018-12-12 8:55 ` Gustavo Pimentel
2018-12-11 11:43 ` Lorenzo Pieralisi
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