From: Lucas Stach <l.stach@pengutronix.de>
To: Andrey Smirnov <andrew.smirnov@gmail.com>, linux-pci@vger.kernel.org
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Fabio Estevam <fabio.estevam@nxp.com>,
Chris Healy <cphealy@gmail.com>,
Leonard Crestez <leonard.crestez@nxp.com>,
"A.s. Dong" <aisheng.dong@nxp.com>,
Richard Zhu <hongxing.zhu@nxp.com>,
linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 05/11] PCI: dwc: imx6: Share PHY debug register definitions
Date: Fri, 12 Apr 2019 17:56:18 +0200 [thread overview]
Message-ID: <1555084578.11529.32.camel@pengutronix.de> (raw)
In-Reply-To: <20190401042547.14067-6-andrew.smirnov@gmail.com>
Am Sonntag, den 31.03.2019, 21:25 -0700 schrieb Andrey Smirnov:
> Both pcie-designware.c and pci-imx6.c contain custom definitions for
> PHY debug registers R0/R1 and on top of that there's already a
> definition for R0 in pcie-designware.h. Move all of the definitions to
> pcie-designware.h. No functional change intended.
>
> > Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > Cc: Fabio Estevam <fabio.estevam@nxp.com>
> > Cc: Chris Healy <cphealy@gmail.com>
> > Cc: Lucas Stach <l.stach@pengutronix.de>
> > Cc: Leonard Crestez <leonard.crestez@nxp.com>
> > Cc: "A.s. Dong" <aisheng.dong@nxp.com>
> > Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: linux-imx@nxp.com
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Cc: linux-pci@vger.kernel.org
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 6 ++----
> drivers/pci/controller/dwc/pcie-designware.c | 12 +++---------
> drivers/pci/controller/dwc/pcie-designware.h | 3 +++
> 3 files changed, 8 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 92c40c250a34..bb95a3273ca2 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -103,8 +103,6 @@ struct imx6_pcie {
>
> /* PCIe Port Logic registers (memory-mapped) */
> #define PL_OFFSET 0x700
> -#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
> -#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
>
> #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
> #define PCIE_PHY_CTRL_DATA_LOC 0
> @@ -839,8 +837,8 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
>
> err_reset_phy:
> > dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
> > - dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
> > - dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
> > + dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0),
> > + dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1));
> > imx6_pcie_reset_phy(imx6_pcie);
> > return ret;
> }
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 31f6331ca46f..086e87a40316 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -14,12 +14,6 @@
>
> #include "pcie-designware.h"
>
> -/* PCIe Port Logic registers */
> > -#define PLR_OFFSET 0x700
> > -#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
> > -#define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4)
> > -#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29)
> -
> int dw_pcie_read(void __iomem *addr, int size, u32 *val)
> {
> > if (!IS_ALIGNED((uintptr_t)addr, size)) {
> @@ -334,9 +328,9 @@ int dw_pcie_link_up(struct dw_pcie *pci)
> > if (pci->ops->link_up)
> > return pci->ops->link_up(pci);
>
> > - val = readl(pci->dbi_base + PCIE_PHY_DEBUG_R1);
> > - return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) &&
> > - (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
> > + val = readl(pci->dbi_base + PCIE_PORT_DEBUG1);
> > + return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
> > + (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
> }
>
> void dw_pcie_setup(struct dw_pcie *pci)
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 377f4c0b52da..662bb9082c76 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -41,6 +41,9 @@
> > #define PCIE_PORT_DEBUG0 0x728
> > #define PORT_LOGIC_LTSSM_STATE_MASK 0x1f
> > #define PORT_LOGIC_LTSSM_STATE_L0 0x11
> > +#define PCIE_PORT_DEBUG1 0x72C
> > +#define PCIE_PORT_DEBUG1_LINK_UP (0x1 << 4)
> > +#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING (0x1 << 29)
>
> > #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
> > #define PORT_LOGIC_SPEED_CHANGE BIT(17)
next prev parent reply other threads:[~2019-04-12 15:56 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-01 4:25 [PATCH v3 00/11] i.MX6, DesignWare PCI improvements Andrey Smirnov
2019-04-01 4:25 ` [PATCH v3 01/11] PCI: imx6: Simplify imx7d_pcie_wait_for_phy_pll_lock() Andrey Smirnov
2019-04-12 15:49 ` Lucas Stach
2019-04-01 4:25 ` [PATCH v3 02/11] PCI: imx6: Remove redundant debug tracing Andrey Smirnov
2019-04-12 15:53 ` Lucas Stach
2019-04-14 18:47 ` Andrey Smirnov
2019-04-01 4:25 ` [PATCH v3 03/11] PCI: imx6: Return -ETIMEOUT from imx6_pcie_wait_for_speed_change() Andrey Smirnov
2019-04-12 15:54 ` Lucas Stach
2019-04-01 4:25 ` [PATCH v3 04/11] PCI: imx6: Remove PCIE_PL_PFLR_* constants Andrey Smirnov
2019-04-12 15:54 ` Lucas Stach
2019-04-01 4:25 ` [PATCH v3 05/11] PCI: dwc: imx6: Share PHY debug register definitions Andrey Smirnov
2019-04-12 15:56 ` Lucas Stach [this message]
2019-04-01 4:25 ` [PATCH v3 06/11] PCI: imx6: Make use of BIT() in constant definitions Andrey Smirnov
2019-04-12 15:56 ` Lucas Stach
2019-04-01 4:25 ` [PATCH v3 07/11] PCI: imx6: Simplify bit operations in PHY functions Andrey Smirnov
2019-04-12 15:59 ` Lucas Stach
2019-04-01 4:25 ` [PATCH v3 08/11] PCI: imx6: Simplify pcie_phy_poll_ack() Andrey Smirnov
2019-04-12 16:12 ` Lucas Stach
2019-04-14 18:46 ` Andrey Smirnov
2019-04-01 4:25 ` [PATCH v3 09/11] PCI: imx6: Restrict PHY register data to 16-bit Andrey Smirnov
2019-04-12 16:15 ` Lucas Stach
2019-04-01 4:25 ` [PATCH v3 10/11] PCI: imx6: Use flags to indicate support for suspend Andrey Smirnov
2019-04-12 16:17 ` Lucas Stach
2019-04-01 4:25 ` [PATCH v3 11/11] PCI: imx6: Replace calls to udelay() with usleep_range() Andrey Smirnov
2019-04-12 16:26 ` Lucas Stach
2019-04-14 18:48 ` Andrey Smirnov
2019-04-12 9:32 ` [PATCH v3 00/11] i.MX6, DesignWare PCI improvements Lorenzo Pieralisi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1555084578.11529.32.camel@pengutronix.de \
--to=l.stach@pengutronix.de \
--cc=aisheng.dong@nxp.com \
--cc=andrew.smirnov@gmail.com \
--cc=bhelgaas@google.com \
--cc=cphealy@gmail.com \
--cc=fabio.estevam@nxp.com \
--cc=hongxing.zhu@nxp.com \
--cc=leonard.crestez@nxp.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-imx@nxp.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).