From: Rob Herring <robh@kernel.org>
To: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: "Rob Herring" <robh+dt@kernel.org>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
linux-pci@vger.kernel.org, "Frank Li" <Frank.Li@nxp.com>,
"Pavel Parkhomenko" <Pavel.Parkhomenko@baikalelectronics.ru>,
linux-kernel@vger.kernel.org,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
devicetree@vger.kernel.org, "Krzysztof Wilczyński" <kw@linux.com>,
"Serge Semin" <fancer.lancer@gmail.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Jingoo Han" <jingoohan1@gmail.com>,
"Alexey Malahov" <Alexey.Malahov@baikalelectronics.ru>
Subject: Re: [PATCH v5 05/20] dt-bindings: PCI: dwc: Add phys/phy-names common properties
Date: Mon, 22 Aug 2022 16:57:24 -0500 [thread overview]
Message-ID: <1661205444.106003.931361.nullmailer@robh.at.kernel.org> (raw)
In-Reply-To: <20220822184701.25246-6-Sergey.Semin@baikalelectronics.ru>
On Mon, 22 Aug 2022 21:46:46 +0300, Serge Semin wrote:
> It's normal to have the DW PCIe RP/EP DT-nodes equipped with the explicit
> PHY phandle references. There can be up to 16 PHYs attach in accordance
> with the maximum number of supported PCIe lanes. Let's extend the common
> DW PCIe controller schema with the 'phys' and 'phy-names' properties
> definition. The PHY names are defined with the regexp pattern
> '^pcie([0-9]+|-?phy[0-9]*)?$' so to match the names currently supported by
> the DW PCIe platform drivers ("pcie": meson; "pciephy": qcom, imx6;
> "pcie-phy": uniphier, rockchip, spear13xx; "pcie": intel-gw; "pcie-phy%d":
> keystone, dra7xx; "pcie": histb, etc). Though the "pcie%d" format would
> the most preferable in this case.
>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
>
> ---
>
> Changelog v3:
> - This is a new patch unpinned from the next one:
> https://lore.kernel.org/linux-pci/20220503214638.1895-2-Sergey.Semin@baikalelectronics.ru/
> by the Rob' request. (@Rob)
>
> Changelog v5:
> - Add a note about having line-based PHY phandles order. (@Rob)
> - Prefer 'pcie[0-9]+' PHY-names over the rest of the cases. (@Rob)
> ---
> .../bindings/pci/snps,dw-pcie-common.yaml | 19 +++++++++++++++++++
> .../bindings/pci/snps,dw-pcie-ep.yaml | 3 +++
> .../devicetree/bindings/pci/snps,dw-pcie.yaml | 3 +++
> 3 files changed, 25 insertions(+)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.example.dtb: pcie@14180000: phy-names: 'oneOf' conditional failed, one must be fixed:
'p2u-0' does not match '^pcie[0-9]+$'
'p2u-0' does not match '^pcie(-?phy[0-9]*)?$'
'p2u-1' does not match '^pcie[0-9]+$'
'p2u-1' does not match '^pcie(-?phy[0-9]*)?$'
'p2u-2' does not match '^pcie[0-9]+$'
'p2u-2' does not match '^pcie(-?phy[0-9]*)?$'
'p2u-3' does not match '^pcie[0-9]+$'
'p2u-3' does not match '^pcie(-?phy[0-9]*)?$'
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.example.dtb: pcie@14180000: Unevaluated properties are not allowed ('#address-cells', '#interrupt-cells', '#size-cells', 'bus-range', 'device_type', 'interrupt-map', 'interrupt-map-mask', 'linux,pci-domain', 'num-lanes', 'ranges', 'supports-clkreq' were unexpected)
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.example.dtb: pcie@14160000: phy-names: 'oneOf' conditional failed, one must be fixed:
'p2u-0' does not match '^pcie[0-9]+$'
'p2u-0' does not match '^pcie(-?phy[0-9]*)?$'
'p2u-1' does not match '^pcie[0-9]+$'
'p2u-1' does not match '^pcie(-?phy[0-9]*)?$'
'p2u-2' does not match '^pcie[0-9]+$'
'p2u-2' does not match '^pcie(-?phy[0-9]*)?$'
'p2u-3' does not match '^pcie[0-9]+$'
'p2u-3' does not match '^pcie(-?phy[0-9]*)?$'
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.example.dtb: pcie@14160000: Unevaluated properties are not allowed ('#address-cells', '#interrupt-cells', '#size-cells', 'bus-range', 'device_type', 'interrupt-map', 'interrupt-map-mask', 'linux,pci-domain', 'num-lanes', 'num-viewport', 'ranges' were unexpected)
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.example.dtb: pcie-ep@141a0000: phy-names: 'oneOf' conditional failed, one must be fixed:
'p2u-0' does not match '^pcie[0-9]+$'
'p2u-0' does not match '^pcie(-?phy[0-9]*)?$'
'p2u-1' does not match '^pcie[0-9]+$'
'p2u-1' does not match '^pcie(-?phy[0-9]*)?$'
'p2u-2' does not match '^pcie[0-9]+$'
'p2u-2' does not match '^pcie(-?phy[0-9]*)?$'
'p2u-3' does not match '^pcie[0-9]+$'
'p2u-3' does not match '^pcie(-?phy[0-9]*)?$'
'p2u-4' does not match '^pcie[0-9]+$'
'p2u-4' does not match '^pcie(-?phy[0-9]*)?$'
'p2u-5' does not match '^pcie[0-9]+$'
'p2u-5' does not match '^pcie(-?phy[0-9]*)?$'
'p2u-6' does not match '^pcie[0-9]+$'
'p2u-6' does not match '^pcie(-?phy[0-9]*)?$'
'p2u-7' does not match '^pcie[0-9]+$'
'p2u-7' does not match '^pcie(-?phy[0-9]*)?$'
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.example.dtb: pcie-ep@141a0000: Unevaluated properties are not allowed ('num-lanes' was unexpected)
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.example.dtb: pcie-ep@141a0000: phy-names: 'oneOf' conditional failed, one must be fixed:
'p2u-0' does not match '^pcie[0-9]+$'
'p2u-0' does not match '^pcie(-?phy[0-9]*)?$'
'p2u-1' does not match '^pcie[0-9]+$'
'p2u-1' does not match '^pcie(-?phy[0-9]*)?$'
'p2u-2' does not match '^pcie[0-9]+$'
'p2u-2' does not match '^pcie(-?phy[0-9]*)?$'
'p2u-3' does not match '^pcie[0-9]+$'
'p2u-3' does not match '^pcie(-?phy[0-9]*)?$'
'p2u-4' does not match '^pcie[0-9]+$'
'p2u-4' does not match '^pcie(-?phy[0-9]*)?$'
'p2u-5' does not match '^pcie[0-9]+$'
'p2u-5' does not match '^pcie(-?phy[0-9]*)?$'
'p2u-6' does not match '^pcie[0-9]+$'
'p2u-6' does not match '^pcie(-?phy[0-9]*)?$'
'p2u-7' does not match '^pcie[0-9]+$'
'p2u-7' does not match '^pcie(-?phy[0-9]*)?$'
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.example.dtb: pcie-ep@141a0000: Unevaluated properties are not allowed ('num-lanes' was unexpected)
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
next prev parent reply other threads:[~2022-08-22 21:57 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-22 18:46 [PATCH v5 00/20] PCI: dwc: Add generic resources and Baikal-T1 support Serge Semin
2022-08-22 18:46 ` [PATCH v5 01/20] dt-bindings: imx6q-pcie: Fix clock names for imx6sx and imx8mq Serge Semin
2022-08-22 21:57 ` Rob Herring
[not found] ` <8354660.EvYhyI6sBW@steina-w>
2022-08-25 13:01 ` Serge Semin
2022-08-22 18:46 ` [PATCH v5 02/20] dt-bindings: visconti-pcie: Fix interrupts array max constraints Serge Semin
2022-08-30 21:33 ` Rob Herring
2022-09-01 23:33 ` nobuhiro1.iwamatsu
2022-08-22 18:46 ` [PATCH v5 03/20] dt-bindings: PCI: dwc: Detach common RP/EP DT bindings Serge Semin
2022-08-22 18:46 ` [PATCH v5 04/20] dt-bindings: PCI: dwc: Remove bus node from the examples Serge Semin
2022-08-22 18:46 ` [PATCH v5 05/20] dt-bindings: PCI: dwc: Add phys/phy-names common properties Serge Semin
2022-08-22 21:57 ` Rob Herring [this message]
2022-08-25 15:13 ` Serge Semin
2022-08-22 18:46 ` [PATCH v5 06/20] dt-bindings: PCI: dwc: Add max-link-speed common property Serge Semin
2022-08-22 18:46 ` [PATCH v5 07/20] dt-bindings: PCI: dwc: Apply generic schema for generic device only Serge Semin
2022-08-31 21:18 ` Rob Herring
2022-08-22 18:46 ` [PATCH v5 08/20] dt-bindings: PCI: dwc: Add max-functions EP property Serge Semin
2022-08-22 18:46 ` [PATCH v5 09/20] dt-bindings: PCI: dwc: Add interrupts/interrupt-names common properties Serge Semin
2022-08-31 21:24 ` Rob Herring
2022-09-11 19:02 ` Serge Semin
2022-09-25 22:14 ` Serge Semin
2022-08-22 18:46 ` [PATCH v5 10/20] dt-bindings: PCI: dwc: Add reg/reg-names " Serge Semin
2022-08-22 18:46 ` [PATCH v5 11/20] dt-bindings: PCI: dwc: Add clocks/resets " Serge Semin
2022-08-22 18:46 ` [PATCH v5 12/20] dt-bindings: PCI: dwc: Add dma-coherent property Serge Semin
2022-08-31 21:25 ` Rob Herring
2022-08-22 18:46 ` [PATCH v5 13/20] dt-bindings: PCI: dwc: Apply common schema to Rockchip DW PCIe nodes Serge Semin
2022-08-31 21:26 ` Rob Herring
2022-09-11 19:09 ` Serge Semin
2022-08-22 18:46 ` [PATCH v5 14/20] dt-bindings: PCI: dwc: Add Baikal-T1 PCIe Root Port bindings Serge Semin
2022-08-31 21:28 ` Rob Herring
2022-08-22 18:46 ` [PATCH v5 15/20] PCI: dwc: Introduce dma-ranges property support for RC-host Serge Semin
2022-08-22 18:46 ` [PATCH v5 16/20] PCI: dwc: Introduce generic controller capabilities interface Serge Semin
2022-08-22 18:46 ` [PATCH v5 17/20] PCI: dwc: Introduce generic resources getter Serge Semin
2022-08-23 2:07 ` kernel test robot
2022-08-23 6:30 ` kernel test robot
2022-08-22 18:46 ` [PATCH v5 18/20] PCI: dwc: Combine iATU detection procedures Serge Semin
2022-08-22 18:47 ` [PATCH v5 19/20] PCI: dwc: Introduce generic platform clocks and resets Serge Semin
2022-08-22 18:47 ` [PATCH v5 20/20] PCI: dwc: Add Baikal-T1 PCIe controller support Serge Semin
2022-08-29 15:28 ` Lorenzo Pieralisi
2022-08-29 17:32 ` William McVicker
2022-09-12 0:20 ` Serge Semin
2022-08-31 8:36 ` Robin Murphy
2022-08-31 8:54 ` Robin Murphy
2022-09-12 0:25 ` Serge Semin
2022-09-26 13:09 ` Robin Murphy
2022-09-26 13:31 ` Serge Semin
2022-09-12 0:22 ` Serge Semin
2022-09-12 0:02 ` Serge Semin
2022-09-17 10:44 ` Lorenzo Pieralisi
2022-09-26 10:17 ` Lorenzo Pieralisi
2022-09-26 12:49 ` Serge Semin
2022-09-26 14:31 ` Christoph Hellwig
2022-09-26 20:53 ` Serge Semin
2022-09-26 23:08 ` William McVicker
2022-09-28 10:36 ` Serge Semin
2022-09-28 17:59 ` William McVicker
2022-08-29 10:09 ` [PATCH v5 00/20] PCI: dwc: Add generic resources and Baikal-T1 support Lorenzo Pieralisi
2022-09-11 19:14 ` Serge Semin
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