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From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
To: "Rob Herring" <robh+dt@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Jingoo Han" <jingoohan1@gmail.com>,
	"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>
Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>,
	Serge Semin <fancer.lancer@gmail.com>,
	Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
	Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>,
	Frank Li <Frank.Li@nxp.com>,
	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
	<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Subject: [PATCH v5 18/20] PCI: dwc: Combine iATU detection procedures
Date: Mon, 22 Aug 2022 21:46:59 +0300	[thread overview]
Message-ID: <20220822184701.25246-19-Sergey.Semin@baikalelectronics.ru> (raw)
In-Reply-To: <20220822184701.25246-1-Sergey.Semin@baikalelectronics.ru>

Since the iATU CSR region is now retrieved in the DW PCIe resources getter
there is no much benefits in the iATU detection procedures splitting up.
Therefore let's join the iATU unroll/viewport detection procedure with the
rest of the iATU parameters detection code. The resultant method will be
as coherent as before, while the redundant functions will be eliminated
thus producing more readable code.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Rob Herring <robh@kernel.org>

---

Changelog v3:
- This is a new patch created on v3 lap of the series.
---
 drivers/pci/controller/dwc/pcie-designware.c | 39 +++++---------------
 1 file changed, 10 insertions(+), 29 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index a8436027434d..d31f9d41d5cb 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -628,26 +628,21 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
 
 }
 
-static bool dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
-{
-	u32 val;
-
-	val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
-	if (val == 0xffffffff)
-		return true;
-
-	return false;
-}
-
-static void dw_pcie_iatu_detect_regions(struct dw_pcie *pci)
+void dw_pcie_iatu_detect(struct dw_pcie *pci)
 {
 	int max_region, ob, ib;
 	u32 val, min, dir;
 	u64 max;
 
-	if (dw_pcie_cap_is(pci, IATU_UNROLL)) {
+	val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
+	if (val == 0xFFFFFFFF) {
+		dw_pcie_cap_set(pci, IATU_UNROLL);
+
 		max_region = min((int)pci->atu_size / 512, 256);
 	} else {
+		pci->atu_base = pci->dbi_base + PCIE_ATU_VIEWPORT_BASE;
+		pci->atu_size = PCIE_ATU_VIEWPORT_SIZE;
+
 		dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, 0xFF);
 		max_region = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT) + 1;
 	}
@@ -689,23 +684,9 @@ static void dw_pcie_iatu_detect_regions(struct dw_pcie *pci)
 	pci->num_ib_windows = ib;
 	pci->region_align = 1 << fls(min);
 	pci->region_limit = (max << 32) | (SZ_4G - 1);
-}
-
-void dw_pcie_iatu_detect(struct dw_pcie *pci)
-{
-	if (dw_pcie_iatu_unroll_enabled(pci)) {
-		dw_pcie_cap_set(pci, IATU_UNROLL);
-	} else {
-		pci->atu_base = pci->dbi_base + PCIE_ATU_VIEWPORT_BASE;
-		pci->atu_size = PCIE_ATU_VIEWPORT_SIZE;
-	}
-
-	dw_pcie_iatu_detect_regions(pci);
-
-	dev_info(pci->dev, "iATU unroll: %s\n", dw_pcie_cap_is(pci, IATU_UNROLL) ?
-		"enabled" : "disabled");
 
-	dev_info(pci->dev, "iATU regions: %u ob, %u ib, align %uK, limit %lluG\n",
+	dev_info(pci->dev, "iATU: unroll %s, %u ob, %u ib, align %uK, limit %lluG\n",
+		 dw_pcie_cap_is(pci, IATU_UNROLL) ? "T" : "F",
 		 pci->num_ob_windows, pci->num_ib_windows,
 		 pci->region_align / SZ_1K, (pci->region_limit + 1) / SZ_1G);
 }
-- 
2.35.1


  parent reply	other threads:[~2022-08-22 18:49 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-22 18:46 [PATCH v5 00/20] PCI: dwc: Add generic resources and Baikal-T1 support Serge Semin
2022-08-22 18:46 ` [PATCH v5 01/20] dt-bindings: imx6q-pcie: Fix clock names for imx6sx and imx8mq Serge Semin
2022-08-22 21:57   ` Rob Herring
     [not found]   ` <8354660.EvYhyI6sBW@steina-w>
2022-08-25 13:01     ` Serge Semin
2022-08-22 18:46 ` [PATCH v5 02/20] dt-bindings: visconti-pcie: Fix interrupts array max constraints Serge Semin
2022-08-30 21:33   ` Rob Herring
2022-09-01 23:33   ` nobuhiro1.iwamatsu
2022-08-22 18:46 ` [PATCH v5 03/20] dt-bindings: PCI: dwc: Detach common RP/EP DT bindings Serge Semin
2022-08-22 18:46 ` [PATCH v5 04/20] dt-bindings: PCI: dwc: Remove bus node from the examples Serge Semin
2022-08-22 18:46 ` [PATCH v5 05/20] dt-bindings: PCI: dwc: Add phys/phy-names common properties Serge Semin
2022-08-22 21:57   ` Rob Herring
2022-08-25 15:13     ` Serge Semin
2022-08-22 18:46 ` [PATCH v5 06/20] dt-bindings: PCI: dwc: Add max-link-speed common property Serge Semin
2022-08-22 18:46 ` [PATCH v5 07/20] dt-bindings: PCI: dwc: Apply generic schema for generic device only Serge Semin
2022-08-31 21:18   ` Rob Herring
2022-08-22 18:46 ` [PATCH v5 08/20] dt-bindings: PCI: dwc: Add max-functions EP property Serge Semin
2022-08-22 18:46 ` [PATCH v5 09/20] dt-bindings: PCI: dwc: Add interrupts/interrupt-names common properties Serge Semin
2022-08-31 21:24   ` Rob Herring
2022-09-11 19:02     ` Serge Semin
2022-09-25 22:14       ` Serge Semin
2022-08-22 18:46 ` [PATCH v5 10/20] dt-bindings: PCI: dwc: Add reg/reg-names " Serge Semin
2022-08-22 18:46 ` [PATCH v5 11/20] dt-bindings: PCI: dwc: Add clocks/resets " Serge Semin
2022-08-22 18:46 ` [PATCH v5 12/20] dt-bindings: PCI: dwc: Add dma-coherent property Serge Semin
2022-08-31 21:25   ` Rob Herring
2022-08-22 18:46 ` [PATCH v5 13/20] dt-bindings: PCI: dwc: Apply common schema to Rockchip DW PCIe nodes Serge Semin
2022-08-31 21:26   ` Rob Herring
2022-09-11 19:09     ` Serge Semin
2022-08-22 18:46 ` [PATCH v5 14/20] dt-bindings: PCI: dwc: Add Baikal-T1 PCIe Root Port bindings Serge Semin
2022-08-31 21:28   ` Rob Herring
2022-08-22 18:46 ` [PATCH v5 15/20] PCI: dwc: Introduce dma-ranges property support for RC-host Serge Semin
2022-08-22 18:46 ` [PATCH v5 16/20] PCI: dwc: Introduce generic controller capabilities interface Serge Semin
2022-08-22 18:46 ` [PATCH v5 17/20] PCI: dwc: Introduce generic resources getter Serge Semin
2022-08-23  2:07   ` kernel test robot
2022-08-23  6:30   ` kernel test robot
2022-08-22 18:46 ` Serge Semin [this message]
2022-08-22 18:47 ` [PATCH v5 19/20] PCI: dwc: Introduce generic platform clocks and resets Serge Semin
2022-08-22 18:47 ` [PATCH v5 20/20] PCI: dwc: Add Baikal-T1 PCIe controller support Serge Semin
2022-08-29 15:28   ` Lorenzo Pieralisi
2022-08-29 17:32     ` William McVicker
2022-09-12  0:20       ` Serge Semin
2022-08-31  8:36     ` Robin Murphy
2022-08-31  8:54       ` Robin Murphy
2022-09-12  0:25         ` Serge Semin
2022-09-26 13:09           ` Robin Murphy
2022-09-26 13:31             ` Serge Semin
2022-09-12  0:22       ` Serge Semin
2022-09-12  0:02     ` Serge Semin
2022-09-17 10:44       ` Lorenzo Pieralisi
2022-09-26 10:17       ` Lorenzo Pieralisi
2022-09-26 12:49         ` Serge Semin
2022-09-26 14:31           ` Christoph Hellwig
2022-09-26 20:53             ` Serge Semin
2022-09-26 23:08               ` William McVicker
2022-09-28 10:36                 ` Serge Semin
2022-09-28 17:59                   ` William McVicker
2022-08-29 10:09 ` [PATCH v5 00/20] PCI: dwc: Add generic resources and Baikal-T1 support Lorenzo Pieralisi
2022-09-11 19:14   ` Serge Semin

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