From: Manikanta Maddireddy <mmaddireddy@nvidia.com>
To: <thierry.reding@gmail.com>, <bhelgaas@google.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>,
<jonathanh@nvidia.com>, <lorenzo.pieralisi@arm.com>,
<vidyas@nvidia.com>
Cc: <linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<devicetree@vger.kernel.org>,
Manikanta Maddireddy <mmaddireddy@nvidia.com>
Subject: [PATCH V3 21/29] PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of soc struct
Date: Mon, 13 May 2019 23:37:36 +0530 [thread overview]
Message-ID: <20190513180744.16493-22-mmaddireddy@nvidia.com> (raw)
In-Reply-To: <20190513180744.16493-1-mmaddireddy@nvidia.com>
Tegra186 and Tegra30 have three PCIe root ports. AFI_PEX2_CTRL register
is defined for third root port. Offset of this register in Tegra186 is
different from Tegra30, so add offset as part of soc data structure.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
---
V3: No change
V2: No change
drivers/pci/controller/pci-tegra.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
index 0024bc42b400..d20c88a79e00 100644
--- a/drivers/pci/controller/pci-tegra.c
+++ b/drivers/pci/controller/pci-tegra.c
@@ -169,7 +169,6 @@
#define AFI_PEX0_CTRL 0x110
#define AFI_PEX1_CTRL 0x118
-#define AFI_PEX2_CTRL 0x128
#define AFI_PEX_CTRL_RST (1 << 0)
#define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
#define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
@@ -308,6 +307,7 @@ struct tegra_pcie_soc {
unsigned int num_ports;
const struct tegra_pcie_port_soc *ports;
unsigned int msi_base_shift;
+ unsigned long afi_pex2_ctrl;
u32 pads_pll_ctl;
u32 tx_ref_sel;
u32 pads_refclk_cfg0;
@@ -518,6 +518,7 @@ static struct pci_ops tegra_pcie_ops = {
static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
{
+ const struct tegra_pcie_soc *soc = port->pcie->soc;
unsigned long ret = 0;
switch (port->index) {
@@ -530,7 +531,7 @@ static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
break;
case 2:
- ret = AFI_PEX2_CTRL;
+ ret = soc->afi_pex2_ctrl;
break;
}
@@ -2431,6 +2432,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
.num_ports = 2,
.ports = tegra20_pcie_ports,
.msi_base_shift = 0,
+ .afi_pex2_ctrl = 0x128,
.pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
.pads_refclk_cfg0 = 0xfa5cfa5c,
@@ -2548,6 +2550,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
.num_ports = 3,
.ports = tegra186_pcie_ports,
.msi_base_shift = 8,
+ .afi_pex2_ctrl = 0x19c,
.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
.pads_refclk_cfg0 = 0x80b880b8,
--
2.17.1
next prev parent reply other threads:[~2019-05-13 18:09 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-13 18:07 [PATCH V3 00/29] Enable Tegra PCIe root port features Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 01/29] soc/tegra: pmc: Export tegra_powergate_power_on() Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 02/29] PCI: tegra: Handle failure cases in tegra_pcie_power_on() Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 03/29] PCI: tegra: Rearrange Tegra PCIe driver functions Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 04/29] PCI: tegra: Mask AFI_INTR in runtime suspend Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 05/29] PCI: tegra: Fix PCIe host power up sequence Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 06/29] PCI: tegra: Add PCIe Gen2 link speed support Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 07/29] PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 08/29] PCI: tegra: Program UPHY electrical settings for Tegra210 Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 09/29] PCI: tegra: Enable opportunistic UpdateFC and ACK Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 10/29] PCI: tegra: Disable AFI dynamic clock gating Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 11/29] PCI: tegra: Process pending DLL transactions before entering L1 or L2 Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 12/29] PCI: tegra: Enable PCIe xclk clock clamping Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 13/29] PCI: tegra: Increase the deskew retry time Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 14/29] PCI: tegra: Add SW fixup for RAW violations Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 15/29] PCI: tegra: Update flow control timer frequency in Tegra210 Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 16/29] PCI: tegra: Set target speed as Gen1 before starting LTSSM Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 17/29] PCI: tegra: Fix PLLE power down issue due to CLKREQ# signal Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 18/29] PCI: tegra: Program AFI_CACHE* registers only for Tegra20 Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 19/29] PCI: tegra: Change PRSNT_SENSE IRQ log to debug Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 20/29] PCI: tegra: Use legacy IRQ for port service drivers Manikanta Maddireddy
2019-05-13 18:07 ` Manikanta Maddireddy [this message]
2019-05-13 18:07 ` [PATCH V3 22/29] PCI: tegra: Access endpoint config only if PCIe link is up Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 23/29] dt-bindings: pci: tegra: Document PCIe DPD pinctrl optional prop Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 24/29] arm64: tegra: Add PEX DPD states as pinctrl properties Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 25/29] PCI: tegra: Put PEX CLK & BIAS pads in DPD mode Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 26/29] PCI: Add DT binding for "reset-gpios" property Manikanta Maddireddy
2019-05-14 18:23 ` Rob Herring
2019-05-13 18:07 ` [PATCH V3 27/29] PCI: OF: Add of_pci_get_reset_gpio() to parse reset-gpios from DT Manikanta Maddireddy
2019-05-14 18:31 ` Rob Herring
2019-05-16 5:50 ` Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 28/29] PCI: tegra: Add support for GPIO based PERST# Manikanta Maddireddy
2019-05-13 18:07 ` [PATCH V3 29/29] PCI: tegra: Change link retry log level to debug Manikanta Maddireddy
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190513180744.16493-22-mmaddireddy@nvidia.com \
--to=mmaddireddy@nvidia.com \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=jonathanh@nvidia.com \
--cc=linux-pci@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=mark.rutland@arm.com \
--cc=robh+dt@kernel.org \
--cc=thierry.reding@gmail.com \
--cc=vidyas@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).