[Patch 0/1] pciutils: Add available DVSEC Details

[Patch 0/1] pciutils: Add available DVSEC Details

[Sean V Kelley]

Add separate Designated Vendor Specific Capability (DVSEC) defines
and cap function so as to align with PCIe r5.0, sec 7.9.6.2 terms and
provide available details.  First step in later adding support for CXL.

Sean V Kelley (1):
  lspci: Add available DVSEC details

 lib/header.h    |   4 +
 ls-ecaps.c      |  25 +++-
 tests/cap-dvsec | 340 ++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 368 insertions(+), 1 deletion(-)
 create mode 100644 tests/cap-dvsec

--
2.26.0

[Patch 1/1] lspci: Add available DVSEC details

[Sean V Kelley]

Instead of current generic 'unknown' output for DVSEC, add details on
Vendor ID, Rev, etc.

Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com>
---
 lib/header.h    |   4 +
 ls-ecaps.c      |  25 +++-
 tests/cap-dvsec | 340 ++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 368 insertions(+), 1 deletion(-)
 create mode 100644 tests/cap-dvsec

diff --git a/lib/header.h b/lib/header.h
index bfdcc80..daeddeb 100644
--- a/lib/header.h
+++ b/lib/header.h
@@ -1042,6 +1042,10 @@
 #define PCI_EVNDR_HEADER	4	/* Vendor-Specific Header */
 #define PCI_EVNDR_REGISTERS	8	/* Vendor-Specific Registers */
 
+/* PCIe Designated Vendor-Specific Capability */
+#define PCI_DVSEC_HEADER1	4	/* Designated Vendor-Specific Header 1 */
+#define PCI_DVSEC_HEADER2	8	/* Designated Vendor-Specific Header 2 */
+
 /* Access Control Services */
 #define PCI_ACS_CAP		0x04	/* ACS Capability Register */
 #define PCI_ACS_CAP_VALID	0x0001	/* ACS Source Validation */
diff --git a/ls-ecaps.c b/ls-ecaps.c
index 0021734..937dcc4 100644
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -634,6 +634,29 @@ cap_rclink(struct device *d, int where)
     }
 }
 
+static void
+cap_dvsec(struct device *d, int where)
+{
+  u32 hdr;
+
+  printf("Designated Vendor Specific Extended Capability:\n");
+  if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8))
+    {
+      printf("<unreadable>\n");
+      return;
+    }
+
+  hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1);
+  printf("\t\tDVSEC Vendor ID=%04x Rev=%d Len=%03x <?>\n",
+    BITS(hdr, 0, 16),
+    BITS(hdr, 16, 4),
+    BITS(hdr, 20, 12));
+
+  hdr = get_conf_long(d, where + PCI_DVSEC_HEADER2);
+  printf("\t\tDVSEC ID=%04x <?>\n",
+    BITS(hdr, 0, 16));
+}
+
 static void
 cap_evendor(struct device *d, int where)
 {
@@ -924,7 +947,7 @@ show_ext_caps(struct device *d, int type)
 	    printf("Readiness Time Reporting <?>\n");
 	    break;
 	  case PCI_EXT_CAP_ID_DVSEC:
-	    printf("Designated Vendor-Specific <?>\n");
+	    cap_dvsec(d, where);
 	    break;
 	  case PCI_EXT_CAP_ID_VF_REBAR:
 	    printf("VF Resizable BAR <?>\n");
diff --git a/tests/cap-dvsec b/tests/cap-dvsec
new file mode 100644
index 0000000..3b3558c
--- /dev/null
+++ b/tests/cap-dvsec
@@ -0,0 +1,340 @@
+4e:00.0 Unassigned class [ff00]: Intel Corporation Device 0d93
+        Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
+        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+        Interrupt: pin A routed to IRQ 255
+        NUMA node: 0
+        Region 0: Memory at b3100000 (32-bit, non-prefetchable) [disabled] [size=1M]
+        Region 2: I/O ports at a400 [disabled] [size=1K]
+        Region 4: Memory at b1000000 (32-bit, prefetchable) [disabled] [size=16M]
+        Capabilities: [40] Express (v2) Root Complex Integrated Endpoint, MSI 00
+                DevCap: MaxPayload 256 bytes, PhantFunc 0
+                        ExtTag+ RBE+ FLReset+
+                DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq-
+                        RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop- FLReset-
+                        MaxPayload 128 bytes, MaxReadReq 512 bytes
+                DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
+                DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, NROPrPrP-, LTR+
+                         10BitTagComp-, 10BitTagReq-, OBFF Via WAKE#, ExtFmt+, EETLPPrefix+, MaxEETLPPrefixes 1
+                         EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
+                         FRS-
+                         AtomicOpsCap: 32bit+ 64bit+ 128bitCAS+
+                DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
+                         AtomicOpsCtl: ReqEn-
+        Capabilities: [80] MSI: Enable- Count=1/4 Maskable+ 64bit+
+                Address: 0000000000000000  Data: 0000
+                Masking: 00000000  Pending: 00000000
+        Capabilities: [a0] Power Management version 3
+                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
+                Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
+        Capabilities: [100 v1] Advanced Error Reporting
+                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+                UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
+                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
+                AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
+                        MultHdrRecCap+ MultHdrRecEn- TLPPfxPres- HdrLogCap-
+                HeaderLog: 00000000 00000000 00000000 00000000
+        Capabilities: [200 v1] Multi-Function Virtual Channel <?>
+        Capabilities: [300 v1] Virtual Channel
+                Caps:   LPEVC=0 RefClk=100ns PATEntryBits=1
+                Arb:    Fixed- WRR32- WRR64- WRR128-
+                Ctrl:   ArbSelect=Fixed
+                Status: InProgress-
+                VC0:    Caps:   PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
+                        Arb:    Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
+                        Ctrl:   Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
+                        Status: NegoPending- InProgress-
+        Capabilities: [550 v1] Multicast
+                McastCap: MaxGroups 64, WindowSz 1 (2 bytes)            McastCtl: NumGroups 1, Enable-
+                McastBAR: IndexPos 0, BaseAddr 0000000000000000
+                McastReceiveVec:      0000000000000000
+                McastBlockAllVec:     0000000000000000
+                McastBlockUntransVec: 0000000000000000
+        Capabilities: [588 v1] Latency Tolerance Reporting
+                Max snoop latency: 0ns
+                Max no snoop latency: 0ns
+        Capabilities: [5b0 v1] Transaction Processing Hints
+                Extended requester support
+                Steering table in TPH capability structure
+        Capabilities: [6e0 v1] Address Translation Service (ATS)
+                ATSCap: Invalidate Queue Depth: 00
+                ATSCtl: Enable-, Smallest Translation Unit: 00
+        Capabilities: [700 v1] Resizable BAR <?>
+        Capabilities: [714 v1] Secondary PCI Express
+                LnkCtl3: LnkEquIntrruptEn-, PerformEqu-
+                LaneErrStat: 0
+        Capabilities: [b20 v1] Page Request Interface (PRI)
+                PRICtl: Enable- Reset-
+                PRISta: RF- UPRGI- Stopped+
+                Page Request Capacity: 00000000, Page Request Allocation: 00000000
+        Capabilities: [b40 v1] Process Address Space ID (PASID)
+                PASIDCap: Exec+ Priv+, Max PASID Width: 14
+                PASIDCtl: Enable- Exec- Priv-
+        Capabilities: [b50 v1] Precision Time Measurement
+                PTMCap: Requester:- Responder:- Root:-
+                PTMClockGranularity: Unimplemented
+                PTMControl: Enabled:- RootSelected:-
+                PTMEffectiveGranularity: Unknown
+        Capabilities: [d00 v1] Vendor Specific Information: ID=0040 Rev=1 Len=04c <?>
+        Capabilities: [e00 v1] Designated Vendor Specific Extended Capability:
+                DVSEC Vendor ID=8086 Rev=0 Len=038 <?>
+                DVSEC ID=0000 <?>
+        Capabilities: [e38 v1] Device Serial Number 12-34-56-78-90-00-00-00
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+ea0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+eb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ec0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ed0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ee0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ef0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-- 
2.26.0

Re: [Patch 1/1] lspci: Add available DVSEC details

[Bjorn Helgaas]

On Thu, Apr 09, 2020 at 11:32:04AM -0700, Sean V Kelley wrote:
> Instead of current generic 'unknown' output for DVSEC, add details on
> Vendor ID, Rev, etc.
> 
> Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
> Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com>

Looks good to me.

> +static void
> +cap_dvsec(struct device *d, int where)
> +{
> +  u32 hdr;
> +
> +  printf("Designated Vendor Specific Extended Capability:\n");

s/Vendor Specific/Vendor-Specific/ to match the spec usage
s/ Extended Capability:// to match other lspci capability output (?)

> +4e:00.0 Unassigned class [ff00]: Intel Corporation Device 0d93

> +        Capabilities: [d00 v1] Vendor Specific Information: ID=0040 Rev=1 Len=04c <?>
> +        Capabilities: [e00 v1] Designated Vendor Specific Extended Capability:
> +                DVSEC Vendor ID=8086 Rev=0 Len=038 <?>
> +                DVSEC ID=0000 <?>
> +        Capabilities: [e38 v1] Device Serial Number 12-34-56-78-90-00-00-00
> +00: 86 80 93 0d 00 00 10 00 00 00 00 ff 00 00 80 00

Obviously this class code is wrong.  I assume it'll be fixed in real
hardware, but ironically we've just spent a few days chasing a problem
because of a Google Edge TPU with invalid class code.  In that case,
Linux doesn't assign resources to BARs, so things fall apart after
that.

Re: [Patch 1/1] lspci: Add available DVSEC details

[Sean V Kelley]

On 9 Apr 2020, at 12:56, Bjorn Helgaas wrote:

> On Thu, Apr 09, 2020 at 11:32:04AM -0700, Sean V Kelley wrote:
>> Instead of current generic 'unknown' output for DVSEC, add details on
>> Vendor ID, Rev, etc.
>>
>> Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
>> Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com>
>
> Looks good to me.
>
>> +static void
>> +cap_dvsec(struct device *d, int where)
>> +{
>> +  u32 hdr;
>> +
>> +  printf("Designated Vendor Specific Extended Capability:\n");
>

> s/Vendor Specific/Vendor-Specific/ to match the spec usage
> s/ Extended Capability:// to match other lspci capability output (?)
>

Sure, sounds good.

>> +4e:00.0 Unassigned class [ff00]: Intel Corporation Device 0d93
>
>> +        Capabilities: [d00 v1] Vendor Specific Information: ID=0040 
>> Rev=1 Len=04c <?>
>> +        Capabilities: [e00 v1] Designated Vendor Specific Extended 
>> Capability:
>> +                DVSEC Vendor ID=8086 Rev=0 Len=038 <?>
>> +                DVSEC ID=0000 <?>
>> +        Capabilities: [e38 v1] Device Serial Number 
>> 12-34-56-78-90-00-00-00
>> +00: 86 80 93 0d 00 00 10 00 00 00 00 ff 00 00 80 00
>
> Obviously this class code is wrong.  I assume it'll be fixed in real
> hardware, but ironically we've just spent a few days chasing a problem
> because of a Google Edge TPU with invalid class code.  In that case,
> Linux doesn't assign resources to BARs, so things fall apart after
> that.

Wow.  Easy to forget how much depends on it.  Yes, it will be fixed in 
real hardware with real IDs.  :)

Thanks,

Sean