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* [PATCH 1/3] PCI: Add quirks for Juniper FPGAs to set class code
@ 2020-09-15 15:11 Ming Qiao
  2020-09-15 15:11 ` [PATCH 2/3] PCI: Add quirks for Juniper ASICs " Ming Qiao
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Ming Qiao @ 2020-09-15 15:11 UTC (permalink / raw)
  To: bhelgaas, linux-pci, linux-kernel
  Cc: Ming Qiao, Debjit Ghosh, Santhanakrishnan Balraj, Rajat Jain

Some of the Juniper FPGAs do not report correct PCI class ID, which
would confuse kernel APIs accessing the specific class of devices.
Change them to PCI_CLASS_SYSTEM_OTHER << 8.

Also introduce Juniper vendor ID to be used in the quirks.
    
Signed-off-by: Debjit Ghosh <dghosh@juniper.net>
Signed-off-by: Santhanakrishnan Balraj <sbalraj@juniper.net>
Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Ming Qiao <mqiao@juniper.net>
---
 drivers/pci/quirks.c    | 25 +++++++++++++++++++++++++
 include/linux/pci_ids.h |  2 ++
 2 files changed, 27 insertions(+)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 2a589b6..61344d2 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -5632,3 +5632,28 @@ static void apex_pci_fixup_class(struct pci_dev *pdev)
 }
 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
 			       PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);
+
+/*
+ * PCI class reported by some Juniper FPGAs is not correct.
+ * Change it to SYSTEM.
+ */
+static void quirk_jnx_fpga(struct pci_dev *dev)
+{
+	if (!dmi_match(DMI_BOARD_VENDOR, "Juniper Networks Inc."))
+		return;
+
+	dev->class = PCI_CLASS_SYSTEM_OTHER << 8;
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x0004, quirk_jnx_fpga);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x006A, quirk_jnx_fpga);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x006B, quirk_jnx_fpga);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x006C, quirk_jnx_fpga);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x006E, quirk_jnx_fpga);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x0079, quirk_jnx_fpga);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x0083, quirk_jnx_fpga);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x0071, quirk_jnx_fpga);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x00A7, quirk_jnx_fpga);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x00A8, quirk_jnx_fpga);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x00A9, quirk_jnx_fpga);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x00AA, quirk_jnx_fpga);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_XILINX, 0x0505, quirk_jnx_fpga);
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 1ab1e24..bfbf8f1 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1859,6 +1859,8 @@
 #define PCI_VENDOR_ID_ESDGMBH		0x12fe
 #define PCI_DEVICE_ID_ESDGMBH_CPCIASIO4 0x0111
 
+#define PCI_VENDOR_ID_JUNIPER		0X1304
+
 #define PCI_VENDOR_ID_CB		0x1307	/* Measurement Computing */
 
 #define PCI_VENDOR_ID_SIIG		0x131f
-- 
2.10.0


^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [PATCH 2/3] PCI: Add quirks for Juniper ASICs to set class code
  2020-09-15 15:11 [PATCH 1/3] PCI: Add quirks for Juniper FPGAs to set class code Ming Qiao
@ 2020-09-15 15:11 ` Ming Qiao
  2020-09-15 15:11 ` [PATCH 3/3] PCI: Add quirks for Juniper ASICs to fix PCIe gen Ming Qiao
  2020-09-15 20:36 ` [PATCH 1/3] PCI: Add quirks for Juniper FPGAs to set class code Bjorn Helgaas
  2 siblings, 0 replies; 4+ messages in thread
From: Ming Qiao @ 2020-09-15 15:11 UTC (permalink / raw)
  To: bhelgaas, linux-pci, linux-kernel
  Cc: Ming Qiao, Debjit Ghosh, Santhanakrishnan Balraj, Rajat Jain

Some of the Juniper ASICs do not report correct PCI class ID, which
would confuse kernel APIs accessing the specific class of devices.
Change them to PCI_CLASS_NETWORK_OTHER << 8.
        
Signed-off-by: Debjit Ghosh <dghosh@juniper.net>
Signed-off-by: Santhanakrishnan Balraj <sbalraj@juniper.net>
Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Ming Qiao <mqiao@juniper.net>
---
 drivers/pci/quirks.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 61344d2..04dd490 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -5657,3 +5657,22 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x00A8, quirk_jnx_fpga);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x00A9, quirk_jnx_fpga);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x00AA, quirk_jnx_fpga);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_XILINX, 0x0505, quirk_jnx_fpga);
+
+/*
+ * PCI class reported by some Juniper ASICs is not correct.
+ * Change it to NETWORK.
+ */
+static void quirk_jnx_asic(struct pci_dev *dev)
+{
+	dev->class = PCI_CLASS_NETWORK_OTHER << 8;
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x003C, quirk_jnx_asic);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x003D, quirk_jnx_asic);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x003E, quirk_jnx_asic);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x0055, quirk_jnx_asic);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x005E, quirk_jnx_asic);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x005F, quirk_jnx_asic);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x008E, quirk_jnx_asic);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x008D, quirk_jnx_asic);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x0090, quirk_jnx_asic);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x00B2, quirk_jnx_asic);
-- 
2.10.0


^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [PATCH 3/3] PCI: Add quirks for Juniper ASICs to fix PCIe gen
  2020-09-15 15:11 [PATCH 1/3] PCI: Add quirks for Juniper FPGAs to set class code Ming Qiao
  2020-09-15 15:11 ` [PATCH 2/3] PCI: Add quirks for Juniper ASICs " Ming Qiao
@ 2020-09-15 15:11 ` Ming Qiao
  2020-09-15 20:36 ` [PATCH 1/3] PCI: Add quirks for Juniper FPGAs to set class code Bjorn Helgaas
  2 siblings, 0 replies; 4+ messages in thread
From: Ming Qiao @ 2020-09-15 15:11 UTC (permalink / raw)
  To: bhelgaas, linux-pci, linux-kernel; +Cc: Ming Qiao, Rajat Jain

Some of the Juniper ASICs report incorrect PCIe gen type for the PCIe
link to the root port. Make the root port to ignore these fields.
        
Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Ming Qiao <mqiao@juniper.net>
---
 drivers/pci/quirks.c | 42 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 04dd490..0a28a09 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -5658,6 +5658,45 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x00A9, quirk_jnx_fpga);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x00AA, quirk_jnx_fpga);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_XILINX, 0x0505, quirk_jnx_fpga);
 
+static struct dmi_system_id jnx_asic_pci_bug_affected_platforms[] = {
+	{
+	.ident = "Juniper Networks PTX MLC Card",
+	.matches = {
+		DMI_MATCH(DMI_BOARD_VENDOR, "Juniper Networks Inc."),
+		DMI_MATCH(DMI_BOARD_NAME, "0C0A")
+		},
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(dmi, jnx_asic_pci_bug_affected_platforms);
+
+#define INTEL_DEBUG_REG		0x8F8
+#define INTEL_DEBUG_REG_IGNORE_GEN	BIT(3)
+
+/*
+ * Some Juniper ASICs have an issue where they report incorrect gen type
+ * (Gen-1 / Gen-2) for the PCIe link to the root port.
+ * This workaround needs to be applied to each Intel root port which connects
+ * to such juniper ASIC. It causes the root port to ignore the incorrect
+ * fields.
+ */
+static void fixup_jnx_intel_root_port(struct pci_dev *dev)
+{
+	struct pci_dev *root;
+	u32 tmp32;
+	int ret;
+
+	root = pcie_find_root_port(dev);
+	if (!root || root->vendor != PCI_VENDOR_ID_INTEL)
+		return;
+
+	ret = pci_read_config_dword(root, INTEL_DEBUG_REG, &tmp32);
+	tmp32 |= INTEL_DEBUG_REG_IGNORE_GEN;
+	ret |= pci_write_config_dword(root, INTEL_DEBUG_REG, tmp32);
+	if (ret)
+		dev_err(&root->dev, "Failed on root port quirk. CONFIG_PCI_MMCONFIG not selected?\n");
+}
+
 /*
  * PCI class reported by some Juniper ASICs is not correct.
  * Change it to NETWORK.
@@ -5665,6 +5704,9 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_XILINX, 0x0505, quirk_jnx_fpga);
 static void quirk_jnx_asic(struct pci_dev *dev)
 {
 	dev->class = PCI_CLASS_NETWORK_OTHER << 8;
+
+	if (dmi_check_system(jnx_asic_pci_bug_affected_platforms))
+		fixup_jnx_intel_root_port(dev)
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x003C, quirk_jnx_asic);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x003D, quirk_jnx_asic);
-- 
2.10.0


^ permalink raw reply related	[flat|nested] 4+ messages in thread
* Re: [PATCH 1/3] PCI: Add quirks for Juniper FPGAs to set class code
  2020-09-15 15:11 [PATCH 1/3] PCI: Add quirks for Juniper FPGAs to set class code Ming Qiao
  2020-09-15 15:11 ` [PATCH 2/3] PCI: Add quirks for Juniper ASICs " Ming Qiao
  2020-09-15 15:11 ` [PATCH 3/3] PCI: Add quirks for Juniper ASICs to fix PCIe gen Ming Qiao
@ 2020-09-15 20:36 ` Bjorn Helgaas
  2 siblings, 0 replies; 4+ messages in thread
From: Bjorn Helgaas @ 2020-09-15 20:36 UTC (permalink / raw)
  To: Ming Qiao
  Cc: bhelgaas, linux-pci, linux-kernel, Debjit Ghosh,
	Santhanakrishnan Balraj, Rajat Jain

On Tue, Sep 15, 2020 at 08:11:01AM -0700, Ming Qiao wrote:
> Some of the Juniper FPGAs do not report correct PCI class ID, which
> would confuse kernel APIs accessing the specific class of devices.
> Change them to PCI_CLASS_SYSTEM_OTHER << 8.

Please include a note about the consequence of the incorrect class ID,
i.e., what happens without this quirk?  Does the system panic?  Does
some device not work correctly?  If so, which, and what does the
problem look like to a user?

"Confusing kernel APIs" is pretty general and won't help a user who is
seeing a problem to find this patch.

> Also introduce Juniper vendor ID to be used in the quirks.
>     
> Signed-off-by: Debjit Ghosh <dghosh@juniper.net>
> Signed-off-by: Santhanakrishnan Balraj <sbalraj@juniper.net>
> Signed-off-by: Rajat Jain <rajatja@google.com>
> Signed-off-by: Ming Qiao <mqiao@juniper.net>
> ---
>  drivers/pci/quirks.c    | 25 +++++++++++++++++++++++++
>  include/linux/pci_ids.h |  2 ++
>  2 files changed, 27 insertions(+)
> 
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 2a589b6..61344d2 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -5632,3 +5632,28 @@ static void apex_pci_fixup_class(struct pci_dev *pdev)
>  }
>  DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
>  			       PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);
> +
> +/*
> + * PCI class reported by some Juniper FPGAs is not correct.
> + * Change it to SYSTEM.
> + */
> +static void quirk_jnx_fpga(struct pci_dev *dev)
> +{
> +	if (!dmi_match(DMI_BOARD_VENDOR, "Juniper Networks Inc."))
> +		return;

Why is the DMI_BOARD_VENDOR relevant to this quirk?  This check seems
to mean that the class code is programmable by the BIOS, and all
BIOSes program it correctly *except* the Juniper BIOS.

If this is just a silicon defect in the chips, you shouldn't need to
check the DMI_BOARD_VENDOR.

> +	dev->class = PCI_CLASS_SYSTEM_OTHER << 8;
> +}
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x0004, quirk_jnx_fpga);
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x006A, quirk_jnx_fpga);
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x006B, quirk_jnx_fpga);
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x006C, quirk_jnx_fpga);
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x006E, quirk_jnx_fpga);
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x0079, quirk_jnx_fpga);
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x0083, quirk_jnx_fpga);
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x0071, quirk_jnx_fpga);
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x00A7, quirk_jnx_fpga);
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x00A8, quirk_jnx_fpga);
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x00A9, quirk_jnx_fpga);
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x00AA, quirk_jnx_fpga);
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_XILINX, 0x0505, quirk_jnx_fpga);
> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> index 1ab1e24..bfbf8f1 100644
> --- a/include/linux/pci_ids.h
> +++ b/include/linux/pci_ids.h
> @@ -1859,6 +1859,8 @@
>  #define PCI_VENDOR_ID_ESDGMBH		0x12fe
>  #define PCI_DEVICE_ID_ESDGMBH_CPCIASIO4 0x0111
>  
> +#define PCI_VENDOR_ID_JUNIPER		0X1304

Please use "0x1304" (lower-case 'x') like the rest of the file.

>  #define PCI_VENDOR_ID_CB		0x1307	/* Measurement Computing */
>  
>  #define PCI_VENDOR_ID_SIIG		0x131f
> -- 
> 2.10.0
> 

^ permalink raw reply	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-09-15 22:33 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2020-09-15 15:11 [PATCH 1/3] PCI: Add quirks for Juniper FPGAs to set class code Ming Qiao
2020-09-15 15:11 ` [PATCH 2/3] PCI: Add quirks for Juniper ASICs " Ming Qiao
2020-09-15 15:11 ` [PATCH 3/3] PCI: Add quirks for Juniper ASICs to fix PCIe gen Ming Qiao
2020-09-15 20:36 ` [PATCH 1/3] PCI: Add quirks for Juniper FPGAs to set class code Bjorn Helgaas

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