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From: Bjorn Helgaas <helgaas@kernel.org>
To: "Antti Järvinen" <antti.jarvinen@gmail.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	Alex Williamson <alex.williamson@redhat.com>,
	Murali Karicheri <m-karicheri2@ti.com>,
	Kishon Vijay Abraham I <kishon@ti.com>
Subject: Re: [PATCH] PCI: quirk for preventing bus reset on TI C667X
Date: Fri, 29 Jan 2021 17:49:46 -0600	[thread overview]
Message-ID: <20210129234946.GA124037@bjorn-Precision-5520> (raw)
In-Reply-To: <35612e76-0b97-7bb4-60b7-88ae6d53f0be@gmail.com>

On Tue, Jan 26, 2021 at 01:22:18PM +0200, Antti Järvinen wrote:
> On 22.1.2021 1.55, Bjorn Helgaas wrote:> 
> 
> > It looks like we would probably be trying a Secondary Bus Reset using
> > the bridge leading to the C667X.  Can you confirm? 
> 
> Yes, this is my understanding too.
> 
> > Wonder if you
> > could try doing what pci_reset_secondary_bus() does by hand:
> > 
> 
> I tried this by hand. It looks that result is same as through VFIO.
> 
> # cat sbr.sh
> BRIDGE=10:00.0
> C667X=11:00.0
> 
> setpci -s$C667X VENDOR_ID.w
> 
> VAL=$(setpci -s$BRIDGE BRIDGE_CONTROL.w)
> echo $VAL
> setpci -s$BRIDGE BRIDGE_CONTROL.w=$(($VAL | 0x40))
> sleep 1
> setpci -s$BRIDGE BRIDGE_CONTROL.w=$VAL
> sleep 1
> setpci -s$C667X VENDOR_ID.w=0
> setpci -s$C667X VENDOR_ID.w
> 
> 
> # ./sbr.sh
> 104c
> 0003
> ffff
> 
> 
> >   # BRIDGE=...                              # PCI address, e.g., 00:1c.0
> >   # C667X=...
> >   # setpci -s$C667X VENDOR_ID.w
> >   # setpci -s$BRIDGE BRIDGE_CONTROL.w       # prints "val"
> >   # setpci -s$BRIDGE BRIDGE_CONTROL.w=      # val | 0x40 (set SBR)
> >   # sleep 1
> >   # setpci -s$BRIDGE BRIDGE_CONTROL.w=      # val (clear SBR)
> >   # sleep 1
> >   # setpci -s$C667X VENDOR_ID.w=0
> >   # setpci -s$C667X VENDOR_ID.w
> > 
> > If we use this quirk and avoid the reset, I assume that means
> > assigning the device to VMs with VFIO will leak state between VMs?
> 
> I think this is true.

Alex, is there some warning about situations like this where a device
may leak state between VMs?

There's nothing in quirk_no_bus_reset() itself where we set
PCI_DEV_FLAGS_NO_BUS_RESET, and nothing in pci_parent_bus_reset() or
pci_dev_reset_slot_function() where we test it, but I didn't chase
into VFIO.

Seems important enough that we might want to mention it at least once
and maybe even every time we try to reset the device.  I hope the leak
isn't completely silent.

Bjorn

  reply	other threads:[~2021-01-29 23:50 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-12 15:36 [PATCH] PCI: quirk for preventing bus reset on TI C667X Antti Järvinen
2021-01-21 23:55 ` Bjorn Helgaas
2021-01-26 11:22   ` Antti Järvinen
2021-01-29 23:49     ` Bjorn Helgaas [this message]
2021-02-17 21:18   ` Bjorn Helgaas
2021-02-28 13:53     ` [PATCH v2] " Antti Järvinen
2021-03-07  0:22       ` Krzysztof Wilczyński
2021-03-08 14:21         ` [PATCH v3] PCI: Add " Antti Järvinen
2021-03-12 21:09           ` Bjorn Helgaas
2021-03-15 10:26             ` [PATCH v4] " Antti Järvinen
2021-04-19 12:44               ` Kishon Vijay Abraham I
2021-05-27 23:07               ` Bjorn Helgaas
2021-03-15 10:45             ` [PATCH v3] " Antti Järvinen
2021-03-08 14:28         ` [PATCH v2] PCI: " Antti Järvinen

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