Re: [PATCH v3] PCI: Add quirk for preventing bus reset on TI C667X

["Antti Järvinen" <antti.jarvinen@gmail.com>]

On 12.3.2021 23.09, Bjorn Helgaas wrote:
> On Mon, Mar 08, 2021 at 02:21:30PM +0000, Antti Järvinen wrote:
>> Some TI KeyStone C667X devices do no support bus/hot reset. Its PCIESS
>> automatically disables LTSSM when secondary bus reset is received and
>> device stops working. Prevent bus reset by adding quirk_no_bus_reset to
>> the device. With this change device can be assigned to VMs with VFIO,
>> but it will leak state between VMs.
> 
> s/do no/do/not/ (also in the comment below)
> 

Should be fixed in v4 patch.
 
> Does the user get any indication of this leaking state?  I looked
> through drivers/vfio and drivers/pci, but I haven't found anything
> yet.
> 

I haven't seen any indication too. 

Overall I think all devices having this quirk will leak state, as they
don't get resetted.


> We *could* log something in quirk_no_bus_reset(), but that would just
> be noise for people who don't pass the device through to a VM.  So
> maybe it would be nicer if we logged something when we actually *do*
> pass it through to a VM.
> 
>> Reference: https://e2e.ti.com/support/processors/f/791/t/954382
>> Signed-off-by: Antti Järvinen <antti.jarvinen@gmail.com>
>> ---
>>  drivers/pci/quirks.c | 10 ++++++++++
>>  1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
>> index 653660e3ba9e..d9201ad1ca39 100644
>> --- a/drivers/pci/quirks.c
>> +++ b/drivers/pci/quirks.c
>> @@ -3578,6 +3578,16 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
>>   */
>>  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
>>  
>> +/*
>> + * Some TI keystone C667X devices do no support bus/hot reset.
>> + * Its PCIESS automatically disables LTSSM when secondary bus reset is
>> + * received and device stops working. Prevent bus reset by adding
>> + * quirk_no_bus_reset to the device. With this change device can be
>> + * assigned to VMs with VFIO, but it will leak state between VMs.
>> + * Reference https://e2e.ti.com/support/processors/f/791/t/954382
>> + */
>> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);
>> +
>>  static void quirk_no_pm_reset(struct pci_dev *dev)
>>  {
>>  	/*
>> -- 
>> 2.17.1
>>