From: Ben Widawsky <ben.widawsky@intel.com>
To: linux-cxl@vger.kernel.org, linux-nvdimm@lists.01.org,
linux-pci@vger.kernel.org
Cc: patches@lists.linux.dev, Bjorn Helgaas <helgaas@kernel.org>,
Ben Widawsky <ben.widawsky@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <Jonathan.Cameron@Huawei.com>,
Vishal Verma <vishal.l.verma@intel.com>
Subject: [PATCH 01/13] cxl/core: Rename find_cxl_port
Date: Thu, 6 Jan 2022 16:37:44 -0800 [thread overview]
Message-ID: <20220107003756.806582-2-ben.widawsky@intel.com> (raw)
In-Reply-To: <20220107003756.806582-1-ben.widawsky@intel.com>
Needed for other things.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
drivers/cxl/core/port.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 29b0722dc6eb..5a1ffadd5d0d 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -666,7 +666,7 @@ static int match_port_by_dport(struct device *dev, const void *data)
return cxl_find_dport_by_dev(port, data) != NULL;
}
-static struct cxl_port *find_cxl_port(struct device *dport_dev)
+static struct cxl_port *dport_find_cxl_port(struct device *dport_dev)
{
struct device *port_dev;
@@ -699,7 +699,7 @@ struct cxl_port *find_cxl_root(struct cxl_memdev *cxlmd)
if (!dport_dev)
break;
- port = find_cxl_port(dport_dev);
+ port = dport_find_cxl_port(dport_dev);
if (!port)
continue;
@@ -728,7 +728,7 @@ static void cxl_remove_ep(void *data)
if (!dport_dev)
break;
- port = find_cxl_port(dport_dev);
+ port = dport_find_cxl_port(dport_dev);
if (!port || is_cxl_root(port))
continue;
@@ -787,7 +787,7 @@ static int add_port_register_ep(struct cxl_memdev *cxlmd,
resource_size_t component_reg_phys;
int rc;
- parent_port = find_cxl_port(grandparent(dport_dev));
+ parent_port = dport_find_cxl_port(grandparent(dport_dev));
if (!parent_port) {
/*
* The root CXL port is added by the CXL platform driver, fail
@@ -811,7 +811,7 @@ static int add_port_register_ep(struct cxl_memdev *cxlmd,
goto out;
}
- port = find_cxl_port(dport_dev);
+ port = dport_find_cxl_port(dport_dev);
if (!port) {
component_reg_phys = find_component_registers(uport_dev);
port = devm_cxl_add_port(&parent_port->dev, uport_dev,
@@ -876,7 +876,7 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd)
break;
}
- port = find_cxl_port(dport_dev);
+ port = dport_find_cxl_port(dport_dev);
if (port) {
dev_dbg(&cxlmd->dev,
"found already registered port %s:%s\n",
@@ -922,7 +922,7 @@ EXPORT_SYMBOL_NS_GPL(devm_cxl_enumerate_ports, CXL);
struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd)
{
- return find_cxl_port(grandparent(&cxlmd->dev));
+ return dport_find_cxl_port(grandparent(&cxlmd->dev));
}
EXPORT_SYMBOL_NS_GPL(cxl_mem_find_port, CXL);
--
2.34.1
next prev parent reply other threads:[~2022-01-07 0:38 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-07 0:37 [PATCH 00/13] CXL Region driver Ben Widawsky
2022-01-07 0:37 ` Ben Widawsky [this message]
2022-01-07 0:37 ` [PATCH 02/13] cxl/core: Track port depth Ben Widawsky
2022-01-07 0:37 ` [PATCH 03/13] cxl/region: Add region creation ABI Ben Widawsky
2022-01-07 0:37 ` [PATCH 04/13] cxl/region: Introduce concept of region configuration Ben Widawsky
2022-01-07 0:37 ` [PATCH 05/13] cxl/mem: Cache port created by the mem dev Ben Widawsky
2022-01-07 0:37 ` [PATCH 06/13] cxl/region: Introduce a cxl_region driver Ben Widawsky
2022-01-07 0:37 ` [PATCH 07/13] cxl/acpi: Handle address space allocation Ben Widawsky
2022-01-07 0:37 ` [PATCH 08/13] cxl/region: Address " Ben Widawsky
2022-01-07 0:37 ` [PATCH 09/13] cxl/region: Implement XHB verification Ben Widawsky
2022-01-07 10:07 ` Jonathan Cameron
2022-01-07 11:55 ` Jonathan Cameron
2022-01-11 22:47 ` Ben Widawsky
2022-01-07 10:30 ` Jonathan Cameron
2022-01-07 10:38 ` Jonathan Cameron
2022-01-07 16:32 ` Ben Widawsky
2022-01-11 21:32 ` Ben Widawsky
2022-01-07 0:37 ` [PATCH 10/13] cxl/region: HB port config verification Ben Widawsky
2022-01-07 0:37 ` [PATCH 11/13] cxl/region: Add infrastructure for decoder programming Ben Widawsky
2022-01-07 0:37 ` [PATCH 12/13] cxl/region: Record host bridge target list Ben Widawsky
2022-01-07 18:14 ` Jonathan Cameron
2022-01-07 19:20 ` Dan Williams
2022-01-07 0:37 ` [PATCH 13/13] cxl: Program decoders for regions Ben Widawsky
2022-01-07 16:18 ` Jonathan Cameron
2022-01-07 16:33 ` Ben Widawsky
2022-01-07 17:22 ` Jonathan Cameron
2022-01-11 0:05 ` Ben Widawsky
2022-01-12 14:53 ` Jonathan Cameron
2022-01-12 16:54 ` Ben Widawsky
2022-01-15 18:54 ` [PATCH 00/13] CXL Region driver Ben Widawsky
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