From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Ben Widawsky <ben.widawsky@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <linux-nvdimm@lists.01.org>,
<linux-pci@vger.kernel.org>, <patches@lists.linux.dev>,
Bjorn Helgaas <helgaas@kernel.org>,
Alison Schofield <alison.schofield@intel.com>,
"Dan Williams" <dan.j.williams@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
"Vishal Verma" <vishal.l.verma@intel.com>
Subject: Re: [PATCH 09/13] cxl/region: Implement XHB verification
Date: Fri, 7 Jan 2022 10:30:52 +0000 [thread overview]
Message-ID: <20220107103052.00006c4b@huawei.com> (raw)
In-Reply-To: <20220107003756.806582-10-ben.widawsky@intel.com>
On Thu, 6 Jan 2022 16:37:52 -0800
Ben Widawsky <ben.widawsky@intel.com> wrote:
> Cross host bridge verification primarily determines if the requested
> interleave ordering can be achieved by the root decoder, which isn't as
> programmable as other decoders.
>
> The algorithm implemented here is based on the CXL Type 3 Memory Device
> Software Guide, chapter 2.13.14
>
> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Trivial thing inline.
> diff --git a/drivers/cxl/region.c b/drivers/cxl/region.c
> index c8e3c48dfbb9..ca559a4b5347 100644
> --- a/drivers/cxl/region.c
> +++ b/drivers/cxl/region.c
> @@ -28,6 +28,17 @@
> */
>
> #define region_ways(region) ((region)->config.eniw)
> +#define region_ig(region) (ilog2((region)->config.ig))
> +
> +#define for_each_cxl_endpoint(ep, region, idx) \
> + for (idx = 0, ep = (region)->config.targets[idx]; \
> + idx < region_ways(region); \
> + idx++, ep = (region)->config.targets[idx])
> +
> +#define for_each_cxl_decoder_target(target, decoder, idx) \
> + for (idx = 0, target = (decoder)->target[idx]; \
As target is used too often in here, you'll replace it in ->target[idx] as well.
It happens to work today because the parameter always happens to be target
> + idx < (decoder)->nr_targets; \
> + idx++, target++)
>
next prev parent reply other threads:[~2022-01-07 10:30 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-07 0:37 [PATCH 00/13] CXL Region driver Ben Widawsky
2022-01-07 0:37 ` [PATCH 01/13] cxl/core: Rename find_cxl_port Ben Widawsky
2022-01-07 0:37 ` [PATCH 02/13] cxl/core: Track port depth Ben Widawsky
2022-01-07 0:37 ` [PATCH 03/13] cxl/region: Add region creation ABI Ben Widawsky
2022-01-07 0:37 ` [PATCH 04/13] cxl/region: Introduce concept of region configuration Ben Widawsky
2022-01-07 0:37 ` [PATCH 05/13] cxl/mem: Cache port created by the mem dev Ben Widawsky
2022-01-07 0:37 ` [PATCH 06/13] cxl/region: Introduce a cxl_region driver Ben Widawsky
2022-01-07 0:37 ` [PATCH 07/13] cxl/acpi: Handle address space allocation Ben Widawsky
2022-01-07 0:37 ` [PATCH 08/13] cxl/region: Address " Ben Widawsky
2022-01-07 0:37 ` [PATCH 09/13] cxl/region: Implement XHB verification Ben Widawsky
2022-01-07 10:07 ` Jonathan Cameron
2022-01-07 11:55 ` Jonathan Cameron
2022-01-11 22:47 ` Ben Widawsky
2022-01-07 10:30 ` Jonathan Cameron [this message]
2022-01-07 10:38 ` Jonathan Cameron
2022-01-07 16:32 ` Ben Widawsky
2022-01-11 21:32 ` Ben Widawsky
2022-01-07 0:37 ` [PATCH 10/13] cxl/region: HB port config verification Ben Widawsky
2022-01-07 0:37 ` [PATCH 11/13] cxl/region: Add infrastructure for decoder programming Ben Widawsky
2022-01-07 0:37 ` [PATCH 12/13] cxl/region: Record host bridge target list Ben Widawsky
2022-01-07 18:14 ` Jonathan Cameron
2022-01-07 19:20 ` Dan Williams
2022-01-07 0:37 ` [PATCH 13/13] cxl: Program decoders for regions Ben Widawsky
2022-01-07 16:18 ` Jonathan Cameron
2022-01-07 16:33 ` Ben Widawsky
2022-01-07 17:22 ` Jonathan Cameron
2022-01-11 0:05 ` Ben Widawsky
2022-01-12 14:53 ` Jonathan Cameron
2022-01-12 16:54 ` Ben Widawsky
2022-01-15 18:54 ` [PATCH 00/13] CXL Region driver Ben Widawsky
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